ADC_CTRL Simulation Results

Monday May 16 2022 08:22:13 UTC

GitHub Revision: `8d5fa645a`
Foundry Revision: `8d5fa645a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3018928693

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	20	20	100.00
		adc_ctrl_csr_aliasing	5	5	100.00
V1		TOTAL	105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	47	50	94.00
V2	alert_test	adc_ctrl_alert_test	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	5	5	100.00
		adc_ctrl_csr_rw	20	20	100.00
		adc_ctrl_csr_aliasing	5	5	100.00
		adc_ctrl_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	5	5	100.00
		adc_ctrl_csr_rw	20	20	100.00
		adc_ctrl_csr_aliasing	5	5	100.00
		adc_ctrl_same_csr_outstanding	20	20	100.00
V2		TOTAL	737	740	99.59
V2S	tl_intg_err	adc_ctrl_tl_intg_err	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	20	20	100.00
V2S		TOTAL	20	20	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	29	50	58.00
V3		TOTAL	29	50	58.00
		TOTAL	891	915	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	1	1	1	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	98.80	90.71	100.00	100.00	94.42	92.77	91.39

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 19 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 19 failures.
  - 1.adc_ctrl_stress_all_with_rand_reset.1198547789
    Line 173, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/out/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 17027188965 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 17027188965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.adc_ctrl_stress_all_with_rand_reset.3884702855
    Line 154, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/out/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 2225900198 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 2225900198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 17 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:408) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 3 failures:

Test adc_ctrl_stress_all has 3 failures.

2.adc_ctrl_stress_all.1246851936
Line 149, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/out/run.log

  UVM_ERROR @ 334019502348 ps: (adc_ctrl_scoreboard.sv:408) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 334019502348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.adc_ctrl_stress_all.2039345112
Line 165, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/27.adc_ctrl_stress_all/out/run.log

  UVM_ERROR @ 496269838617 ps: (adc_ctrl_scoreboard.sv:408) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 496269838617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

3.adc_ctrl_stress_all_with_rand_reset.753097809
Line 175, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/out/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.adc_ctrl_stress_all_with_rand_reset.1859626567
Line 151, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/out/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---