ADC_CTRL Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.960s	5.977ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.330s	1.097ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	522.138us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.698m	26.031ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.190s	778.602us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.930s	528.569us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	522.138us	20	20	100.00
		adc_ctrl_csr_aliasing	3.190s	778.602us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.474m	499.274ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.616m	494.085ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.965m	487.671ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.678m	492.571ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.576m	509.119ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.587m	498.245ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.425m	507.843ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	17.343m	489.582ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.040s	5.362ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.774m	45.838ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.357m	123.711ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	34.662m	764.279ms	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	1.850s	530.105us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.800s	472.653us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.640s	636.417us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.640s	636.417us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.330s	1.097ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	522.138us	20	20	100.00
		adc_ctrl_csr_aliasing	3.190s	778.602us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.640s	4.915ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.330s	1.097ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	522.138us	20	20	100.00
		adc_ctrl_csr_aliasing	3.190s	778.602us	5	5	100.00
		adc_ctrl_same_csr_outstanding	19.640s	4.915ms	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	tl_intg_err	adc_ctrl_sec_cm	9.940s	4.410ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.520s	8.469ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.520s	8.469ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.276m	568.954ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			891	920	96.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.47	99.01	95.70	100.00	100.00	98.18	98.64	90.80

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 24 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 24 failures.
  - 1.adc_ctrl_stress_all_with_rand_reset.1918130269
    Line 401, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 136905702025 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 136905702025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.adc_ctrl_stress_all_with_rand_reset.3729569711
    Line 314, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 1829563898 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 1829563898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 22 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 5 failures:

Test adc_ctrl_stress_all has 5 failures.

3.adc_ctrl_stress_all.2879675664
Line 328, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 322814836876 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 322814836876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.adc_ctrl_stress_all.2379491974
Line 327, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 337631260406 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 337631260406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.