ADC_CTRL Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.360s	5.943ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.890s	1.309ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.230s	547.281us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.757m	48.676ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.420s	1.007ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.020s	532.025us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.230s	547.281us	20	20	100.00
		adc_ctrl_csr_aliasing	3.420s	1.007ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	18.748m	494.175ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.207m	496.653ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.218m	497.137ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.144m	497.062ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.582m	492.686ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.838m	498.929ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.692m	489.557ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	19.556m	504.107ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.630s	5.598ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.858m	48.261ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	12.155m	144.029ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	32.265m	472.163ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.780s	495.502us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.850s	525.845us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.190s	500.375us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.190s	500.375us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.890s	1.309ms	5	5	100.00
		adc_ctrl_csr_rw	2.230s	547.281us	20	20	100.00
		adc_ctrl_csr_aliasing	3.420s	1.007ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.140s	4.567ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.890s	1.309ms	5	5	100.00
		adc_ctrl_csr_rw	2.230s	547.281us	20	20	100.00
		adc_ctrl_csr_aliasing	3.420s	1.007ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	20.140s	4.567ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	18.810s	7.773ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.700s	9.099ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.700s	9.099ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.599m	397.798ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			892	920	96.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.53	99.01	95.70	100.00	100.00	98.18	98.64	91.17

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 22 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.3661533745
    Line 400, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 33709917139 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 33709917139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.adc_ctrl_stress_all_with_rand_reset.158515399
    Line 427, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 141568345211 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 141568345211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 20 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 5 failures:

Test adc_ctrl_stress_all has 4 failures.

11.adc_ctrl_stress_all.903680392
Line 439, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 369256260526 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 369256260526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.adc_ctrl_stress_all.2964664826
Line 327, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/20.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 328664170585 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 328664170585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

40.adc_ctrl_stress_all_with_rand_reset.3333331758
Line 328, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 191138359362 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 191138359362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:135) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.adc_ctrl_stress_all_with_rand_reset.600167194
    Line 343, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73917520480 ps: (adc_ctrl_scoreboard.sv:135) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 73917520480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```