ADC_CTRL Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.000s 5.961ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 4.010s 1.358ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.090s 563.934us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 51.290s 14.277ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 3.230s 684.777us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.300s 631.232us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.090s 563.934us 20 20 100.00
adc_ctrl_csr_aliasing 3.230s 684.777us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 19.996m 487.515ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 19.030m 495.717ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 20.177m 497.588ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 19.550m 495.872ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 19.758m 494.293ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 18.470m 489.414ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 21.206m 512.126ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 18.562m 489.790ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 12.940s 5.296ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.818m 43.394ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.263m 144.051ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 31.395m 653.560ms 44 50 88.00
V2 alert_test adc_ctrl_alert_test 1.740s 514.365us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.860s 501.827us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 2.940s 581.886us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 2.940s 581.886us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 4.010s 1.358ms 5 5 100.00
adc_ctrl_csr_rw 2.090s 563.934us 20 20 100.00
adc_ctrl_csr_aliasing 3.230s 684.777us 5 5 100.00
adc_ctrl_same_csr_outstanding 18.860s 4.063ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 4.010s 1.358ms 5 5 100.00
adc_ctrl_csr_rw 2.090s 563.934us 20 20 100.00
adc_ctrl_csr_aliasing 3.230s 684.777us 5 5 100.00
adc_ctrl_same_csr_outstanding 18.860s 4.063ms 20 20 100.00
V2 TOTAL 734 740 99.19
V2S tl_intg_err adc_ctrl_sec_cm 17.690s 8.329ms 5 5 100.00
adc_ctrl_tl_intg_err 22.050s 8.573ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 22.050s 8.573ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 15.661m 1.574s 26 50 52.00
V3 TOTAL 26 50 52.00
TOTAL 890 920 96.74

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 15 93.75
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.50 99.01 95.70 100.00 100.00 98.18 98.64 90.97

Failure Buckets

Past Results