94eb0df12
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | adc_ctrl_smoke | 15.000s | 5.961ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | adc_ctrl_csr_hw_reset | 4.010s | 1.358ms | 5 | 5 | 100.00 |
V1 | csr_rw | adc_ctrl_csr_rw | 2.090s | 563.934us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | adc_ctrl_csr_bit_bash | 51.290s | 14.277ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | adc_ctrl_csr_aliasing | 3.230s | 684.777us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | adc_ctrl_csr_mem_rw_with_rand_reset | 2.300s | 631.232us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | adc_ctrl_csr_rw | 2.090s | 563.934us | 20 | 20 | 100.00 |
adc_ctrl_csr_aliasing | 3.230s | 684.777us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | filters_polled | adc_ctrl_filters_polled | 19.996m | 487.515ms | 50 | 50 | 100.00 |
V2 | filters_polled_fixed | adc_ctrl_filters_polled_fixed | 19.030m | 495.717ms | 50 | 50 | 100.00 |
V2 | filters_interrupt | adc_ctrl_filters_interrupt | 20.177m | 497.588ms | 50 | 50 | 100.00 |
V2 | filters_interrupt_fixed | adc_ctrl_filters_interrupt_fixed | 19.550m | 495.872ms | 50 | 50 | 100.00 |
V2 | filters_wakeup | adc_ctrl_filters_wakeup | 19.758m | 494.293ms | 50 | 50 | 100.00 |
V2 | filters_wakeup_fixed | adc_ctrl_filters_wakeup_fixed | 18.470m | 489.414ms | 50 | 50 | 100.00 |
V2 | filters_both | adc_ctrl_filters_both | 21.206m | 512.126ms | 50 | 50 | 100.00 |
V2 | clock_gating | adc_ctrl_clock_gating | 18.562m | 489.790ms | 50 | 50 | 100.00 |
V2 | poweron_counter | adc_ctrl_poweron_counter | 12.940s | 5.296ms | 50 | 50 | 100.00 |
V2 | lowpower_counter | adc_ctrl_lowpower_counter | 1.818m | 43.394ms | 50 | 50 | 100.00 |
V2 | fsm_reset | adc_ctrl_fsm_reset | 11.263m | 144.051ms | 50 | 50 | 100.00 |
V2 | stress_all | adc_ctrl_stress_all | 31.395m | 653.560ms | 44 | 50 | 88.00 |
V2 | alert_test | adc_ctrl_alert_test | 1.740s | 514.365us | 50 | 50 | 100.00 |
V2 | intr_test | adc_ctrl_intr_test | 1.860s | 501.827us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | adc_ctrl_tl_errors | 2.940s | 581.886us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | adc_ctrl_tl_errors | 2.940s | 581.886us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | adc_ctrl_csr_hw_reset | 4.010s | 1.358ms | 5 | 5 | 100.00 |
adc_ctrl_csr_rw | 2.090s | 563.934us | 20 | 20 | 100.00 | ||
adc_ctrl_csr_aliasing | 3.230s | 684.777us | 5 | 5 | 100.00 | ||
adc_ctrl_same_csr_outstanding | 18.860s | 4.063ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | adc_ctrl_csr_hw_reset | 4.010s | 1.358ms | 5 | 5 | 100.00 |
adc_ctrl_csr_rw | 2.090s | 563.934us | 20 | 20 | 100.00 | ||
adc_ctrl_csr_aliasing | 3.230s | 684.777us | 5 | 5 | 100.00 | ||
adc_ctrl_same_csr_outstanding | 18.860s | 4.063ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 734 | 740 | 99.19 | |||
V2S | tl_intg_err | adc_ctrl_sec_cm | 17.690s | 8.329ms | 5 | 5 | 100.00 |
adc_ctrl_tl_intg_err | 22.050s | 8.573ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | adc_ctrl_tl_intg_err | 22.050s | 8.573ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | adc_ctrl_stress_all_with_rand_reset | 15.661m | 1.574s | 26 | 50 | 52.00 |
V3 | TOTAL | 26 | 50 | 52.00 | |||
TOTAL | 890 | 920 | 96.74 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 16 | 16 | 15 | 93.75 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.50 | 99.01 | 95.70 | 100.00 | 100.00 | 98.18 | 98.64 | 90.97 |
Offending '(wakeup_time == cfg_wakeup_time)'
has 23 failures:
1.adc_ctrl_stress_all_with_rand_reset.3744950227
Line 346, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
Offending '(wakeup_time == cfg_wakeup_time)'
UVM_ERROR @ 59991041768 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
UVM_INFO @ 59991041768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.adc_ctrl_stress_all_with_rand_reset.2502688078
Line 353, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all_with_rand_reset/latest/run.log
Offending '(wakeup_time == cfg_wakeup_time)'
UVM_ERROR @ 34508191621 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
UVM_INFO @ 34508191621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
has 7 failures:
Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
3.adc_ctrl_stress_all_with_rand_reset.2607498859
Line 398, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/3.adc_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 506408227094 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 506408227094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test adc_ctrl_stress_all has 6 failures.
4.adc_ctrl_stress_all.3597854037
Line 328, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/4.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 327157784613 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 327157784613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.adc_ctrl_stress_all.1077004937
Line 329, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/30.adc_ctrl_stress_all/latest/run.log
UVM_ERROR @ 329967568416 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 329967568416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.