ADC_CTRL Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 15.990s 5.944ms 50 50 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 1.490s 1.235ms 5 5 100.00
V1 csr_rw adc_ctrl_csr_rw 2.070s 563.380us 20 20 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 1.791m 26.257ms 5 5 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 4.100s 901.588us 5 5 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.300s 606.033us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.070s 563.380us 20 20 100.00
adc_ctrl_csr_aliasing 4.100s 901.588us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 filters_polled adc_ctrl_filters_polled 20.056m 494.978ms 50 50 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 20.294m 493.583ms 50 50 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 18.744m 501.179ms 50 50 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 20.341m 490.852ms 50 50 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 20.651m 493.548ms 50 50 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 20.927m 501.041ms 50 50 100.00
V2 filters_both adc_ctrl_filters_both 19.877m 489.275ms 50 50 100.00
V2 clock_gating adc_ctrl_clock_gating 18.334m 490.580ms 50 50 100.00
V2 poweron_counter adc_ctrl_poweron_counter 13.340s 5.119ms 50 50 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.798m 46.601ms 50 50 100.00
V2 fsm_reset adc_ctrl_fsm_reset 11.854m 137.110ms 50 50 100.00
V2 stress_all adc_ctrl_stress_all 25.959m 597.844ms 43 50 86.00
V2 alert_test adc_ctrl_alert_test 1.800s 530.544us 50 50 100.00
V2 intr_test adc_ctrl_intr_test 1.840s 528.063us 50 50 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 2.980s 489.685us 20 20 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 2.980s 489.685us 20 20 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 1.490s 1.235ms 5 5 100.00
adc_ctrl_csr_rw 2.070s 563.380us 20 20 100.00
adc_ctrl_csr_aliasing 4.100s 901.588us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.370s 5.298ms 20 20 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 1.490s 1.235ms 5 5 100.00
adc_ctrl_csr_rw 2.070s 563.380us 20 20 100.00
adc_ctrl_csr_aliasing 4.100s 901.588us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.370s 5.298ms 20 20 100.00
V2 TOTAL 733 740 99.05
V2S tl_intg_err adc_ctrl_sec_cm 11.060s 4.635ms 5 5 100.00
adc_ctrl_tl_intg_err 24.100s 8.485ms 20 20 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 24.100s 8.485ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 6.299m 226.124ms 26 50 52.00
V3 TOTAL 26 50 52.00
TOTAL 889 920 96.63

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 16 15 93.75
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.49 99.01 95.70 100.00 100.00 98.18 98.64 90.90

Failure Buckets

Past Results