ADC_CTRL Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	15.530s	5.982ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.890s	1.018ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	553.695us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.010m	52.711ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.210s	1.072ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.180s	586.266us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	553.695us	20	20	100.00
		adc_ctrl_csr_aliasing	6.210s	1.072ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	20.488m	499.489ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.325m	507.097ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.812m	499.404ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.299m	492.392ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	19.623m	527.562ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	20.158m	496.101ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	20.051m	497.997ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.267m	493.915ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	14.260s	5.141ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.873m	45.655ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	11.948m	136.015ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	26.513m	621.800ms	44	50	88.00
V2	alert_test	adc_ctrl_alert_test	1.840s	503.551us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.870s	518.449us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.610s	504.415us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.610s	504.415us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.890s	1.018ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	553.695us	20	20	100.00
		adc_ctrl_csr_aliasing	6.210s	1.072ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.850s	4.763ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.890s	1.018ms	5	5	100.00
		adc_ctrl_csr_rw	2.020s	553.695us	20	20	100.00
		adc_ctrl_csr_aliasing	6.210s	1.072ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.850s	4.763ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	tl_intg_err	adc_ctrl_sec_cm	5.200s	4.543ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.650s	8.264ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.650s	8.264ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	9.950m	350.719ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			888	920	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.54	99.01	95.70	100.00	100.00	98.18	98.64	91.27

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 23 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.3704737981
    Line 355, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 12720205438 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 12720205438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 6.adc_ctrl_stress_all_with_rand_reset.2008234999
    Line 342, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/6.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 8860159235 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 8860159235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 21 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 9 failures:

Test adc_ctrl_stress_all has 6 failures.

0.adc_ctrl_stress_all.1659663016
Line 346, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 496207612763 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 496207612763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.adc_ctrl_stress_all.2694333016
Line 340, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/2.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 322431612676 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 322431612676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 3 failures.

11.adc_ctrl_stress_all_with_rand_reset.2380059615
Line 410, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/11.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 279634083399 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 279634083399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.adc_ctrl_stress_all_with_rand_reset.2458751755
Line 422, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/22.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 254419137419 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 254419137419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.