Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6624	1			T12	44		T18	20		T19	13
testmodes[AdcCtrlTestmodeNormal]	5032	1			T12	57		T14	1		T16	1
testmodes[AdcCtrlTestmodeLowpower]	5169	1			T12	62		T13	3		T15	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3699	1			T12	15		T18	19		T19	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1624	1			T12	13		T19	5		T20	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1189	1			T12	15		T94	21		T214	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1570	1			T12	8		T19	4		T20	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1856	1			T12	24		T19	1		T20	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1272	1			T12	25		T17	1		T19	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1235	1			T12	21		T94	21		T214	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1221	1			T12	19		T17	2		T24	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2472	1			T12	22		T13	2		T17	20