Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21187

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3113

1

T13

19

T17

11

T19

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18574

1

T6

1

T7

4

T25

1

auto[1]

5726

1

T12

2

T14

31

T15

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	347	1			T12	2		T17	1		T94	1
values[0]	21	1			T212	7		T213	14		-	-
values[1]	709	1			T24	2		T34	2		T135	1
values[2]	2757	1			T15	10		T16	11		T17	3
values[3]	649	1			T14	31		T24	13		T60	12
values[4]	622	1			T34	2		T111	1		T36	2
values[5]	496	1			T19	1		T24	6		T60	6
values[6]	476	1			T17	3		T91	7		T103	20
values[7]	725	1			T13	11		T104	21		T101	8
values[8]	601	1			T214	13		T127	1		T122	2
values[9]	1338	1			T13	8		T17	5		T19	10
minimum	15559	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	973	1			T24	2		T34	2		T95	1
values[1]	2662	1			T15	10		T16	11		T17	3
values[2]	599	1			T14	31		T24	13		T34	2
values[3]	714	1			T34	1		T111	1		T36	2
values[4]	407	1			T17	3		T19	1		T24	6
values[5]	528	1			T60	6		T95	1		T104	21
values[6]	684	1			T13	11		T214	13		T101	8
values[7]	636	1			T90	9		T111	1		T127	1
values[8]	958	1			T13	8		T17	5		T19	10
values[9]	229	1			T127	1		T110	35		T125	12
minimum	15910	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T34	1		T95	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T24	1		T112	4		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T15	10		T16	1		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	2		T105	1		T98	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	16		T24	6		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T96	9		T122	1		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T36	1		T134	1		T96	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	1		T111	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T19	1		T24	6		T91	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T17	1		T103	11		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T60	6		T104	11		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T95	1		T137	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T216	1		T156	3		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	11		T214	8		T101	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T90	8		T114	17		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T111	1		T127	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T36	1		T134	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	8		T17	3		T19	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T110	18		T125	1		T131	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T127	1		T218	3		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15763	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T34	1		T110	5		T220	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T24	1		T112	3		T113	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T16	10		T112	10		T107	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	1		T108	4		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	15		T24	7		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T215	14		T221	14		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T36	1		T134	9		T96	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T156	14		T141	7		T222	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T91	2		T223	6		T168	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T17	2		T103	9		T113	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T104	10		T224	6		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	15		T155	16		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T156	16		T225	12		T226	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T214	5		T223	14		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T90	1		T114	17		T117	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T114	2		T155	7		T131	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T36	1		T134	1		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	2		T19	2		T97	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T110	17		T125	11		T188	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T219	1		T227	14		T228	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	1		T7	4		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T12	2		T17	1		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T212	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T213	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	1		T135	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	1		T112	4		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T15	10		T16	1		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	2		T105	1		T98	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	16		T24	6		T60	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	1		T116	16		T221	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T34	1		T36	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T111	1		T96	9		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T19	1		T24	6		T60	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T34	1		T99	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T91	5		T109	1		T224	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T17	1		T103	11		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T104	11		T216	8		T156	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	11		T101	8		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T122	1		T114	17		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T214	8		T127	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T90	8		T36	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T13	8		T17	3		T19	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15426	1			T12	161		T17	19		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T125	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T212	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	1		T110	5		T220	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T24	1		T112	3		T113	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T16	10		T112	10		T107	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	1		T108	4		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	15		T24	7		T102	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T221	14		T142	11		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	1		T36	1		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T215	14		T156	14		T141	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T223	6		T117	10		T168	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T113	14		T222	4		T133	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T91	2		T224	6		T185	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	2		T103	9		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T104	10		T156	16		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T137	15		T155	16		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T114	17		T117	11		T225	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T214	5		T114	2		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T90	1		T36	1		T134	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T17	2		T19	2		T97	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T34	2		T95	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T24	2		T112	4		T113	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T15	1		T16	11		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	2		T105	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	16		T24	8		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T96	1		T122	1		T215	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T36	2		T134	10		T96	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	1		T111	1		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	1		T24	1		T91	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T17	3		T103	10		T113	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	1		T104	11		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T95	1		T137	16		T155	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T216	1		T156	17		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	1		T214	8		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T90	6		T114	18		T117	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T111	1		T127	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T36	2		T134	2		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	2		T17	4		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T110	18		T125	12		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T127	1		T218	2		T219	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15910	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T114	10		T110	2		T123	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T112	3		T216	11		T190	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	901	1			T15	9		T59	9		T60	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T98	14		T128	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	15		T24	5		T105	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T96	8		T230	14		T221	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T96	9		T150	12		T179	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T156	12		T222	7		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T24	5		T91	2		T101	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T103	10		T138	16		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T60	5		T104	10		T216	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T231	2		T54	12		T187	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T156	2		T182	15		T130	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	10		T214	5		T101	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T90	3		T114	16		T50	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T114	2		T155	9		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T98	7		T110	10		T138	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	6		T17	1		T19	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T110	17		T131	10		T232	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T218	1		T227	14		T228	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T12	2		T17	1		T94	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T212	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T213	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T34	2		T135	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T24	2		T112	4		T113	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T15	1		T16	11		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T17	2		T105	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	16		T24	8		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	1		T116	1		T221	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T34	2		T36	2		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T111	1		T96	1		T215	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	1		T24	1		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T34	1		T99	1		T113	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T91	5		T109	1		T224	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	3		T103	10		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T104	11		T216	1		T156	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	1		T101	1		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T122	1		T114	18		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T214	8		T127	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T90	6		T36	2		T134	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T13	2		T17	4		T19	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15559	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T213	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T114	10		T110	2		T123	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T112	3		T233	2		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T15	9		T59	9		T234	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T17	1		T98	14		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	15		T24	5		T60	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T116	15		T221	17		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T96	9		T105	16		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T96	8		T156	12		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	5		T60	5		T101	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T222	9		T133	1		T176	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T91	2		T224	6		T185	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T103	10		T223	9		T138	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T104	10		T216	7		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	10		T101	7		T156	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T114	16		T50	6		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T214	5		T114	2		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T90	3		T98	7		T110	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	6		T17	1		T19	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21137

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3163

1

T13

8

T14

31

T17

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18915

1

T6

1

T7

4

T25

1

auto[1]

5385

1

T14

31

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T235	1		-	-		-	-
values[0]	23	1			T157	1		T236	10		T237	2
values[1]	609	1			T24	2		T60	6		T98	15
values[2]	709	1			T17	3		T214	13		T95	1
values[3]	626	1			T60	12		T111	1		T127	2
values[4]	650	1			T99	1		T101	6		T128	3
values[5]	2561	1			T15	10		T16	11		T17	8
values[6]	667	1			T34	2		T134	10		T105	33
values[7]	581	1			T13	7		T19	10		T34	1
values[8]	805	1			T19	1		T103	20		T90	9
values[9]	1174	1			T13	12		T14	31		T24	6
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T60	6		T95	1		T98	15
values[1]	691	1			T24	2		T214	13		T104	21
values[2]	691	1			T17	3		T60	12		T111	1
values[3]	2686	1			T15	10		T16	11		T17	3
values[4]	570	1			T17	5		T95	1		T105	33
values[5]	641	1			T13	7		T34	2		T134	10
values[6]	590	1			T19	11		T34	1		T90	9
values[7]	740	1			T13	11		T103	20		T111	1
values[8]	942	1			T13	1		T14	31		T24	6
values[9]	92	1			T97	14		T117	11		T238	10
minimum	15904	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T98	15		T99	1		T179	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T60	6		T95	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	1		T214	8		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T108	4		T109	1		T140	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T111	1		T127	1		T114	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	1		T60	12		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T15	10		T16	1		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	2		T24	6		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T17	3		T95	1		T101	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T105	17		T112	4		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	1		T97	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	7		T134	1		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	9		T90	8		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	1		T36	1		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	11		T103	11		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T111	1		T134	1		T114	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T60	13		T96	9		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T14	16		T24	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T97	1		T117	1		T238	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T240	1		T241	14		T242	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15771	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T220	4		T221	6		T188	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T175	4		T110	17		T215	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T24	1		T214	5		T104	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T108	3		T190	10		T155	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T114	2		T220	12		T221	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	2		T239	1		T238	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1092	1			T16	10		T107	20		T243	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	1		T24	7		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	2		T124	3		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T105	16		T112	3		T136	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	1		T97	11		T125	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T134	9		T96	8		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T19	2		T90	1		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T36	1		T137	15		T155	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T103	9		T112	10		T113	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T134	1		T114	17		T155	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T102	13		T108	1		T110	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	15		T91	2		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T97	13		T117	10		T238	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T241	19		T242	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T157	1		T212	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T236	1		T237	2		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T24	1		T98	15		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	6		T100	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T214	8		T104	11		T100	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	1		T95	1		T108	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T111	1		T127	2		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T60	12		T140	3		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T101	6		T109	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T99	1		T128	3		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T15	10		T16	1		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	2		T24	6		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	1		T97	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T134	1		T105	17		T114	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	8		T36	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	7		T34	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T19	1		T103	11		T90	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T111	1		T134	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T13	11		T60	13		T96	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	1		T14	16		T24	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T212	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T236	9		T246	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T24	1		T221	6		T188	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T110	17		T215	9		T156	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T214	5		T104	10		T100	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	2		T108	3		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T114	2		T221	14		T247	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T239	1		T156	16		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T117	4		T233	8		T220	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T233	2		T225	12		T186	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T16	10		T17	2		T107	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	1		T24	7		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	1		T97	11		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T134	9		T105	16		T136	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T19	2		T36	1		T112	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	1		T137	15		T156	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T103	9		T90	1		T96	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	1		T114	17		T155	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T97	13		T102	13		T108	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	15		T91	2		T244	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1