Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20665

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3635

1

T13

19

T17

11

T24

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18386

1

T6

1

T7

4

T25

1

auto[1]

5914

1

T13

11

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	64	1			T104	21		T315	26		T316	3
values[0]	79	1			T134	10		T100	1		T115	1
values[1]	474	1			T17	3		T19	1		T24	6
values[2]	646	1			T14	31		T60	6		T95	1
values[3]	728	1			T13	1		T214	13		T34	1
values[4]	583	1			T13	11		T36	2		T99	1
values[5]	710	1			T17	5		T96	9		T97	14
values[6]	510	1			T17	3		T60	13		T223	15
values[7]	563	1			T24	2		T99	1		T101	6
values[8]	2754	1			T13	7		T15	10		T16	11
values[9]	1295	1			T19	10		T24	13		T60	12
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T17	3		T24	6		T111	1
values[1]	689	1			T14	31		T19	1		T60	6
values[2]	557	1			T13	1		T214	13		T34	1
values[3]	763	1			T13	11		T17	5		T36	2
values[4]	574	1			T60	13		T96	9		T97	14
values[5]	540	1			T17	3		T108	7		T136	2
values[6]	2705	1			T15	10		T16	11		T22	1
values[7]	716	1			T13	7		T60	12		T34	2
values[8]	836	1			T24	13		T91	7		T95	2
values[9]	306	1			T19	10		T116	10		T110	8
minimum	15906	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T100	1		T115	1		T140	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	1		T24	6		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	16		T19	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T60	6		T135	1		T98	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T116	16		T117	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T214	8		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	1		T113	1		T108	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	11		T17	3		T112	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T97	1		T109	1		T224	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T60	13		T96	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T108	4		T230	12		T238	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	2		T136	1		T216	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T15	10		T16	1		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T24	1		T34	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T60	12		T96	10		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	7		T34	1		T90	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	6		T91	5		T95	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T105	17		T127	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T19	8		T116	10		T190	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T110	3		T185	15		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15770	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T110	3		T155	2		T185	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	2		T134	9		T125	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	15		T97	11		T233	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T233	2		T125	10		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T117	4		T124	3		T292	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T214	5		T103	9		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T36	1		T113	9		T108	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	2		T112	13		T137	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T97	13		T224	6		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T96	8		T117	11		T222	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T108	3		T238	8		T247	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	1		T136	1		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T16	10		T107	20		T243	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T24	1		T34	1		T137	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T96	13		T221	6		T257	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T34	1		T90	1		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T24	7		T91	2		T134	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T105	16		T100	8		T114	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T19	2		T190	10		T304	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T110	5		T185	10		T304	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	1		T7	4		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T104	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T315	12		T316	3		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T100	1		T115	1		T217	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T134	1		T318	1		T319	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T19	1		T140	3		T110	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	1		T24	6		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	16		T95	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	6		T98	8		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T98	15		T116	16		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	1		T214	8		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	1		T108	6		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	11		T99	1		T128	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T97	1		T113	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T17	3		T96	1		T112	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T230	12		T231	3		T238	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	2		T60	13		T223	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T99	1		T102	15		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T24	1		T101	6		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T15	10		T16	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	7		T34	2		T90	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T19	8		T24	6		T60	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T105	17		T127	1		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T104	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T315	14		T317	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T51	3		T207	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T134	9		T319	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T110	3		T155	2		T185	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T17	2		T125	3		T320	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	15		T97	11		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T168	4		T182	1		T130	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T239	1		T124	3		T186	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T214	5		T103	9		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	1		T108	4		T117	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T137	14		T141	12		T188	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T97	13		T113	9		T175	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	2		T96	8		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T238	8		T258	9		T290	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T17	1		T223	6		T215	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T102	13		T108	3		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	1		T136	1		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T16	10		T96	13		T107	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T34	2		T90	1		T223	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T19	2		T24	7		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T105	16		T100	8		T114	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T100	1		T115	1		T140	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	3		T24	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	16		T19	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	1		T135	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T116	1		T117	5		T124	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T214	8		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T36	2		T113	10		T108	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T17	4		T112	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T97	14		T109	1		T224	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T60	1		T96	9		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	4		T230	1		T238	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	2		T136	2		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T15	1		T16	11		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T24	2		T34	2		T137	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T60	1		T96	14		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	1		T34	2		T90	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	8		T91	5		T95	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T105	17		T127	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T19	3		T116	1		T190	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T110	6		T185	11		T304	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15903	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T110	10		T155	2		T217	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	5		T54	12		T57	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	15		T96	8		T98	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T60	5		T98	7		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T116	15		T176	3		T312	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T214	5		T103	10		T216	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T108	4		T155	7		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	10		T17	1		T112	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T224	6		T257	4		T251	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T60	12		T114	10		T230	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T108	3		T230	11		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	1		T216	7		T223	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T15	9		T59	9		T234	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T155	14		T156	17		T248	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T60	11		T96	9		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	6		T90	3		T101	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	5		T91	2		T104	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T105	16		T100	9		T114	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T19	7		T116	9		T190	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T110	2		T185	14		T218	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T51	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T104	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T315	15		T316	1		T317	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T100	1		T115	1		T217	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T134	10		T318	1		T319	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	1		T140	3		T110	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	3		T24	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	16		T95	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	1		T98	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T98	1		T116	1		T239	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T13	1		T214	8		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T36	2		T108	6		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	1		T99	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T97	14		T113	10		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T17	4		T96	9		T112	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T230	1		T231	1		T238	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	2		T60	1		T223	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T99	1		T102	14		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T24	2		T101	1		T136	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1461	1			T15	1		T16	11		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	1		T34	4		T90	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T19	3		T24	8		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	444	1			T105	17		T127	1		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T104	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T315	11		T316	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T217	11		T51	3		T207	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T319	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T110	10		T155	2		T185	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T24	5		T54	12		T252	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	15		T96	8		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T60	5		T98	7		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T98	14		T116	15		T303	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T214	5		T103	10		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T108	4		T155	7		T156	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	10		T128	2		T216	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T224	6		T257	4		T251	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	1		T112	3		T114	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T230	11		T231	2		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T17	1		T60	12		T223	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T102	14		T150	12		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T101	5		T216	7		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T15	9		T59	9		T234	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	6		T90	3		T223	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T19	7		T24	5		T60	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T105	16		T100	9		T114	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9