Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21028

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3272

1

T13

18

T17

11

T19

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18754

1

T6

1

T7

4

T25

1

auto[1]

5546

1

T13

11

T14

31

T15

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T95	1		T229	11		T321	1
values[0]	140	1			T24	2		T103	20		T95	1
values[1]	625	1			T214	13		T34	2		T95	1
values[2]	890	1			T17	8		T34	1		T111	1
values[3]	646	1			T60	13		T91	7		T104	21
values[4]	2530	1			T13	11		T15	10		T16	11
values[5]	628	1			T13	1		T14	31		T19	1
values[6]	512	1			T60	6		T111	1		T135	1
values[7]	523	1			T24	6		T122	1		T109	2
values[8]	653	1			T13	7		T17	3		T60	12
values[9]	1243	1			T19	10		T24	13		T36	2
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1029	1			T17	8		T24	2		T214	13
values[1]	769	1			T60	13		T91	7		T98	8
values[2]	569	1			T104	21		T99	1		T122	1
values[3]	2601	1			T13	11		T14	31		T15	10
values[4]	653	1			T13	1		T90	9		T111	1
values[5]	497	1			T24	6		T60	6		T135	1
values[6]	510	1			T60	12		T122	1		T109	2
values[7]	767	1			T13	7		T17	3		T19	10
values[8]	768	1			T24	13		T95	1		T96	9
values[9]	215	1			T36	2		T136	2		T215	5
minimum	15922	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T214	8		T95	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T17	4		T24	1		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T114	17		T128	3		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T60	13		T91	5		T98	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T104	11		T99	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T122	1		T155	15		T231	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T14	16		T15	10		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	11		T34	1		T96	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T111	1		T114	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T90	8		T114	11		T108	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	6		T135	1		T105	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	6		T97	1		T108	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T60	12		T122	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T109	1		T110	11		T155	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T134	1		T112	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	7		T17	2		T19	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	6		T96	1		T150	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T95	1		T127	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T258	3		T322	1		T158	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T36	1		T136	1		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15774	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T177	13		T323	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T214	5		T113	9		T117	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T17	4		T24	1		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T114	17		T233	2		T125	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T91	2		T100	8		T108	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T104	10		T175	4		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T155	17		T238	5		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1129	1			T14	15		T16	10		T134	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T34	1		T112	3		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T114	2		T244	2		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T90	1		T108	1		T110	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T105	16		T187	17		T324	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T97	13		T108	4		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T224	6		T223	6		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T110	3		T155	5		T185	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T134	9		T112	10		T113	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	1		T19	2		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T24	7		T96	8		T215	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T110	5		T117	10		T141	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T258	9		T158	16		T325	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T36	1		T136	1		T215	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T229	1		T321	1		T245	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T95	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T95	1		T156	13		T299	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T24	1		T103	11		T326	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T214	8		T105	1		T98	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T34	1		T95	1		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T111	1		T115	1		T233	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	4		T34	1		T98	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T104	11		T114	17		T128	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T60	13		T91	5		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T15	10		T16	1		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T13	11		T216	8		T238	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T14	16		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T34	1		T90	8		T96	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T111	1		T135	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T60	6		T97	1		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T24	6		T122	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T109	1		T110	11		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T60	12		T112	1		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	7		T17	2		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T24	6		T134	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T19	8		T36	1		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T229	10		T245	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T156	14		T299	14		T327	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T24	1		T103	9		T326	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T214	5		T113	9		T117	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	1		T36	1		T97	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T233	2		T125	3		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T17	4		T108	3		T190	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T104	10		T114	17		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T91	2		T155	17		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T16	10		T107	20		T243	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T238	5		T141	12		T328	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	15		T134	1		T96	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T34	1		T90	1		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T114	2		T185	6		T292	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T97	13		T108	4		T110	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T223	6		T125	11		T257	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T110	3		T155	5		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T112	10		T224	6		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	1		T137	14		T298	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T24	7		T134	9		T96	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T19	2		T36	1		T102	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T214	8		T95	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T17	7		T24	2		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T114	18		T128	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T60	1		T91	5		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T104	11		T99	1		T175	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T122	1		T155	18		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1470	1			T14	16		T15	1		T16	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	1		T34	2		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T111	1		T114	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T90	6		T114	1		T108	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	1		T135	1		T105	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T60	1		T97	14		T108	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T60	1		T122	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T109	1		T110	4		T155	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T134	10		T112	11		T113	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	1		T17	2		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T24	8		T96	9		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T95	1		T127	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T258	10		T322	1		T158	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T36	2		T136	2		T215	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15895	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T177	1		T323	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T214	5		T98	14		T156	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	1		T103	10		T190	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T114	16		T128	2		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T60	12		T91	2		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T104	10		T51	3		T264	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T155	14		T231	2		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	910	1			T14	15		T15	9		T59	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	10		T96	8		T112	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T114	2		T101	7		T116	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T90	3		T114	10		T110	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T24	5		T105	16		T116	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T60	5		T108	4		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T60	11		T216	11		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T110	10		T155	7		T185	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T223	9		T138	16		T179	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	6		T17	1		T19	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T24	5		T150	12		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T110	2		T142	13		T218	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T258	2		T158	15		T325	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T145	1		T291	12		T242	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T54	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T177	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T229	11		T321	1		T245	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T95	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T95	1		T156	15		T299	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T24	2		T103	10		T326	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T214	8		T105	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T34	2		T95	1		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T111	1		T115	1		T233	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	7		T34	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T104	11		T114	18		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T60	1		T91	5		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T15	1		T16	11		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	1		T216	1		T238	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	1		T14	16		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	2		T90	6		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T111	1		T135	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T60	1		T97	14		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	1		T122	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T109	1		T110	4		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T60	1		T112	11		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	1		T17	2		T140	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T24	8		T134	10		T96	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T19	3		T36	2		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T156	12		T299	15		T329	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T103	10		T326	11		T145	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T214	5		T98	14		T230	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T100	9		T156	2		T251	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T233	2		T231	8		T185	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	1		T98	7		T108	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T104	10		T114	16		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T60	12		T91	2		T101	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	885	1			T15	9		T59	9		T234	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T13	10		T216	7		T238	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	15		T96	9		T105	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T90	3		T96	8		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T114	2		T116	24		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T60	5		T108	4		T110	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T24	5		T216	11		T223	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T110	10		T155	7		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T60	11		T224	6		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	6		T17	1		T138	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T24	5		T150	12		T217	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T19	7		T102	14		T110	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9