Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21165

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3135

1

T13

19

T19

10

T24

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18611

1

T6

1

T7

4

T25

1

auto[1]

5689

1

T12

2

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	609	1			T12	2		T13	1		T17	6
values[0]	24	1			T135	1		T212	7		T330	16
values[1]	744	1			T24	2		T34	2		T112	7
values[2]	2734	1			T15	10		T16	11		T17	3
values[3]	662	1			T14	31		T24	13		T60	12
values[4]	590	1			T34	2		T111	1		T36	2
values[5]	471	1			T19	1		T24	6		T34	1
values[6]	497	1			T17	3		T60	6		T91	7
values[7]	703	1			T13	11		T104	21		T101	8
values[8]	654	1			T214	13		T127	1		T122	2
values[9]	1053	1			T13	7		T19	10		T60	13
minimum	15559	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	720	1			T24	2		T34	2		T135	1
values[1]	2638	1			T15	10		T16	11		T17	3
values[2]	597	1			T14	31		T24	13		T34	2
values[3]	734	1			T34	1		T111	1		T36	2
values[4]	419	1			T17	3		T19	1		T24	6
values[5]	492	1			T60	6		T95	1		T104	21
values[6]	706	1			T13	11		T214	13		T101	8
values[7]	639	1			T111	1		T127	1		T122	2
values[8]	1075	1			T13	8		T17	5		T19	10
values[9]	118	1			T127	1		T131	11		T188	4
minimum	16162	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T34	1		T135	1		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T24	1		T112	4		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T15	10		T16	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T105	1		T99	1		T128	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	16		T24	6		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T96	9		T122	1		T102	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	1		T134	1		T96	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T34	1		T111	1		T105	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	1		T19	1		T24	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T113	1		T101	7		T223	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	6		T104	11		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T95	1		T216	8		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T156	18		T230	12		T226	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	11		T214	8		T101	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T111	1		T114	17		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T127	1		T122	2		T114	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T17	3		T36	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	8		T19	8		T60	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T131	11		T188	1		T232	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T127	1		T331	1		T332	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15812	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T270	1		T220	1		T292	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T34	1		T110	5		T221	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T24	1		T112	3		T113	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T16	10		T17	1		T112	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T108	4		T175	4		T155	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	15		T24	7		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T102	13		T215	14		T142	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T36	1		T134	9		T96	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T105	16		T156	14		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T17	2		T91	2		T103	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T113	14		T223	6		T133	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T104	10		T224	6		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T137	15		T129	9		T131	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T156	15		T226	2		T182	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T214	5		T223	14		T155	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T114	17		T155	2		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T114	2		T117	11		T155	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T17	2		T36	1		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T19	2		T90	1		T134	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T188	3		T232	10		T310	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T332	4		T219	1		T228	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T220	4		T292	10		T326	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T12	2		T17	4		T94	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T13	1		T254	1		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T135	1		T212	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T330	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T34	1		T100	1		T114	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T24	1		T112	4		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T15	10		T16	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T105	1		T128	3		T108	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	16		T24	6		T60	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T99	1		T122	1		T102	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	1		T36	1		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T111	1		T96	9		T105	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	1		T24	6		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T34	1		T99	1		T101	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	1		T60	6		T91	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T95	1		T113	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T104	11		T156	18		T230	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	11		T101	8		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T114	17		T155	3		T215	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T214	8		T127	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T111	1		T36	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T13	7		T19	8		T60	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15426	1			T12	161		T17	19		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T17	2		T125	11		T220	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T141	12		T332	4		T306	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T212	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T330	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T34	1		T110	5		T124	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T24	1		T112	3		T113	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T16	10		T17	1		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T108	4		T175	4		T190	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	15		T24	7		T137	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T102	13		T142	11		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	1		T36	1		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T105	16		T215	14		T156	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T117	10		T304	23		T271	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T223	6		T222	4		T133	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T17	2		T91	2		T103	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T113	14		T137	15		T129	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T104	10		T156	15		T226	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T223	14		T155	16		T156	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T114	17		T155	2		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T214	5		T114	2		T117	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T36	1		T96	8		T97	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T19	2		T90	1		T134	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T34	2		T135	1		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T24	2		T112	4		T113	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T15	1		T16	11		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T105	1		T99	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	16		T24	8		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T96	1		T122	1		T102	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T36	2		T134	10		T96	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	1		T111	1		T105	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	3		T19	1		T24	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T113	15		T101	2		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	1		T104	11		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T95	1		T216	1		T137	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T156	16		T230	1		T226	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T214	8		T101	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T111	1		T114	18		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T127	1		T122	2		T114	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T17	4		T36	2		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T13	2		T19	3		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T131	1		T188	4		T232	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T127	1		T331	1		T332	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15998	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T270	1		T220	5		T292	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T114	10		T110	2		T123	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T112	3		T216	11		T190	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T15	9		T17	1		T59	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T128	2		T108	4		T155	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	15		T24	5		T230	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T96	8		T102	14		T116	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T96	9		T150	12		T179	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T105	16		T156	12		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T24	5		T91	2		T103	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T101	5		T223	8		T133	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T60	5		T104	10		T224	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T216	7		T231	2		T131	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T156	17		T230	11		T182	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	10		T214	5		T101	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T114	16		T155	2		T50	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T114	2		T155	7		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T17	1		T98	7		T110	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	6		T19	7		T60	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T131	10		T232	9		T207	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T332	1		T228	4		T177	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T217	7		T181	15		T145	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T326	11		T148	11		T213	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	447	1			T12	2		T17	5		T94	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T13	1		T254	1		T141	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T135	1		T212	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T330	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T34	2		T100	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T24	2		T112	4		T113	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T15	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T105	1		T128	1		T108	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T14	16		T24	8		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T99	1		T122	1		T102	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T34	2		T36	2		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T111	1		T96	1		T105	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	1		T24	1		T117	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T34	1		T99	1		T101	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	3		T60	1		T91	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T95	1		T113	15		T137	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T104	11		T156	16		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T101	1		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T114	18		T155	3		T215	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T214	8		T127	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T111	1		T36	2		T96	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T13	1		T19	3		T60	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15559	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T17	1		T248	10		T287	25
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T332	1		T306	1		T228	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T114	10		T110	2		T123	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T112	3		T233	2		T262	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	918	1			T15	9		T17	1		T59	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T128	2		T108	4		T216	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	15		T24	5		T60	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T102	14		T116	15		T142	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T96	9		T150	12		T230	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T96	8		T105	16		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T24	5		T54	2		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T101	5		T223	8		T222	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T60	5		T91	2		T103	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T231	2		T290	7		T148	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T104	10		T156	17		T230	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	10		T101	7		T216	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T114	16		T155	2		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T214	5		T114	2		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T98	7		T110	10		T138	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T13	6		T19	7		T60	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9