Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21073

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T13

8

T14

31

T17

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18712

1

T6

1

T7

4

T25

1

auto[1]

5588

1

T14

31

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T91	7		T96	9		T97	14
values[0]	21	1			T157	1		T236	10		T212	7
values[1]	579	1			T60	6		T95	1		T98	15
values[2]	759	1			T17	3		T24	2		T214	13
values[3]	640	1			T60	12		T111	1		T127	1
values[4]	586	1			T127	1		T99	1		T101	6
values[5]	2610	1			T15	10		T16	11		T17	8
values[6]	650	1			T34	2		T134	10		T96	9
values[7]	537	1			T13	7		T19	10		T34	1
values[8]	896	1			T19	1		T103	20		T90	9
values[9]	899	1			T13	12		T14	31		T24	6
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	549	1			T95	1		T98	15		T100	1
values[1]	704	1			T17	3		T24	2		T214	13
values[2]	748	1			T60	12		T111	1		T127	1
values[3]	2659	1			T15	10		T16	11		T17	3
values[4]	534	1			T17	5		T95	1		T105	33
values[5]	680	1			T13	7		T34	2		T134	10
values[6]	570	1			T19	11		T34	1		T90	9
values[7]	724	1			T103	20		T95	1		T111	1
values[8]	984	1			T13	11		T14	31		T24	6
values[9]	73	1			T13	1		T97	14		T50	7
minimum	16075	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T98	15		T179	3		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T95	1		T100	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T24	1		T214	8		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T17	1		T108	4		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T127	1		T114	3		T101	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T60	12		T111	1		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T15	10		T16	1		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	2		T24	6		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	3		T101	9		T124	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T95	1		T105	17		T112	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T34	1		T96	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	7		T134	1		T224	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	8		T90	8		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	1		T34	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T103	11		T95	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T111	1		T134	1		T114	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T13	11		T60	13		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	16		T24	6		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T97	1		T50	7		T185	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T13	1		T176	4		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15814	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T60	6		T215	1		T236	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T220	4		T188	3		T189	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T175	4		T110	17		T156	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	1		T214	5		T104	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	2		T108	3		T190	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T114	2		T239	1		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T238	8		T141	12		T257	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T16	10		T107	20		T243	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	1		T24	7		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	2		T124	13		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T105	16		T112	3		T136	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	1		T96	8		T97	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	9		T224	6		T155	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	2		T90	1		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T36	1		T113	9		T137	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T103	9		T112	10		T113	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T134	1		T114	17		T155	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T102	13		T108	1		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	15		T91	2		T223	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T97	13		T185	4		T242	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T315	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T215	9		T236	9		T240	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T96	9		T97	1		T216	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T91	5		T122	1		T109	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T157	1		T212	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T236	1		T245	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T98	15		T99	1		T179	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T60	6		T95	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	1		T214	8		T104	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	1		T108	4		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T127	1		T122	1		T114	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T60	12		T111	1		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T127	1		T101	6		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T99	1		T128	3		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T15	10		T16	1		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	2		T24	6		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	1		T96	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	1		T105	17		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	8		T36	1		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	7		T34	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T103	11		T90	8		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T19	1		T111	1		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T13	11		T60	13		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	1		T14	16		T24	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T97	13		T185	4		T189	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T91	2		T271	6		T315	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T212	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T236	9		T246	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T221	6		T188	3		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T110	17		T215	9		T156	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T24	1		T214	5		T104	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	2		T108	3		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T114	2		T239	1		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T238	8		T141	12		T131	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T117	4		T233	8		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T233	2		T225	12		T186	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1100	1			T16	10		T17	2		T107	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T17	1		T24	7		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T96	8		T97	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T134	9		T105	16		T136	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T19	2		T36	1		T108	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T36	1		T113	9		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T103	9		T90	1		T96	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	1		T114	17		T155	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T102	13		T108	1		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	15		T223	6		T51	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T98	1		T179	1		T220	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T95	1		T100	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	2		T214	8		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T17	3		T108	4		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T127	1		T114	3		T101	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T60	1		T111	1		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T15	1		T16	11		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T17	2		T24	8		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T17	4		T101	2		T124	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T95	1		T105	17		T112	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	2		T96	9		T97	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T134	10		T224	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	3		T90	6		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T19	1		T34	1		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T103	10		T95	1		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T111	1		T134	2		T114	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T13	1		T60	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	16		T24	1		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T97	14		T50	1		T185	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T13	1		T176	1		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15935	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T60	1		T215	10		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T98	14		T179	2		T189	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T110	17		T156	12		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T214	5		T104	10		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T108	3		T190	12		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T114	2		T101	5		T221	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T60	11		T238	9		T257	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	880	1			T15	9		T59	9		T234	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	1		T24	5		T128	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T17	1		T101	7		T180	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T105	16		T112	3		T223	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T114	10		T54	2		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	6		T224	6		T155	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	7		T90	3		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T150	12		T216	7		T230	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T103	10		T98	7		T217	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T114	16		T116	9		T216	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	10		T60	12		T96	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T14	15		T24	5		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T50	6		T185	4		T242	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T176	3		T315	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T221	4		T264	8		T333	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T60	5		T330	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T96	1		T97	14		T216	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T91	5		T122	1		T109	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T157	1		T212	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T236	10		T245	1		T246	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T98	1		T99	1		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	1		T95	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	2		T214	8		T104	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	3		T108	4		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T127	1		T122	1		T114	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T60	1		T111	1		T140	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T127	1		T101	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T99	1		T128	1		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T15	1		T16	11		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	2		T24	8		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T34	2		T96	9		T97	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T134	10		T105	17		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T19	3		T36	2		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	1		T34	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T103	10		T90	6		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T19	1		T111	1		T134	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T13	1		T60	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	1		T14	16		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T96	8		T50	6		T185	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T91	2		T176	3		T271	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T98	14		T179	2		T221	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T60	5		T110	17		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T214	5		T104	10		T100	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T108	3		T190	12		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T114	2		T221	17		T251	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T60	11		T238	9		T131	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T101	5		T248	10		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T128	2		T233	2		T57	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	876	1			T15	9		T17	1		T59	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	1		T24	5		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T114	10		T54	2		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T105	16		T224	6		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T19	7		T108	4		T230	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	6		T156	17		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T103	10		T90	3		T96	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T114	16		T150	12		T116	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	10		T60	12		T102	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	15		T24	5		T223	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9