Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21071

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3229

1

T13

18

T14

31

T17

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18683

1

T6

1

T7

4

T25

1

auto[1]

5617

1

T13

1

T14

31

T15

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	211	1			T111	1		T223	15		T233	5
values[0]	37	1			T280	8		T253	7		T261	8
values[1]	731	1			T17	3		T60	13		T34	1
values[2]	621	1			T13	1		T19	1		T104	21
values[3]	533	1			T36	2		T98	15		T114	45
values[4]	712	1			T113	15		T122	1		T102	28
values[5]	2717	1			T13	11		T15	10		T16	11
values[6]	671	1			T13	7		T19	10		T95	1
values[7]	885	1			T14	31		T17	5		T24	13
values[8]	555	1			T96	9		T112	7		T99	1
values[9]	733	1			T17	3		T60	6		T91	7
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	675	1			T17	3		T60	13		T34	1
values[1]	598	1			T13	1		T19	1		T104	21
values[2]	587	1			T36	2		T98	15		T114	34
values[3]	2799	1			T13	11		T15	10		T16	11
values[4]	688	1			T24	8		T60	12		T34	2
values[5]	696	1			T13	7		T14	31		T19	10
values[6]	772	1			T17	5		T24	13		T214	13
values[7]	577	1			T91	7		T96	9		T112	7
values[8]	664	1			T17	3		T60	6		T95	1
values[9]	120	1			T115	1		T217	8		T238	18
minimum	16124	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	1		T60	13		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T95	1		T134	1		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T98	8		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	1		T104	11		T114	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T36	1		T216	1		T110	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T98	15		T114	17		T102	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T15	10		T16	1		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	11		T122	1		T101	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	6		T34	1		T103	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T24	1		T60	12		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T19	8		T100	10		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	7		T14	16		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T17	3		T214	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T24	6		T90	8		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T91	5		T96	9		T112	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T101	8		T109	1		T155	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T60	6		T134	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	2		T95	1		T111	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T238	10		T54	3		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T115	1		T217	8		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15805	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T150	13		T223	10		T217	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	2		T105	16		T97	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T134	1		T136	1		T141	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T257	5		T255	1		T200	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T104	10		T137	15		T156	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T36	1		T110	5		T117	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	17		T102	13		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T16	10		T113	14		T107	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	15		T124	10		T168	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T34	1		T103	9		T233	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	1		T112	10		T238	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T19	2		T100	8		T215	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	15		T96	13		T108	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	2		T214	5		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T24	7		T90	1		T113	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T91	2		T112	3		T114	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T155	17		T220	4		T182	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T134	9		T97	13		T223	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T17	1		T36	1		T108	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T238	8		T291	14		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T173	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T223	14		T232	6		T312	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T223	9		T233	3		T254	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T111	1		T217	8		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T280	8		T253	7		T323	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T261	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T17	1		T60	13		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T95	1		T134	1		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T105	17		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T19	1		T104	11		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T36	1		T110	3		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T98	15		T114	28		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T113	1		T216	9		T110	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T122	1		T102	15		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T15	10		T16	1		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	11		T24	1		T60	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	8		T135	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	7		T95	1		T96	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T17	3		T214	8		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	16		T24	6		T90	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T96	9		T112	4		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T101	8		T109	1		T230	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T60	6		T91	5		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	2		T95	1		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T223	6		T233	2		T238	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T272	6		T237	15		T259	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T260	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T261	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	2		T175	4		T110	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T134	1		T136	1		T223	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T105	16		T97	11		T185	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T104	10		T137	15		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T36	1		T110	5		T117	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T114	17		T137	14		T239	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T113	14		T110	17		T155	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T102	13		T244	2		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T16	10		T34	1		T103	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T24	1		T112	10		T124	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T19	2		T100	8		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T96	13		T108	3		T225	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T17	2		T214	5		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	15		T24	7		T90	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T112	3		T114	2		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T182	20		T248	10		T207	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T91	2		T134	9		T97	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	1		T36	1		T108	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T17	3		T60	1		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T95	1		T134	2		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T98	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T19	1		T104	11		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T36	2		T216	1		T110	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T98	1		T114	18		T102	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T15	1		T16	11		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T122	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	1		T34	2		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T24	2		T60	1		T112	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T19	3		T100	9		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T13	1		T14	16		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T17	4		T214	8		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	8		T90	6		T113	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T91	5		T96	1		T112	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T101	1		T109	1		T155	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T60	1		T134	10		T97	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T17	2		T95	1		T111	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T238	9		T54	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T115	1		T217	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15943	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T150	1		T223	15		T217	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T60	12		T105	16		T116	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T217	11		T142	13		T187	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T98	7		T138	5		T257	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T104	10		T114	10		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T110	2		T230	16		T231	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T98	14		T114	16		T102	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T15	9		T59	9		T234	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	10		T101	5		T156	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T24	5		T103	10		T123	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T60	11		T238	4		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	7		T100	9		T216	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	6		T14	15		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	1		T214	5		T54	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T24	5		T90	3		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T91	2		T96	8		T112	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T101	7		T155	14		T182	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	5		T223	8		T233	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T17	1		T128	2		T108	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T238	9		T54	2		T291	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T217	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T221	4		T334	9		T280	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T150	12		T223	9		T232	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T223	7		T233	3		T254	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T111	1		T217	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T280	1		T253	1		T323	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	3		T60	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T95	1		T134	2		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T105	17		T97	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T19	1		T104	11		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T36	2		T110	6		T117	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T98	1		T114	19		T137	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T113	15		T216	2		T110	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T122	1		T102	14		T244	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T15	1		T16	11		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	1		T24	2		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T19	3		T135	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	1		T95	1		T96	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T17	4		T214	8		T34	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	16		T24	8		T90	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T96	1		T112	4		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T101	1		T109	1		T230	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T60	1		T91	5		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T17	2		T95	1		T111	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T223	8		T233	2		T238	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T217	7		T237	8		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T280	7		T253	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T60	12		T116	15		T110	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T150	12		T223	9		T217	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T105	16		T98	7		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T104	10		T156	12		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T110	2		T231	2		T298	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T98	14		T114	26		T54	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T216	7		T110	17		T155	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T102	14		T156	17		T168	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T15	9		T24	5		T59	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	10		T60	11		T101	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T19	7		T100	9		T263	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	6		T96	9		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	1		T214	5		T216	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	15		T24	5		T90	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T96	8		T112	3		T114	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T101	7		T230	14		T182	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T60	5		T91	2		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T17	1		T128	2		T108	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9