Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21024

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3276

1

T13

18

T17

11

T19

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18754

1

T6

1

T7

4

T25

1

auto[1]

5546

1

T13

11

T14

31

T15

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T95	1		T36	2		T215	10
values[0]	63	1			T299	30		T335	25		T336	8
values[1]	734	1			T17	3		T24	2		T214	13
values[2]	871	1			T17	5		T34	1		T111	1
values[3]	612	1			T60	13		T91	7		T104	21
values[4]	2549	1			T13	11		T14	31		T15	10
values[5]	626	1			T13	1		T19	1		T34	2
values[6]	558	1			T60	6		T111	1		T135	1
values[7]	498	1			T24	6		T122	1		T109	2
values[8]	636	1			T17	3		T60	12		T134	10
values[9]	1028	1			T13	7		T19	10		T24	13
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	797	1			T17	8		T24	2		T214	13
values[1]	805	1			T60	13		T91	7		T98	8
values[2]	596	1			T104	21		T99	1		T122	1
values[3]	2550	1			T13	11		T14	31		T15	10
values[4]	653	1			T13	1		T19	1		T90	9
values[5]	549	1			T24	6		T60	6		T111	1
values[6]	489	1			T60	12		T122	1		T109	2
values[7]	713	1			T13	7		T17	3		T19	10
values[8]	884	1			T24	13		T95	1		T96	9
values[9]	138	1			T36	2		T215	5		T182	2
minimum	16126	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T214	8		T95	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	4		T24	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T114	17		T128	3		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T60	13		T91	5		T98	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T104	11		T99	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T122	1		T101	6		T155	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T14	16		T15	10		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	11		T34	1		T96	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T19	1		T114	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T90	8		T114	11		T108	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	6		T111	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	6		T97	1		T108	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	12		T122	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T109	1		T110	11		T155	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T134	1		T112	1		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	7		T17	2		T19	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	6		T96	1		T150	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T95	1		T127	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T258	3		T322	1		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T36	1		T215	1		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15814	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T34	1		T97	1		T101	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T214	5		T113	9		T117	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T17	4		T24	1		T103	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T114	17		T233	2		T125	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T91	2		T108	3		T190	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T104	10		T175	4		T225	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	17		T238	5		T141	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T14	15		T16	10		T134	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T34	1		T112	3		T130	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T114	2		T244	2		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T90	1		T108	1		T110	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T105	16		T185	6		T187	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T97	13		T108	4		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T224	6		T223	6		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T110	3		T155	5		T185	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T134	9		T112	10		T113	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	1		T19	2		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T24	7		T96	8		T215	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T136	1		T110	5		T117	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T258	9		T245	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T36	1		T215	4		T182	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T34	1		T97	11		T220	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T215	1		T187	12		T188	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T95	1		T36	1		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T299	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T335	14		T336	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T214	8		T95	1		T98	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T17	1		T24	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T111	1		T105	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T17	3		T34	1		T98	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T104	11		T114	17		T128	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T60	13		T91	5		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T14	16		T15	10		T16	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T13	11		T112	4		T216	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T19	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T34	1		T90	8		T96	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T111	1		T135	1		T105	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T60	6		T97	1		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T24	6		T122	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T109	1		T110	11		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	12		T134	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	2		T140	3		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T24	6		T96	1		T113	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T13	7		T19	8		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T215	9		T187	14		T188	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T36	1		T182	1		T310	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T299	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T335	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T214	5		T113	9		T117	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T17	2		T24	1		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T233	2		T125	3		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	2		T108	3		T190	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T104	10		T114	17		T225	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T91	2		T155	17		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1136	1			T14	15		T16	10		T107	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T112	3		T238	5		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T134	1		T96	13		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T34	1		T90	1		T108	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T105	16		T114	2		T185	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T97	13		T108	4		T238	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T223	6		T125	11		T257	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T110	3		T155	5		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T134	9		T112	10		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	1		T137	14		T180	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T24	7		T96	8		T113	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T19	2		T102	13		T136	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T214	8		T95	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	7		T24	2		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T114	18		T128	1		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T60	1		T91	5		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T104	11		T99	1		T175	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T122	1		T101	1		T155	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T14	16		T15	1		T16	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	1		T34	2		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	1		T19	1		T114	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T90	6		T114	1		T108	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	1		T111	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T60	1		T97	14		T108	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T60	1		T122	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T109	1		T110	4		T155	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T134	10		T112	11		T113	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T17	2		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T24	8		T96	9		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T95	1		T127	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T258	10		T322	1		T245	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T36	2		T215	5		T182	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15920	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T34	2		T97	12		T101	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T214	5		T185	14		T130	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	1		T103	10		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T114	16		T128	2		T233	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T60	12		T91	2		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T104	10		T262	14		T51	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T101	5		T155	14		T231	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T14	15		T15	9		T59	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	10		T96	8		T112	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T114	2		T101	7		T116	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T90	3		T114	10		T110	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	5		T105	16		T116	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T60	5		T108	4		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T60	11		T216	11		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T110	10		T155	7		T185	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T223	9		T138	16		T179	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	6		T17	1		T19	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T24	5		T150	12		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T110	2		T142	13		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T258	2		T177	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T332	1		T291	12		T242	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T98	14		T156	12		T54	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T251	11		T302	10		T335	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T215	10		T187	15		T188	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T95	1		T36	2		T182	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T299	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T335	15		T336	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T214	8		T95	1		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T17	3		T24	2		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T111	1		T105	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	4		T34	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T104	11		T114	18		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T60	1		T91	5		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T14	16		T15	1		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	1		T112	4		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	1		T19	1		T134	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T34	2		T90	6		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T111	1		T135	1		T105	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T60	1		T97	14		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	1		T122	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T109	1		T110	4		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T60	1		T134	10		T112	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	2		T140	3		T137	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T24	8		T96	9		T113	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T13	1		T19	3		T127	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T187	11		T337	8		T325	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T332	1		T338	7		T159	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T299	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T335	10		T336	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T214	5		T98	14		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T103	10		T100	9		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T233	2		T230	27		T231	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	1		T98	7		T108	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T104	10		T114	16		T128	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T60	12		T91	2		T101	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	897	1			T14	15		T15	9		T59	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T13	10		T112	3		T216	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T96	9		T101	7		T116	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T90	3		T96	8		T114	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T105	16		T114	2		T116	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T60	5		T108	4		T238	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T24	5		T216	11		T223	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T110	10		T155	7		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T60	11		T224	6		T223	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	1		T138	5		T180	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T24	5		T150	12		T217	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	6		T19	7		T102	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9