Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19297

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

5003

1

T13

8

T14

31

T15

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18783

1

T6

1

T7

4

T25

1

auto[1]

5517

1

T13

18

T14

31

T15

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	221	1			T135	1		T155	13		T185	9
values[0]	34	1			T96	9		T304	4		T339	8
values[1]	666	1			T24	2		T60	12		T90	9
values[2]	559	1			T13	7		T95	1		T134	12
values[3]	628	1			T34	2		T99	1		T113	15
values[4]	530	1			T13	1		T17	3		T19	10
values[5]	722	1			T14	31		T17	3		T24	6
values[6]	588	1			T13	11		T214	13		T34	1
values[7]	673	1			T60	19		T34	2		T91	7
values[8]	603	1			T36	2		T112	11		T108	7
values[9]	3182	1			T15	10		T16	11		T17	5
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T60	12		T90	9		T95	1
values[1]	2482	1			T13	7		T15	10		T16	11
values[2]	561	1			T34	2		T99	1		T113	15
values[3]	619	1			T13	1		T17	6		T19	10
values[4]	701	1			T14	31		T24	6		T127	1
values[5]	677	1			T13	11		T60	6		T214	13
values[6]	677	1			T60	13		T91	7		T36	4
values[7]	639	1			T17	5		T95	1		T112	11
values[8]	984	1			T19	1		T24	13		T95	1
values[9]	142	1			T135	1		T97	14		T155	13
minimum	16133	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T60	12		T90	8		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T95	1		T134	1		T105	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T122	1		T216	8		T155	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1247	1			T13	7		T15	10		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T34	1		T113	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T99	1		T247	2		T298	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T17	3		T96	10		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T19	8		T103	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T24	6		T127	1		T114	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	16		T109	1		T216	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	11		T60	6		T214	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T102	15		T176	10		T340	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	1		T99	1		T114	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T60	13		T91	5		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T95	1		T110	11		T224	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	3		T112	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T24	6		T95	1		T111	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T19	1		T104	11		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T135	1		T97	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T155	8		T222	5		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15802	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T101	6		T236	1		T248	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T90	1		T134	1		T113	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T134	9		T105	16		T114	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T155	2		T124	10		T186	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1082	1			T16	10		T97	11		T107	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	1		T113	14		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T247	4		T298	3		T258	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	3		T96	13		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T19	2		T103	9		T96	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T114	17		T223	14		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	15		T215	14		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T214	5		T34	1		T112	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T102	13		T158	19		T274	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	1		T108	1		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T91	2		T36	1		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T110	3		T224	6		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	2		T112	10		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T24	7		T244	2		T220	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T104	10		T100	8		T117	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T97	13		T142	6		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T155	5		T249	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T236	9		T248	23		T300	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T135	1		T157	1		T186	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T155	8		T185	5		T222	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T96	9		T304	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T339	8		T301	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	1		T60	12		T90	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T105	17		T99	1		T114	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T134	1		T122	1		T116	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	7		T95	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T34	1		T113	1		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T99	1		T123	10		T231	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T17	2		T96	10		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	1		T19	8		T103	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T17	1		T24	6		T114	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	16		T127	1		T101	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	11		T214	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T109	1		T216	12		T176	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T60	6		T34	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T60	13		T91	5		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T36	1		T116	10		T110	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T112	1		T108	4		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T24	6		T95	2		T111	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1353	1			T15	10		T16	1		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T142	11		T158	11		T232	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T155	5		T185	4		T332	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T301	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T24	1		T90	1		T113	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T105	16		T114	2		T155	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T134	1		T155	19		T186	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T134	9		T97	11		T137	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T34	1		T113	14		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T247	4		T298	3		T258	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	1		T96	13		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T19	2		T103	9		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	2		T114	17		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	15		T108	4		T136	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T214	5		T112	3		T117	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T158	19		T337	9		T274	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	1		T108	1		T110	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T91	2		T36	1		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T36	1		T110	3		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T112	10		T108	3		T117	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T24	7		T97	13		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1255	1			T16	10		T17	2		T104	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T60	1		T90	6		T134	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T95	1		T134	10		T105	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T122	1		T216	1		T155	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1417	1			T13	1		T15	1		T16	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T34	2		T113	15		T175	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T99	1		T247	6		T298	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	5		T96	14		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T19	3		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T24	1		T127	1		T114	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	16		T109	1		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	1		T60	1		T214	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T102	14		T176	1		T340	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T36	2		T99	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T60	1		T91	5		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T95	1		T110	4		T224	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	4		T112	11		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T24	8		T95	1		T111	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T19	1		T104	11		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T135	1		T97	14		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T155	6		T222	3		T249	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15946	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T101	1		T236	10		T248	25
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T60	11		T90	3		T96	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T105	16		T114	2		T231	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T216	7		T155	2		T54	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	912	1			T13	6		T15	9		T59	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T233	2		T217	7		T179	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T298	2		T258	2		T299	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T17	1		T96	9		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	7		T103	10		T101	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	5		T114	16		T223	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T14	15		T216	11		T251	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	10		T60	5		T214	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T102	14		T176	9		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T114	10		T116	9		T110	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T60	12		T91	2		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T110	10		T224	6		T156	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T17	1		T230	11		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	5		T98	14		T142	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T104	10		T100	9		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T303	7		T142	13		T158	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T155	7		T222	2		T249	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T238	9		T148	8		T341	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T101	5		T248	20		T339	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T135	1		T157	1		T186	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T155	6		T185	5		T222	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T96	1		T304	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T339	1		T301	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	2		T60	1		T90	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T105	17		T99	1		T114	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T134	2		T122	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T95	1		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T34	2		T113	15		T175	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T99	1		T123	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	2		T96	14		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	1		T19	3		T103	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T17	3		T24	1		T114	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	16		T127	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T214	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T109	1		T216	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T60	1		T34	2		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	1		T91	5		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	2		T116	1		T110	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T112	11		T108	4		T117	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T24	8		T95	2		T111	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1609	1			T15	1		T16	11		T17	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T303	7		T142	13		T158	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T155	7		T185	4		T222	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T96	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T339	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T60	11		T90	3		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T105	16		T114	2		T101	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T116	15		T216	7		T155	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	6		T150	12		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T233	2		T217	7		T179	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T123	9		T231	8		T264	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T17	1		T96	9		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T19	7		T103	10		T110	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T24	5		T114	16		T223	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	15		T101	7		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	10		T214	5		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T216	11		T176	9		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	5		T114	10		T110	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T60	12		T91	2		T102	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T116	9		T110	10		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T108	3		T230	11		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T24	5		T98	14		T156	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	999	1			T15	9		T17	1		T59	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9