Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T98	1		T99	1		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T60	1		T95	1		T100	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T24	2		T214	8		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T108	4		T109	1		T140	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T111	1		T127	1		T114	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T17	3		T60	1		T239	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T15	1		T16	11		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	2		T24	8		T34	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T17	4		T95	1		T101	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T105	17		T112	4		T136	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T34	2		T97	12		T125	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	1		T134	10		T96	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T19	4		T90	6		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T34	1		T36	2		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	1		T103	10		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T111	1		T134	2		T114	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T60	1		T96	1		T99	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	1		T14	16		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T97	14		T117	11		T238	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T240	1		T241	20		T242	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15895	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T98	14		T179	2		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	5		T110	17		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T214	5		T104	10		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T108	3		T190	12		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T114	2		T101	5		T221	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T60	11		T238	9		T57	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T15	9		T59	9		T234	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	1		T24	5		T128	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T17	1		T101	7		T180	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T105	16		T112	3		T223	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T182	15		T187	11		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	6		T114	10		T224	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T19	7		T90	3		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T150	12		T216	7		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	10		T103	10		T98	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T114	16		T216	11		T155	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T60	12		T96	8		T102	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	15		T24	5		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T238	4		T189	1		T249	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T241	13		T242	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T250	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T235	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T157	1		T212	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T236	10		T237	2		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	2		T98	1		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T60	1		T100	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T214	8		T104	11		T100	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	3		T95	1		T108	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T111	1		T127	2		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T60	1		T140	3		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T101	1		T109	1		T117	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T99	1		T128	1		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T15	1		T16	11		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	2		T24	8		T34	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T34	2		T97	12		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T134	10		T105	17		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	3		T36	2		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T34	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T19	1		T103	10		T90	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T111	1		T134	2		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T13	1		T60	1		T96	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T13	1		T14	16		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T98	14		T221	4		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T60	5		T110	17		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T214	5		T104	10		T100	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T108	3		T190	12		T138	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T114	2		T221	17		T251	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T60	11		T156	2		T238	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T101	5		T248	10		T252	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T128	2		T233	2		T54	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	859	1			T15	9		T17	1		T59	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T17	1		T24	5		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T248	10		T158	11		T207	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T105	16		T114	10		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	7		T108	4		T230	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	6		T156	17		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T103	10		T90	3		T96	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T114	16		T150	12		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T13	10		T60	12		T96	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	15		T24	5		T91	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9