Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21089

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3211

1

T13

11

T17

3

T19

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18789

1

T6

1

T7

4

T25

1

auto[1]

5511

1

T13

18

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T265	1		T266	2		-	-
values[0]	89	1			T182	14		T267	1		T148	12
values[1]	708	1			T19	1		T24	2		T60	6
values[2]	2670	1			T15	10		T16	11		T17	3
values[3]	661	1			T13	11		T19	10		T95	1
values[4]	595	1			T17	3		T36	2		T112	7
values[5]	721	1			T127	2		T98	15		T122	2
values[6]	598	1			T24	13		T34	1		T96	9
values[7]	654	1			T214	13		T34	2		T134	10
values[8]	673	1			T13	8		T14	31		T60	12
values[9]	1034	1			T17	5		T60	13		T91	7
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	988	1			T19	1		T24	2		T34	2
values[1]	2724	1			T15	10		T16	11		T17	3
values[2]	552	1			T13	11		T17	3		T36	2
values[3]	598	1			T127	1		T99	1		T122	1
values[4]	700	1			T112	7		T127	1		T98	15
values[5]	581	1			T24	13		T34	1		T96	9
values[6]	820	1			T14	31		T60	12		T214	13
values[7]	630	1			T13	8		T91	7		T135	1
values[8]	700	1			T17	5		T90	9		T95	2
values[9]	103	1			T60	13		T268	1		T269	5
minimum	15904	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T105	17		T115	1		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T19	1		T24	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T15	10		T16	1		T19	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	2		T24	6		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	1		T36	1		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	11		T270	1		T248	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T239	1		T179	3		T231	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T127	1		T99	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T112	4		T98	15		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T127	1		T122	1		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	1		T224	7		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	6		T96	1		T116	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	16		T60	12		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T214	8		T34	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	8		T91	5		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T136	1		T216	8		T54	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T17	3		T95	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T90	8		T95	1		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T60	13		T268	1		T271	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T269	3		T188	1		T272	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15770	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T105	16		T225	12		T141	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T24	1		T34	1		T103	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T16	10		T19	2		T96	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T17	1		T104	10		T108	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T17	2		T36	1		T110	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T248	10		T189	2		T272	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T239	1		T258	9		T207	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T108	4		T110	3		T137	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T112	3		T113	14		T190	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T102	13		T137	14		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T224	6		T233	2		T215	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T24	7		T96	8		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	15		T134	9		T97	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T214	5		T34	1		T97	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T91	2		T113	9		T117	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T136	1		T142	11		T273	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T17	2		T36	1		T134	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T90	1		T220	11		T222	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T271	6		T274	4		T275	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T269	2		T188	3		T272	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	1		T7	4		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T266	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T267	1		T276	1		T277	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T182	8		T148	12		T278	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T60	6		T105	17		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	1		T24	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T15	10		T16	1		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	2		T24	6		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T19	8		T95	1		T98	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	11		T108	6		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	1		T36	1		T112	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T99	1		T108	7		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T98	15		T114	11		T128	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T127	2		T122	2		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T34	1		T113	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	6		T96	1		T102	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T134	1		T112	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T214	8		T34	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	8		T14	16		T60	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T136	1		T54	9		T57	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T17	3		T60	13		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T90	8		T95	1		T105	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T276	1		T277	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T182	6		T278	20		T261	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T105	16		T225	12		T141	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T24	1		T34	1		T103	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T16	10		T96	13		T107	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	1		T104	10		T114	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T19	2		T110	17		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T108	4		T279	6		T189	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	2		T36	1		T112	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T108	4		T233	8		T155	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T190	10		T223	6		T124	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T110	3		T137	29		T125	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T113	14		T220	4		T186	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	7		T96	8		T102	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T134	9		T112	10		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T214	5		T34	1		T97	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	15		T97	11		T113	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T136	1		T186	6		T247	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T17	2		T91	2		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T90	1		T220	11		T222	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T105	17		T115	1		T225	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T19	1		T24	2		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T15	1		T16	11		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	2		T24	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	3		T36	2		T99	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T270	1		T248	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T239	2		T179	1		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T127	1		T99	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T112	4		T98	1		T113	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T127	1		T122	1		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	1		T224	7		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	8		T96	9		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T14	16		T60	1		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T214	8		T34	2		T97	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	2		T91	5		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T136	2		T216	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T17	4		T95	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T90	6		T95	1		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T60	1		T268	1		T271	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T269	3		T188	4		T272	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15898	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T105	16		T222	2		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T103	10		T96	8		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T15	9		T19	7		T59	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T17	1		T24	5		T104	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T110	17		T262	14		T50	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T13	10		T248	10		T189	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T179	2		T231	8		T130	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T101	5		T108	3		T110	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T112	3		T98	14		T114	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T102	14		T123	9		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T224	6		T233	2		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T24	5		T116	15		T110	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	15		T60	11		T223	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T214	5		T155	14		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	6		T91	2		T138	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T216	7		T54	8		T142	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	1		T155	2		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T90	3		T101	7		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T60	12		T271	6		T280	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T281	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T265	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T266	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T267	1		T276	2		T277	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T182	7		T148	1		T278	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T60	1		T105	17		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	1		T24	2		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T15	1		T16	11		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T17	2		T24	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T19	3		T95	1		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T108	6		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	3		T36	2		T112	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T99	1		T108	8		T233	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T98	1		T114	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T127	2		T122	2		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	1		T113	15		T220	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T24	8		T96	9		T102	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T134	10		T112	11		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T214	8		T34	2		T97	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	2		T14	16		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T136	2		T54	1		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T17	4		T60	1		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T90	6		T95	1		T105	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T266	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T277	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T182	7		T148	11		T278	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T60	5		T105	16		T222	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T103	10		T100	9		T116	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	886	1			T15	9		T59	9		T234	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	1		T24	5		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	7		T98	7		T110	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	10		T108	4		T131	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T112	3		T179	2		T54	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T108	3		T155	7		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T98	14		T114	10		T128	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T101	5		T110	10		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T131	14		T282	2		T219	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T24	5		T102	14		T116	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T224	6		T223	9		T233	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T214	5		T231	2		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	6		T14	15		T60	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T54	8		T57	7		T133	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T17	1		T60	12		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T90	3		T101	7		T216	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9