Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21083

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3217

1

T13

7

T17

6

T60

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19080

1

T6

1

T7

4

T25

1

auto[1]

5220

1

T13

11

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	260	1			T36	2		T134	10		T114	34
values[0]	21	1			T54	13		T283	8		-	-
values[1]	607	1			T24	6		T190	23		T137	15
values[2]	585	1			T24	15		T91	7		T97	14
values[3]	673	1			T13	1		T60	6		T90	9
values[4]	553	1			T34	1		T95	1		T122	1
values[5]	770	1			T214	13		T104	21		T99	1
values[6]	708	1			T13	11		T14	31		T111	1
values[7]	475	1			T17	5		T19	1		T60	13
values[8]	614	1			T17	6		T34	2		T95	1
values[9]	3140	1			T13	7		T15	10		T16	11
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	593	1			T97	14		T244	3		T190	23
values[1]	607	1			T13	1		T24	15		T91	7
values[2]	687	1			T60	6		T90	9		T95	1
values[3]	569	1			T34	1		T122	1		T101	6
values[4]	828	1			T111	1		T104	21		T96	23
values[5]	583	1			T13	11		T14	31		T19	1
values[6]	2469	1			T15	10		T16	11		T17	5
values[7]	723	1			T17	6		T34	2		T103	20
values[8]	981	1			T13	7		T19	10		T60	12
values[9]	207	1			T114	34		T117	5		T155	13
minimum	16053	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T97	1		T244	1		T156	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T190	13		T137	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T24	7		T91	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T101	1		T102	15		T216	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T90	8		T95	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T60	6		T109	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T101	6		T150	13		T138	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T34	1		T122	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T111	1		T96	10		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T104	11		T108	4		T223	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	11		T14	16		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T96	1		T136	1		T175	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T15	10		T16	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T60	13		T36	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T111	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	3		T103	11		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T19	8		T134	1		T114	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T13	7		T60	12		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T117	1		T200	1		T277	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T114	17		T155	8		T238	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15811	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T54	13		T142	14		T284	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T97	13		T244	2		T156	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T190	10		T137	14		T215	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T24	8		T91	2		T155	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T102	13		T110	17		T239	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T90	1		T117	10		T215	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T225	12		T221	12		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T142	6		T188	2		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T117	11		T233	2		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T96	13		T110	3		T233	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T104	10		T108	3		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	15		T214	5		T108	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T96	8		T136	1		T175	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T16	10		T17	2		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	1		T97	11		T112	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T34	1		T134	1		T105	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	3		T103	9		T113	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T19	2		T134	9		T108	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	1		T36	1		T113	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T117	4		T200	12		T277	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T114	17		T155	5		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T142	11		T284	5		T285	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T134	1		T216	12		T286	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T36	1		T114	17		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T54	13		T283	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T24	6		T156	3		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T190	13		T137	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	7		T91	5		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T101	1		T216	8		T110	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T90	8		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T60	6		T102	15		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T95	1		T150	13		T54	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T34	1		T122	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T214	8		T99	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T104	11		T108	4		T223	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	11		T14	16		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T175	1		T223	10		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	3		T19	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T60	13		T36	1		T96	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	1		T95	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T17	3		T113	1		T114	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T15	10		T16	1		T19	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T13	7		T60	12		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T134	9		T200	12		T237	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T36	1		T114	17		T137	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T156	16		T185	4		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T190	10		T137	14		T215	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	8		T91	2		T97	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T110	17		T239	1		T51	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T90	1		T117	10		T155	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T102	13		T215	9		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T248	13		T189	2		T271	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T117	11		T225	12		T226	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T214	5		T110	3		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T104	10		T108	3		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	15		T96	13		T108	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T175	4		T223	14		T155	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	2		T112	10		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	1		T96	8		T97	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	1		T134	1		T105	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	3		T113	9		T114	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T16	10		T19	2		T107	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T34	1		T103	9		T113	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T97	14		T244	3		T156	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T190	11		T137	15		T215	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T24	10		T91	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T101	1		T102	14		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T90	6		T95	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	1		T109	1		T225	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T101	1		T150	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T34	1		T122	1		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T111	1		T96	14		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T104	11		T108	4		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	1		T14	16		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T96	9		T136	2		T175	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T15	1		T16	11		T17	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T60	1		T36	2		T97	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T34	2		T111	1		T134	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T17	5		T103	10		T113	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T19	3		T134	10		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T13	1		T60	1		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T117	5		T200	13		T277	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T114	18		T155	6		T238	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15945	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T54	1		T142	12		T284	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T156	2		T54	8		T185	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T190	12		T51	3		T185	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T24	5		T91	2		T98	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T102	14		T216	7		T110	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T90	3		T156	17		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T60	5		T221	10		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T101	5		T150	12		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T233	2		T287	10		T189	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T96	9		T128	2		T116	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T104	10		T108	3		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	10		T14	15		T214	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T223	9		T155	2		T222	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	856	1			T15	9		T17	1		T59	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T60	12		T112	3		T288	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T105	16		T230	14		T258	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T103	10		T100	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T19	7		T114	10		T108	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	6		T60	11		T96	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T277	7		T289	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T114	16		T155	7		T238	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T24	5		T187	11		T269	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T54	12		T142	13		T285	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T134	10		T216	1		T286	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T36	2		T114	18		T137	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T54	1		T283	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	1		T156	17		T254	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T190	11		T137	15		T215	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T24	10		T91	5		T97	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T101	1		T216	1		T110	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	1		T90	6		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T60	1		T102	14		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T95	1		T150	1		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	1		T122	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T214	8		T99	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T104	11		T108	4		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T14	16		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T175	5		T223	15		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	4		T19	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	1		T36	2		T96	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	2		T95	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	5		T113	10		T114	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T15	1		T16	11		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	1		T60	1		T34	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T216	11		T237	3		T161	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T114	16		T155	7		T131	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T54	12		T283	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T24	5		T156	2		T54	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T190	12		T185	14		T182	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T24	5		T91	2		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T216	7		T110	17		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T90	3		T156	17		T217	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T60	5		T102	14		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T150	12		T54	2		T131	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T221	10		T248	5		T189	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T214	5		T101	5		T116	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T104	10		T108	3		T223	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	10		T14	15		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T223	9		T155	2		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T17	1		T98	14		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T60	12		T112	3		T288	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T105	16		T230	14		T248	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T17	1		T114	2		T110	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T15	9		T19	7		T59	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T13	6		T60	11		T103	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9