Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21110

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3190

1

T13

7

T17

6

T60

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19033

1

T6

1

T7

4

T25

1

auto[1]

5267

1

T13

11

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T224	13		T251	14		T176	11
values[0]	29	1			T215	5		T290	16		T283	8
values[1]	602	1			T24	6		T190	23		T137	15
values[2]	570	1			T24	15		T91	7		T97	14
values[3]	666	1			T13	1		T60	6		T90	9
values[4]	531	1			T34	1		T95	1		T122	2
values[5]	805	1			T214	13		T104	21		T99	1
values[6]	697	1			T13	11		T14	31		T111	1
values[7]	508	1			T17	5		T19	1		T60	13
values[8]	724	1			T17	6		T34	2		T95	1
values[9]	3233	1			T13	7		T15	10		T16	11
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	716	1			T24	6		T97	14		T244	3
values[1]	634	1			T13	1		T24	15		T91	7
values[2]	604	1			T60	6		T90	9		T95	1
values[3]	663	1			T34	1		T122	1		T101	6
values[4]	803	1			T111	1		T104	21		T96	23
values[5]	591	1			T13	11		T14	31		T19	1
values[6]	2522	1			T15	10		T16	11		T17	5
values[7]	596	1			T17	6		T34	2		T103	20
values[8]	926	1			T13	7		T19	10		T60	12
values[9]	321	1			T114	34		T117	5		T155	32
minimum	15924	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T24	6		T97	1		T244	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T190	13		T137	1		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	1		T24	7		T91	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T100	1		T101	1		T102	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T90	8		T95	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T60	6		T109	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T34	1		T101	6		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T122	1		T108	4		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T111	1		T96	10		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T104	11		T128	3		T223	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	11		T14	16		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T60	13		T96	1		T223	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T15	10		T16	1		T17	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T135	1		T97	1		T112	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T34	1		T111	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	3		T103	11		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T19	8		T134	1		T114	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	7		T60	12		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T117	1		T138	17		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T114	17		T155	15		T238	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15764	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T291	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T97	13		T244	2		T156	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T190	10		T137	14		T215	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T24	8		T91	2		T155	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T102	13		T110	17		T239	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T90	1		T117	10		T215	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T225	12		T221	12		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T233	8		T141	12		T142	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T108	3		T117	11		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T96	13		T110	3		T156	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T104	10		T223	6		T233	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	15		T214	5		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T96	8		T223	14		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T16	10		T17	2		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T97	11		T112	3		T292	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T134	1		T105	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T17	3		T103	9		T113	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	2		T134	9		T108	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T34	1		T36	1		T113	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T117	4		T200	12		T277	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T114	17		T155	17		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T291	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T224	7		T251	14		T176	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T293	1		T294	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T215	1		T290	8		T283	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T24	6		T156	3		T217	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T190	13		T137	1		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T24	7		T91	5		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T100	1		T101	1		T216	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	1		T90	8		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T60	6		T102	15		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	1		T95	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T122	1		T108	4		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T214	8		T99	1		T101	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T104	11		T223	9		T233	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	11		T14	16		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T128	3		T223	10		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T17	3		T19	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T60	13		T96	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T34	1		T95	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	3		T113	1		T100	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T15	10		T16	1		T19	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	453	1			T13	7		T60	12		T34	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T224	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T215	4		T290	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T156	16		T185	4		T236	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T190	10		T137	14		T124	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	8		T91	2		T97	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T110	17		T239	1		T215	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T90	1		T117	10		T155	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T102	13		T279	6		T132	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T248	13		T188	13		T189	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T108	3		T117	11		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T214	5		T110	3		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T104	10		T223	6		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	15		T96	13		T108	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T223	14		T155	2		T220	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	2		T36	1		T112	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T96	8		T97	11		T112	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T34	1		T134	1		T105	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	3		T113	9		T100	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T16	10		T19	2		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T34	1		T103	9		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T24	1		T97	14		T244	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T190	11		T137	15		T215	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	1		T24	10		T91	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T100	1		T101	1		T102	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T90	6		T95	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	1		T109	1		T225	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T34	1		T101	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T122	1		T108	4		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T111	1		T96	14		T99	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T104	11		T128	1		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T14	16		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T60	1		T96	9		T223	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T15	1		T16	11		T17	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T135	1		T97	12		T112	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	2		T111	1		T134	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	5		T103	10		T113	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T19	3		T134	10		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	1		T60	1		T34	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T117	5		T138	1		T200	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T114	18		T155	18		T238	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15896	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T291	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	5		T156	2		T54	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T190	12		T51	3		T54	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T24	5		T91	2		T98	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T102	14		T216	7		T110	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T90	3		T156	17		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T60	5		T230	16		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T101	5		T150	12		T138	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T108	3		T287	10		T189	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T96	9		T116	9		T110	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T104	10		T128	2		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	10		T14	15		T214	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T60	12		T223	9		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	861	1			T15	9		T17	1		T59	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T112	3		T288	10		T295	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T105	16		T230	14		T258	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T17	1		T103	10		T114	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T19	7		T114	10		T108	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	6		T60	11		T96	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T138	16		T277	7		T289	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T114	16		T155	14		T238	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T263	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T291	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T224	7		T251	1		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T293	2		T294	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T215	5		T290	9		T283	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T24	1		T156	17		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T190	11		T137	15		T124	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T24	10		T91	5		T97	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T100	1		T101	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T13	1		T90	6		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T60	1		T102	14		T109	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	1		T95	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T122	1		T108	4		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T214	8		T99	1		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T104	11		T223	7		T233	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	1		T14	16		T111	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T128	1		T223	15		T155	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T17	4		T19	1		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T60	1		T96	9		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T34	2		T95	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T17	5		T113	10		T100	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T15	1		T16	11		T19	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T13	1		T60	1		T34	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T224	6		T251	13		T176	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T290	7		T283	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T24	5		T156	2		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T190	12		T54	12		T185	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T24	5		T91	2		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T216	7		T110	17		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T90	3		T156	17		T217	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T60	5		T102	14		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T54	2		T251	7		T248	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T108	3		T221	10		T131	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T214	5		T101	5		T150	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T104	10		T223	8		T233	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	10		T14	15		T96	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T128	2		T223	9		T155	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T17	1		T98	14		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T60	12		T112	3		T288	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T105	16		T230	14		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	1		T100	9		T114	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T15	9		T19	7		T59	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T13	6		T60	11		T103	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9