Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19331

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

4969

1

T13

8

T14

31

T15

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18826

1

T6

1

T7

4

T25

1

auto[1]

5474

1

T13

18

T14

31

T15

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T141	8		T296	10		T297	5
values[0]	90	1			T90	9		T96	9		T113	10
values[1]	550	1			T24	2		T60	12		T105	33
values[2]	652	1			T13	7		T95	1		T134	12
values[3]	564	1			T34	2		T99	1		T113	15
values[4]	644	1			T13	1		T17	3		T19	10
values[5]	646	1			T14	31		T17	3		T24	6
values[6]	617	1			T13	11		T214	13		T34	1
values[7]	645	1			T60	19		T34	2		T36	2
values[8]	654	1			T36	2		T112	11		T108	7
values[9]	3321	1			T15	10		T16	11		T17	5
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	843	1			T24	2		T60	12		T90	9
values[1]	2579	1			T13	7		T15	10		T16	11
values[2]	549	1			T34	2		T99	1		T113	15
values[3]	654	1			T13	1		T17	6		T19	10
values[4]	652	1			T14	31		T24	6		T127	1
values[5]	733	1			T13	11		T60	6		T214	13
values[6]	606	1			T60	13		T91	7		T36	4
values[7]	687	1			T17	5		T95	1		T112	11
values[8]	901	1			T19	1		T24	13		T95	1
values[9]	202	1			T135	1		T97	14		T244	3
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T24	1		T60	12		T90	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	1		T105	17		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T122	1		T216	8		T155	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1260	1			T13	7		T15	10		T16	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T34	1		T113	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T99	1		T298	7		T258	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T17	3		T96	10		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T19	8		T103	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	6		T127	1		T114	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T14	16		T109	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	11		T60	6		T214	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T102	15		T216	12		T131	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	1		T99	1		T114	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T60	13		T91	5		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T95	1		T98	15		T116	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	3		T112	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T24	6		T95	1		T111	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T19	1		T104	11		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T135	1		T97	1		T244	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T155	8		T222	5		T189	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T24	1		T90	1		T134	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	9		T105	16		T114	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T155	19		T124	10		T186	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1111	1			T16	10		T97	11		T107	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T34	1		T113	14		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T298	3		T258	9		T299	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	3		T96	13		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T19	2		T103	9		T96	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T114	17		T223	14		T215	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	15		T141	12		T129	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T214	5		T34	1		T112	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T102	13		T131	16		T158	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T36	1		T108	1		T190	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T91	2		T36	1		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T110	3		T224	6		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	2		T112	10		T117	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T24	7		T220	11		T141	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T104	10		T100	8		T117	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T97	13		T244	2		T142	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	5		T189	11		T249	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T141	1		T297	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T296	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T90	8		T96	9		T113	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T293	4		T300	10		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T24	1		T60	12		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T105	17		T99	1		T114	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T134	1		T122	1		T116	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	7		T95	1		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T34	1		T113	1		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T99	1		T123	10		T231	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T17	2		T96	10		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T19	8		T103	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T17	1		T24	6		T114	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	16		T127	1		T101	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	11		T214	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T91	5		T102	15		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T60	6		T34	1		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T60	13		T36	1		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	1		T116	10		T110	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T112	1		T108	4		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T24	6		T95	2		T111	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1382	1			T15	10		T16	1		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T141	7		T297	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T296	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T90	1		T113	9		T302	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T293	3		T300	13		T301	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T24	1		T225	12		T226	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T105	16		T114	2		T155	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T134	1		T155	19		T180	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	9		T97	11		T137	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	1		T113	14		T175	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T298	3		T258	9		T188	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T17	1		T96	13		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T19	2		T103	9		T96	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T17	2		T114	17		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	15		T108	4		T136	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T214	5		T112	3		T108	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T91	2		T102	13		T158	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	1		T110	5		T190	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T36	1		T233	8		T221	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T36	1		T110	3		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T112	10		T108	3		T117	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T24	7		T97	13		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1265	1			T16	10		T17	2		T104	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T24	2		T60	1		T90	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T134	10		T105	17		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T122	1		T216	1		T155	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1449	1			T13	1		T15	1		T16	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T34	2		T113	15		T175	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T99	1		T298	8		T258	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T17	5		T96	14		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T19	3		T103	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T24	1		T127	1		T114	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	16		T109	1		T141	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T13	1		T60	1		T214	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T102	14		T216	1		T131	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	2		T99	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T60	1		T91	5		T36	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T95	1		T98	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	4		T112	11		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T24	8		T95	1		T111	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T19	1		T104	11		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T135	1		T97	14		T244	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T155	6		T222	3		T189	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T60	11		T90	3		T96	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T105	16		T114	2		T101	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T216	7		T155	16		T221	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	922	1			T13	6		T15	9		T59	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T233	2		T217	7		T179	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T298	2		T258	2		T299	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	1		T96	9		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	7		T103	10		T101	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T24	5		T114	16		T223	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T14	15		T251	11		T290	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	10		T60	5		T214	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T102	14		T216	11		T131	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T114	10		T190	12		T223	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T60	12		T91	2		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T98	14		T116	9		T110	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T17	1		T230	11		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	5		T142	13		T248	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T104	10		T100	9		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T303	7		T142	13		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T155	7		T222	2		T189	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T141	8		T297	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T296	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T90	6		T96	1		T113	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T293	4		T300	14		T301	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	2		T60	1		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T105	17		T99	1		T114	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T134	2		T122	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T95	1		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	2		T113	15		T175	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T99	1		T123	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T17	2		T96	14		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	1		T19	3		T103	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T17	3		T24	1		T114	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	16		T127	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	1		T214	8		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T91	5		T102	14		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T60	1		T34	2		T99	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	1		T36	2		T233	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	2		T116	1		T110	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T112	11		T108	4		T117	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T24	8		T95	2		T111	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1623	1			T15	1		T16	11		T17	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T297	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T296	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T90	3		T96	8		T302	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T293	3		T300	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T60	11		T217	11		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T105	16		T114	2		T101	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T116	15		T216	7		T155	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	6		T150	12		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T233	2		T217	7		T179	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T123	9		T231	8		T264	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T17	1		T96	9		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T19	7		T103	10		T110	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T24	5		T114	16		T223	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T14	15		T101	7		T128	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	10		T214	5		T112	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T91	2		T102	14		T216	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	5		T114	10		T110	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T60	12		T221	17		T131	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T116	9		T110	10		T224	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T108	3		T230	11		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T24	5		T98	14		T156	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1024	1			T15	9		T17	1		T59	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9