Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20592

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3708

1

T13

19

T17

11

T24

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18373

1

T6

1

T7

4

T25

1

auto[1]

5927

1

T13

11

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	282	1			T95	1		T104	21		T105	33
values[0]	46	1			T51	12		T185	9		T207	16
values[1]	528	1			T17	3		T24	6		T111	1
values[2]	694	1			T14	31		T19	1		T60	6
values[3]	609	1			T13	1		T214	13		T34	1
values[4]	646	1			T13	11		T17	5		T36	2
values[5]	681	1			T96	9		T97	14		T112	7
values[6]	495	1			T17	3		T60	13		T223	15
values[7]	604	1			T24	2		T102	28		T150	13
values[8]	2725	1			T13	7		T15	10		T16	11
values[9]	1096	1			T19	10		T24	13		T60	12
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	564	1			T24	6		T134	10		T100	1
values[1]	692	1			T14	31		T19	1		T60	6
values[2]	587	1			T13	1		T214	13		T34	1
values[3]	695	1			T13	11		T17	5		T36	2
values[4]	622	1			T60	13		T96	9		T97	14
values[5]	544	1			T17	3		T108	7		T136	2
values[6]	2651	1			T15	10		T16	11		T22	1
values[7]	749	1			T13	7		T60	12		T34	2
values[8]	930	1			T19	10		T24	13		T91	7
values[9]	215	1			T116	10		T110	8		T190	23
minimum	16051	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T100	1		T115	1		T110	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T24	6		T134	1		T140	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	16		T19	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	6		T135	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T98	15		T116	16		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T214	8		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	1		T113	1		T108	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	11		T17	3		T128	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T97	1		T109	1		T224	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T60	13		T96	1		T112	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T108	4		T230	12		T231	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	2		T136	1		T216	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T15	10		T16	1		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T24	1		T34	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T96	10		T105	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	7		T60	12		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T19	8		T24	6		T91	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T105	17		T127	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T116	10		T190	13		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T110	3		T218	3		T305	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15801	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T17	1		T111	1		T157	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T110	3		T155	2		T189	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	9		T125	3		T182	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	15		T233	8		T239	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T97	11		T233	2		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T117	4		T124	3		T292	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T214	5		T103	9		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T36	1		T113	9		T108	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	2		T156	14		T141	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T97	13		T224	6		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T96	8		T112	3		T117	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T108	3		T238	8		T247	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	1		T136	1		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T16	10		T107	20		T243	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	1		T34	1		T137	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T96	13		T124	10		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T34	1		T90	1		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T19	2		T24	7		T91	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T105	16		T100	8		T114	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T190	10		T304	23		T306	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T110	5		T305	10		T307	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T17	2		T232	6		T302	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T95	1		T104	11		T116	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T105	17		T100	10		T114	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T51	9		T185	5		T207	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T100	1		T115	1		T110	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T17	1		T24	6		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	16		T19	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T60	6		T97	1		T98	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T98	15		T116	16		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T214	8		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	1		T113	1		T108	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	11		T17	3		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T97	1		T109	1		T224	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T96	1		T112	4		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T230	12		T231	3		T238	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T17	2		T60	13		T223	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T102	15		T150	13		T108	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	1		T136	1		T216	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T15	10		T16	1		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	7		T34	2		T90	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	8		T24	6		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T60	12		T127	1		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T104	10		T117	10		T271	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T105	16		T100	8		T114	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T51	3		T185	4		T207	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T110	3		T155	2		T189	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	2		T134	9		T125	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	15		T233	8		T182	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T97	11		T125	10		T168	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T239	1		T124	3		T292	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T214	5		T103	9		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T36	1		T113	9		T108	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T17	2		T112	10		T156	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T97	13		T224	6		T141	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T96	8		T112	3		T117	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T238	8		T258	9		T290	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	1		T223	6		T215	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T102	13		T108	3		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T24	1		T136	1		T137	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T16	10		T96	13		T107	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	2		T90	1		T223	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T19	2		T24	7		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T114	17		T110	5		T155	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T100	1		T115	1		T110	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	1		T134	10		T140	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	16		T19	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T60	1		T135	1		T97	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T98	1		T116	1		T117	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	1		T214	8		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	2		T113	10		T108	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T17	4		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T97	14		T109	1		T224	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T60	1		T96	9		T112	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T108	4		T230	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T17	2		T136	2		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T15	1		T16	11		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T24	2		T34	2		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T96	14		T105	1		T124	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	1		T60	1		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T19	3		T24	8		T91	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T105	17		T127	1		T99	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T116	1		T190	11		T304	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T110	6		T218	2		T305	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15937	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T17	3		T111	1		T157	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T110	10		T155	2		T217	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T24	5		T54	12		T57	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	15		T96	8		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T60	5		T98	7		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T98	14		T116	15		T176	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T214	5		T103	10		T216	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T108	4		T155	7		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	10		T17	1		T128	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T224	6		T257	4		T251	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T60	12		T112	3		T114	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T108	3		T230	11		T231	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	1		T216	7		T223	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T15	9		T59	9		T234	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T155	14		T156	17		T248	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T96	9		T231	8		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	6		T60	11		T90	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T19	7		T24	5		T91	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T105	16		T100	9		T114	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T116	9		T190	12		T306	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T110	2		T218	1		T305	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T51	3		T185	4		T237	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T232	2		T302	12		T255	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T95	1		T104	11		T116	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T105	17		T100	9		T114	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T51	9		T185	5		T207	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T100	1		T115	1		T110	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	3		T24	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	16		T19	1		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T60	1		T97	12		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T98	1		T116	1		T239	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T214	8		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T36	2		T113	10		T108	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T17	4		T112	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T97	14		T109	1		T224	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T96	9		T112	4		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T230	1		T231	1		T238	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T17	2		T60	1		T223	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T102	14		T150	1		T108	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T24	2		T136	2		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T15	1		T16	11		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	1		T34	4		T90	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T19	3		T24	8		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T60	1		T127	1		T99	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T104	10		T116	9		T308	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T105	16		T100	9		T114	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T51	3		T185	4		T207	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T110	10		T155	2		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T24	5		T54	12		T57	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T14	15		T96	8		T138	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T60	5		T98	7		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T98	14		T116	15		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T214	5		T103	10		T233	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T108	4		T155	7		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	10		T17	1		T128	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T224	6		T257	4		T251	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T112	3		T114	10		T230	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T230	11		T231	2		T238	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	1		T60	12		T223	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T102	14		T150	12		T108	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T216	7		T155	14		T156	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T15	9		T59	9		T234	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	6		T90	3		T101	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	7		T24	5		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T60	11		T114	16		T101	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9