Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24300

1

T6

1

T7

4

T25

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21105

1

T6

1

T7

4

T25

1

auto[ADC_CTRL_FILTER_COND_OUT]

3195

1

T13

11

T17

3

T19

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18759

1

T6

1

T7

4

T25

1

auto[1]

5541

1

T13

18

T15

10

T16

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T12

163

T13

19

T14

16

auto[1]

4137

1

T6

1

T7

4

T25

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	196	1			T90	9		T105	1		T101	8
values[0]	16	1			T277	15		T309	1		-	-
values[1]	840	1			T19	1		T24	2		T60	6
values[2]	2600	1			T15	10		T16	11		T17	3
values[3]	703	1			T13	11		T98	8		T99	1
values[4]	492	1			T17	3		T36	2		T99	1
values[5]	770	1			T112	7		T127	2		T98	15
values[6]	616	1			T24	13		T34	1		T96	9
values[7]	703	1			T14	31		T214	13		T34	2
values[8]	650	1			T13	8		T60	12		T135	1
values[9]	820	1			T17	5		T60	13		T91	7
minimum	15894	1			T6	1		T7	4		T25	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	819	1			T19	1		T24	2		T34	2
values[1]	2689	1			T15	10		T16	11		T17	3
values[2]	585	1			T13	11		T17	3		T99	1
values[3]	561	1			T36	2		T127	1		T99	1
values[4]	718	1			T112	7		T127	1		T98	15
values[5]	632	1			T24	13		T34	1		T96	9
values[6]	741	1			T14	31		T214	13		T34	2
values[7]	645	1			T13	8		T60	12		T91	7
values[8]	752	1			T17	5		T90	9		T95	2
values[9]	77	1			T60	13		T268	1		T269	5
minimum	16081	1			T6	1		T7	4		T25	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

3338

1

T13

16

T14

15

T15

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T105	17		T115	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T19	1		T24	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T15	10		T16	1		T19	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	2		T24	6		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T17	1		T99	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	11		T270	1		T248	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T36	1		T239	1		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T127	1		T99	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T112	4		T98	15		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T127	1		T122	1		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T34	1		T224	7		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	6		T96	1		T116	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	16		T134	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T214	8		T34	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	8		T60	12		T91	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T136	1		T216	8		T54	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T17	3		T95	1		T36	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T90	8		T95	1		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T60	13		T268	1		T271	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T269	3		T188	1		T272	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15821	1			T12	163		T17	20		T18	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T111	1		T254	1		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T105	16		T141	19		T130	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	1		T34	1		T103	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T16	10		T19	2		T96	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	1		T104	10		T108	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T17	2		T110	17		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T248	10		T189	2		T310	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T36	1		T239	1		T207	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T108	4		T110	3		T137	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T112	3		T113	14		T190	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T102	13		T137	14		T238	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T224	6		T233	2		T215	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T24	7		T96	8		T110	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	15		T134	9		T97	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T214	5		T34	1		T97	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T91	2		T113	9		T124	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T136	1		T142	11		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T17	2		T36	1		T134	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T90	1		T220	11		T222	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T271	6		T275	16		T311	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T269	2		T188	3		T272	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T7	4		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T220	12		T304	12		T261	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T155	3		T268	1		T176	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T90	8		T105	1		T101	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T277	8		T309	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T60	6		T105	17		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T19	1		T24	1		T34	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T15	10		T16	1		T19	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T17	2		T24	6		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T98	8		T99	1		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	11		T108	6		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T17	1		T36	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T99	1		T108	7		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T112	4		T98	15		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	2		T122	2		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T34	1		T128	3		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	6		T96	1		T102	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T14	16		T134	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T214	8		T34	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	8		T60	12		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	1		T216	8		T54	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T17	3		T60	13		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T95	1		T230	12		T222	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15761	1			T12	163		T17	20		T18	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T155	2		T312	13		T313	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T90	1		T220	11		T269	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T277	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T105	16		T225	12		T141	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T24	1		T34	1		T103	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1073	1			T16	10		T19	2		T96	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	1		T104	10		T114	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T110	17		T262	13		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T108	4		T279	6		T189	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	2		T36	1		T239	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T108	4		T233	8		T155	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T112	3		T113	14		T190	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T110	3		T137	29		T238	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T220	4		T186	6		T131	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	7		T96	8		T102	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	15		T134	9		T112	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T214	5		T34	1		T97	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T97	11		T113	9		T124	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T136	1		T133	9		T273	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T17	2		T91	2		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T222	4		T142	11		T188	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	1		T7	4		T25	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T105	17		T115	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T19	1		T24	2		T34	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T15	1		T16	11		T19	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	2		T24	1		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	3		T99	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	1		T270	1		T248	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	2		T239	2		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T127	1		T99	1		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T112	4		T98	1		T113	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T127	1		T122	1		T100	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	1		T224	7		T233	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	8		T96	9		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	16		T134	10		T97	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T214	8		T34	2		T97	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	2		T60	1		T91	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T136	2		T216	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T17	4		T95	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T90	6		T95	1		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T60	1		T268	1		T271	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T269	3		T188	4		T272	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15975	1			T6	1		T7	4		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T111	1		T254	1		T220	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T105	16		T222	2		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T103	10		T96	8		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T15	9		T19	7		T59	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	1		T24	5		T104	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T110	17		T262	14		T50	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	10		T248	10		T189	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T179	2		T231	8		T130	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T101	5		T108	3		T110	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T112	3		T98	14		T114	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T102	14		T123	9		T238	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T224	6		T233	2		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	5		T116	15		T110	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	15		T223	9		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T214	5		T155	14		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	6		T60	11		T91	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T216	7		T54	8		T57	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	1		T155	2		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T90	3		T101	7		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T60	12		T271	6		T280	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T269	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T248	5		T281	6		T314	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T251	11		T177	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T155	3		T268	1		T176	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T90	6		T105	1		T101	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T277	8		T309	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T60	1		T105	17		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T19	1		T24	2		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T15	1		T16	11		T19	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	2		T24	1		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T98	1		T99	1		T109	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	1		T108	6		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	3		T36	2		T239	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T99	1		T108	8		T233	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T112	4		T98	1		T113	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T127	2		T122	2		T100	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	1		T128	1		T220	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T24	8		T96	9		T102	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	16		T134	10		T112	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T214	8		T34	2		T97	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	2		T60	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	2		T216	1		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T17	4		T60	1		T91	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T95	1		T230	1		T222	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15894	1			T6	1		T7	4		T25	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T155	2		T176	9		T312	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T90	3		T101	7		T216	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T277	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T60	5		T105	16		T222	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T103	10		T100	9		T116	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	880	1			T15	9		T19	7		T59	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	1		T24	5		T104	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T98	7		T110	17		T262	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	10		T108	4		T131	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T179	2		T54	12		T264	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T108	3		T155	7		T248	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T112	3		T98	14		T114	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T101	5		T110	10		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T128	2		T131	14		T282	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T24	5		T102	14		T116	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	15		T224	6		T223	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T214	5		T155	14		T231	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	6		T60	11		T138	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T216	7		T54	8		T57	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	1		T60	12		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T230	11		T222	7		T142	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20962

1

T6

1

T7

4

T25

1

auto[1]

auto[0]

3338

1

T13

16

T14

15

T15

9