Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.53 98.98 95.70 100.00 100.00 98.18 98.64 91.24


Total test records in report: 909
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T772 /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2946100028 Dec 20 12:49:57 PM PST 23 Dec 20 01:09:26 PM PST 23 489562633816 ps
T773 /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3096935817 Dec 20 12:49:04 PM PST 23 Dec 20 12:50:25 PM PST 23 31837136592 ps
T49 /workspace/coverage/default/0.adc_ctrl_sec_cm.1864636038 Dec 20 12:48:32 PM PST 23 Dec 20 12:49:42 PM PST 23 3558076638 ps
T774 /workspace/coverage/default/47.adc_ctrl_smoke.1236386728 Dec 20 12:49:43 PM PST 23 Dec 20 12:50:35 PM PST 23 5925075534 ps
T775 /workspace/coverage/default/32.adc_ctrl_fsm_reset.2186002256 Dec 20 12:49:26 PM PST 23 Dec 20 12:57:08 PM PST 23 124186870692 ps
T776 /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1697807312 Dec 20 12:49:13 PM PST 23 Dec 20 01:07:00 PM PST 23 498681444294 ps
T174 /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2096464913 Dec 20 12:47:11 PM PST 23 Dec 20 12:51:06 PM PST 23 325152897747 ps
T777 /workspace/coverage/default/26.adc_ctrl_smoke.3229691530 Dec 20 12:49:04 PM PST 23 Dec 20 12:50:24 PM PST 23 5873757143 ps
T778 /workspace/coverage/default/16.adc_ctrl_fsm_reset.3896023283 Dec 20 12:48:32 PM PST 23 Dec 20 12:57:14 PM PST 23 107753736757 ps
T779 /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3830760786 Dec 20 12:48:48 PM PST 23 Dec 20 12:50:55 PM PST 23 27662380622 ps
T296 /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.548650932 Dec 20 12:49:43 PM PST 23 Dec 20 12:53:06 PM PST 23 100546662688 ps
T780 /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1696021339 Dec 20 12:49:29 PM PST 23 Dec 20 12:50:42 PM PST 23 46973611972 ps
T781 /workspace/coverage/default/32.adc_ctrl_alert_test.4253719529 Dec 20 12:49:15 PM PST 23 Dec 20 12:50:17 PM PST 23 520628942 ps
T782 /workspace/coverage/default/13.adc_ctrl_smoke.1058514214 Dec 20 12:48:57 PM PST 23 Dec 20 12:50:01 PM PST 23 5688077907 ps
T783 /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1644269733 Dec 20 12:49:41 PM PST 23 Dec 20 12:51:46 PM PST 23 30808573500 ps
T784 /workspace/coverage/default/18.adc_ctrl_fsm_reset.2686344014 Dec 20 12:48:51 PM PST 23 Dec 20 12:59:10 PM PST 23 100708470600 ps
T348 /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3922371395 Dec 20 12:50:05 PM PST 23 Dec 20 12:51:31 PM PST 23 77717075878 ps
T785 /workspace/coverage/default/36.adc_ctrl_smoke.2069478932 Dec 20 12:49:22 PM PST 23 Dec 20 12:50:30 PM PST 23 5703741259 ps
T786 /workspace/coverage/default/47.adc_ctrl_stress_all.136454431 Dec 20 12:50:07 PM PST 23 Dec 20 12:53:15 PM PST 23 340652333546 ps
T246 /workspace/coverage/default/48.adc_ctrl_clock_gating.2197557414 Dec 20 12:49:37 PM PST 23 Dec 20 12:53:42 PM PST 23 497964345411 ps
T787 /workspace/coverage/default/29.adc_ctrl_alert_test.1062925645 Dec 20 12:49:04 PM PST 23 Dec 20 12:50:06 PM PST 23 434885233 ps
T788 /workspace/coverage/default/13.adc_ctrl_poweron_counter.2226089002 Dec 20 12:48:27 PM PST 23 Dec 20 12:49:51 PM PST 23 4553768315 ps
T309 /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.289935247 Dec 20 12:49:03 PM PST 23 Dec 20 12:50:28 PM PST 23 29746520112 ps
T789 /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3555399528 Dec 20 12:49:11 PM PST 23 Dec 20 12:53:32 PM PST 23 329627531737 ps
T790 /workspace/coverage/default/23.adc_ctrl_filters_both.354668522 Dec 20 12:49:05 PM PST 23 Dec 20 12:53:37 PM PST 23 169631009457 ps
T791 /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2876471963 Dec 20 12:48:45 PM PST 23 Dec 20 01:02:53 PM PST 23 328413009495 ps
T235 /workspace/coverage/default/14.adc_ctrl_filters_polled.1144229067 Dec 20 12:48:32 PM PST 23 Dec 20 01:02:51 PM PST 23 322183964204 ps
T792 /workspace/coverage/default/40.adc_ctrl_clock_gating.2532320676 Dec 20 12:49:55 PM PST 23 Dec 20 01:03:40 PM PST 23 328634169588 ps
T793 /workspace/coverage/default/27.adc_ctrl_smoke.3268599196 Dec 20 12:49:18 PM PST 23 Dec 20 12:50:23 PM PST 23 5772183702 ps
T794 /workspace/coverage/default/6.adc_ctrl_smoke.3692921450 Dec 20 12:48:09 PM PST 23 Dec 20 12:49:38 PM PST 23 5719557389 ps
T795 /workspace/coverage/default/32.adc_ctrl_smoke.2626962753 Dec 20 12:49:09 PM PST 23 Dec 20 12:50:21 PM PST 23 5766922275 ps
T796 /workspace/coverage/default/26.adc_ctrl_fsm_reset.1985970855 Dec 20 12:49:08 PM PST 23 Dec 20 12:57:48 PM PST 23 126369356807 ps
T294 /workspace/coverage/default/2.adc_ctrl_filters_polled.540388345 Dec 20 12:47:12 PM PST 23 Dec 20 12:52:43 PM PST 23 486629686592 ps
T797 /workspace/coverage/default/3.adc_ctrl_stress_all.2186751036 Dec 20 12:47:26 PM PST 23 Dec 20 12:56:51 PM PST 23 204965073538 ps
T798 /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2900264172 Dec 20 12:49:32 PM PST 23 Dec 20 01:04:22 PM PST 23 494393378883 ps
T799 /workspace/coverage/default/36.adc_ctrl_filters_polled.2718483590 Dec 20 12:49:38 PM PST 23 Dec 20 12:56:25 PM PST 23 165504767633 ps
T800 /workspace/coverage/default/44.adc_ctrl_filters_both.337831467 Dec 20 12:49:53 PM PST 23 Dec 20 12:51:20 PM PST 23 181048118324 ps
T801 /workspace/coverage/default/46.adc_ctrl_lowpower_counter.750994226 Dec 20 12:49:52 PM PST 23 Dec 20 12:51:51 PM PST 23 30589110904 ps
T802 /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2760331275 Dec 20 12:48:09 PM PST 23 Dec 20 12:51:16 PM PST 23 161393844001 ps
T803 /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2227734101 Dec 20 12:48:33 PM PST 23 Dec 20 12:56:15 PM PST 23 633365804325 ps
T804 /workspace/coverage/default/22.adc_ctrl_stress_all.2152193791 Dec 20 12:49:10 PM PST 23 Dec 20 12:56:59 PM PST 23 203487366526 ps
T297 /workspace/coverage/default/26.adc_ctrl_clock_gating.392213317 Dec 20 12:49:05 PM PST 23 Dec 20 12:54:00 PM PST 23 488492770634 ps
T805 /workspace/coverage/default/17.adc_ctrl_filters_both.38332623 Dec 20 12:48:45 PM PST 23 Dec 20 12:53:16 PM PST 23 334747704155 ps
T806 /workspace/coverage/default/49.adc_ctrl_fsm_reset.1768754119 Dec 20 12:49:46 PM PST 23 Dec 20 12:59:20 PM PST 23 122386548467 ps
T807 /workspace/coverage/default/32.adc_ctrl_filters_both.3268533342 Dec 20 12:49:21 PM PST 23 Dec 20 12:54:30 PM PST 23 396977839194 ps
T808 /workspace/coverage/default/32.adc_ctrl_clock_gating.2844213090 Dec 20 12:49:06 PM PST 23 Dec 20 12:51:45 PM PST 23 333123278609 ps
T809 /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2105169605 Dec 20 12:48:54 PM PST 23 Dec 20 01:09:25 PM PST 23 498721709853 ps
T810 /workspace/coverage/default/12.adc_ctrl_filters_wakeup.774409066 Dec 20 12:48:48 PM PST 23 Dec 20 12:53:19 PM PST 23 169994304294 ps
T811 /workspace/coverage/default/34.adc_ctrl_fsm_reset.1692129863 Dec 20 12:49:39 PM PST 23 Dec 20 01:01:19 PM PST 23 117849035397 ps
T812 /workspace/coverage/default/20.adc_ctrl_poweron_counter.932495554 Dec 20 12:48:32 PM PST 23 Dec 20 12:49:40 PM PST 23 4944271349 ps
T261 /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1735322056 Dec 20 12:49:38 PM PST 23 Dec 20 01:03:00 PM PST 23 328411009264 ps
T323 /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.738187365 Dec 20 12:49:39 PM PST 23 Dec 20 12:51:02 PM PST 23 26985519555 ps
T813 /workspace/coverage/default/35.adc_ctrl_alert_test.1927909086 Dec 20 12:49:17 PM PST 23 Dec 20 12:50:19 PM PST 23 424816259 ps
T260 /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2316937625 Dec 20 12:47:25 PM PST 23 Dec 20 01:01:03 PM PST 23 333332914689 ps
T289 /workspace/coverage/default/38.adc_ctrl_stress_all.330250248 Dec 20 12:49:28 PM PST 23 Dec 20 01:04:06 PM PST 23 628348693855 ps
T814 /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2975547660 Dec 20 12:47:13 PM PST 23 Dec 20 12:51:09 PM PST 23 333116974025 ps
T815 /workspace/coverage/default/15.adc_ctrl_smoke.3683423740 Dec 20 12:48:48 PM PST 23 Dec 20 12:49:57 PM PST 23 5578295990 ps
T816 /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2609980821 Dec 20 12:49:08 PM PST 23 Dec 20 12:50:33 PM PST 23 40149701067 ps
T817 /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4002674820 Dec 20 12:48:25 PM PST 23 Dec 20 12:51:13 PM PST 23 40820950406 ps
T818 /workspace/coverage/default/46.adc_ctrl_filters_both.1427743633 Dec 20 12:49:51 PM PST 23 Dec 20 12:52:19 PM PST 23 165017418615 ps
T819 /workspace/coverage/default/8.adc_ctrl_alert_test.3230610554 Dec 20 12:48:15 PM PST 23 Dec 20 12:49:24 PM PST 23 296453542 ps
T820 /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2773208998 Dec 20 12:49:41 PM PST 23 Dec 20 12:50:50 PM PST 23 40877171171 ps
T821 /workspace/coverage/default/30.adc_ctrl_filters_wakeup.873733551 Dec 20 12:49:06 PM PST 23 Dec 20 01:09:38 PM PST 23 489283266638 ps
T822 /workspace/coverage/default/47.adc_ctrl_fsm_reset.2718019278 Dec 20 12:49:56 PM PST 23 Dec 20 01:00:36 PM PST 23 118096255809 ps
T823 /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2588042891 Dec 20 12:48:29 PM PST 23 Dec 20 12:53:13 PM PST 23 324617014259 ps
T824 /workspace/coverage/default/25.adc_ctrl_clock_gating.2255254555 Dec 20 12:48:52 PM PST 23 Dec 20 12:53:23 PM PST 23 165493331394 ps
T825 /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3444139200 Dec 20 12:47:39 PM PST 23 Dec 20 12:49:06 PM PST 23 39515667590 ps
T266 /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1676650749 Dec 20 12:49:24 PM PST 23 Dec 20 01:02:30 PM PST 23 327495071440 ps
T826 /workspace/coverage/default/40.adc_ctrl_filters_polled.3484519491 Dec 20 12:49:37 PM PST 23 Dec 20 12:56:32 PM PST 23 166875533587 ps
T162 /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2834821243 Dec 20 12:47:25 PM PST 23 Dec 20 12:53:23 PM PST 23 498486564464 ps
T827 /workspace/coverage/default/30.adc_ctrl_filters_polled.316780927 Dec 20 12:49:33 PM PST 23 Dec 20 12:59:36 PM PST 23 484199759943 ps
T311 /workspace/coverage/default/13.adc_ctrl_clock_gating.4164525852 Dec 20 12:48:23 PM PST 23 Dec 20 12:55:58 PM PST 23 324130953459 ps
T828 /workspace/coverage/default/10.adc_ctrl_stress_all.624052999 Dec 20 12:48:55 PM PST 23 Dec 20 12:54:12 PM PST 23 202036783477 ps
T829 /workspace/coverage/default/34.adc_ctrl_poweron_counter.1251831987 Dec 20 12:49:09 PM PST 23 Dec 20 12:50:13 PM PST 23 3779619325 ps
T830 /workspace/coverage/default/20.adc_ctrl_filters_polled.2084168710 Dec 20 12:48:50 PM PST 23 Dec 20 12:54:55 PM PST 23 493748576481 ps
T831 /workspace/coverage/default/6.adc_ctrl_filters_polled.826695393 Dec 20 12:48:07 PM PST 23 Dec 20 12:53:13 PM PST 23 168900242981 ps
T832 /workspace/coverage/default/37.adc_ctrl_poweron_counter.655456466 Dec 20 12:49:27 PM PST 23 Dec 20 12:50:25 PM PST 23 3862162523 ps
T833 /workspace/coverage/default/27.adc_ctrl_filters_wakeup.609569209 Dec 20 12:49:08 PM PST 23 Dec 20 12:51:51 PM PST 23 184589111145 ps
T834 /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1468700984 Dec 20 12:49:52 PM PST 23 Dec 20 12:51:42 PM PST 23 26570116055 ps
T835 /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1734668652 Dec 20 12:48:31 PM PST 23 Dec 20 12:50:54 PM PST 23 163986956887 ps
T836 /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1983230879 Dec 20 12:48:32 PM PST 23 Dec 20 01:07:36 PM PST 23 491215145432 ps
T837 /workspace/coverage/default/39.adc_ctrl_stress_all.595120845 Dec 20 12:49:24 PM PST 23 Dec 20 12:54:21 PM PST 23 332499079164 ps
T838 /workspace/coverage/default/0.adc_ctrl_filters_polled.944367217 Dec 20 12:47:12 PM PST 23 Dec 20 01:07:16 PM PST 23 489905948002 ps
T839 /workspace/coverage/default/47.adc_ctrl_alert_test.185527924 Dec 20 12:50:08 PM PST 23 Dec 20 12:50:50 PM PST 23 403970494 ps
T840 /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2266771591 Dec 20 12:49:17 PM PST 23 Dec 20 12:53:21 PM PST 23 200719567982 ps
T841 /workspace/coverage/default/22.adc_ctrl_smoke.3129822640 Dec 20 12:48:55 PM PST 23 Dec 20 12:50:10 PM PST 23 5760333071 ps
T842 /workspace/coverage/default/45.adc_ctrl_poweron_counter.2030203398 Dec 20 12:49:42 PM PST 23 Dec 20 12:50:37 PM PST 23 5393801698 ps
T843 /workspace/coverage/default/17.adc_ctrl_clock_gating.1287709109 Dec 20 12:49:00 PM PST 23 Dec 20 12:55:51 PM PST 23 162015568214 ps
T844 /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1616502940 Dec 20 12:49:17 PM PST 23 Dec 20 12:53:51 PM PST 23 324105021967 ps
T845 /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1106529997 Dec 20 12:47:16 PM PST 23 Dec 20 12:53:29 PM PST 23 490682924356 ps
T846 /workspace/coverage/default/38.adc_ctrl_alert_test.3760146612 Dec 20 12:49:24 PM PST 23 Dec 20 12:50:23 PM PST 23 279489994 ps
T847 /workspace/coverage/default/26.adc_ctrl_alert_test.3425011932 Dec 20 12:49:20 PM PST 23 Dec 20 12:50:20 PM PST 23 457730066 ps
T848 /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1646533317 Dec 20 12:48:45 PM PST 23 Dec 20 12:50:13 PM PST 23 165527112506 ps
T849 /workspace/coverage/default/24.adc_ctrl_filters_both.486791242 Dec 20 12:49:07 PM PST 23 Dec 20 12:53:20 PM PST 23 329533760493 ps
T283 /workspace/coverage/default/49.adc_ctrl_clock_gating.2466678320 Dec 20 12:49:47 PM PST 23 Dec 20 12:56:30 PM PST 23 331071160542 ps
T850 /workspace/coverage/default/8.adc_ctrl_stress_all.1418026678 Dec 20 12:48:40 PM PST 23 Dec 20 12:57:39 PM PST 23 198612634307 ps
T851 /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1189126153 Dec 20 12:48:52 PM PST 23 Dec 20 01:02:06 PM PST 23 329686630922 ps
T852 /workspace/coverage/default/46.adc_ctrl_poweron_counter.4061054848 Dec 20 12:49:43 PM PST 23 Dec 20 12:50:34 PM PST 23 3813217084 ps
T301 /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4053845692 Dec 20 12:49:19 PM PST 23 Dec 20 12:55:27 PM PST 23 493473697789 ps
T853 /workspace/coverage/default/10.adc_ctrl_alert_test.3997714455 Dec 20 12:48:30 PM PST 23 Dec 20 12:49:35 PM PST 23 538554647 ps
T327 /workspace/coverage/default/47.adc_ctrl_filters_interrupt.27084452 Dec 20 12:49:48 PM PST 23 Dec 20 01:03:11 PM PST 23 327186211932 ps
T854 /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2245201200 Dec 20 12:49:42 PM PST 23 Dec 20 12:51:44 PM PST 23 30292023852 ps
T855 /workspace/coverage/default/19.adc_ctrl_smoke.371477790 Dec 20 12:48:38 PM PST 23 Dec 20 12:50:02 PM PST 23 5962436290 ps
T856 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2177511460 Dec 20 12:30:21 PM PST 23 Dec 20 12:31:26 PM PST 23 290870840 ps
T857 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.133480723 Dec 20 12:28:29 PM PST 23 Dec 20 12:29:05 PM PST 23 526987859 ps
T858 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3446637826 Dec 20 12:29:32 PM PST 23 Dec 20 12:29:55 PM PST 23 444715014 ps
T859 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4231365127 Dec 20 12:28:32 PM PST 23 Dec 20 12:29:07 PM PST 23 434015600 ps
T860 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2199491733 Dec 20 12:28:40 PM PST 23 Dec 20 12:29:13 PM PST 23 400461779 ps
T861 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.503929951 Dec 20 12:30:38 PM PST 23 Dec 20 12:31:17 PM PST 23 398872490 ps
T862 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3953591491 Dec 20 12:28:51 PM PST 23 Dec 20 12:29:27 PM PST 23 420404577 ps
T863 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3929141192 Dec 20 12:28:45 PM PST 23 Dec 20 12:29:19 PM PST 23 375492593 ps
T864 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4193925705 Dec 20 12:28:13 PM PST 23 Dec 20 12:28:55 PM PST 23 1957252118 ps
T343 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.885140354 Dec 20 12:28:32 PM PST 23 Dec 20 12:29:11 PM PST 23 4242628006 ps
T865 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3042531749 Dec 20 12:28:29 PM PST 23 Dec 20 12:29:04 PM PST 23 294349794 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2268730166 Dec 20 12:27:55 PM PST 23 Dec 20 12:28:37 PM PST 23 2426354435 ps
T344 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.304409860 Dec 20 12:28:18 PM PST 23 Dec 20 12:29:06 PM PST 23 7924018307 ps
T867 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3835096490 Dec 20 12:29:23 PM PST 23 Dec 20 12:29:47 PM PST 23 472582513 ps
T868 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3375320481 Dec 20 12:28:02 PM PST 23 Dec 20 12:28:43 PM PST 23 446382004 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.722456993 Dec 20 12:28:04 PM PST 23 Dec 20 12:28:45 PM PST 23 389810552 ps
T870 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3420674491 Dec 20 12:28:40 PM PST 23 Dec 20 12:29:13 PM PST 23 431013725 ps
T871 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1187544425 Dec 20 12:28:22 PM PST 23 Dec 20 12:28:57 PM PST 23 892297215 ps
T872 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3588941363 Dec 20 12:28:06 PM PST 23 Dec 20 12:28:48 PM PST 23 567146261 ps
T873 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2473828884 Dec 20 12:28:49 PM PST 23 Dec 20 12:29:24 PM PST 23 418496128 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.525001982 Dec 20 12:28:20 PM PST 23 Dec 20 12:28:58 PM PST 23 569482083 ps
T875 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2006763030 Dec 20 12:28:05 PM PST 23 Dec 20 12:28:50 PM PST 23 1124308167 ps
T876 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.893729161 Dec 20 12:28:17 PM PST 23 Dec 20 12:28:56 PM PST 23 412973163 ps
T877 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3206658765 Dec 20 12:28:12 PM PST 23 Dec 20 12:28:53 PM PST 23 511077562 ps
T878 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1260271149 Dec 20 12:28:27 PM PST 23 Dec 20 12:29:02 PM PST 23 393000282 ps
T879 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1475919990 Dec 20 12:28:34 PM PST 23 Dec 20 12:29:07 PM PST 23 356074893 ps
T880 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1024707231 Dec 20 12:28:18 PM PST 23 Dec 20 12:28:56 PM PST 23 553342671 ps
T881 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1320175521 Dec 20 12:28:11 PM PST 23 Dec 20 12:28:52 PM PST 23 526555002 ps
T882 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2042085840 Dec 20 12:28:23 PM PST 23 Dec 20 12:28:58 PM PST 23 352904855 ps
T883 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.771393326 Dec 20 12:28:34 PM PST 23 Dec 20 12:29:07 PM PST 23 496226241 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.994493024 Dec 20 12:28:35 PM PST 23 Dec 20 12:29:09 PM PST 23 420928739 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.460671353 Dec 20 12:28:10 PM PST 23 Dec 20 12:28:52 PM PST 23 316450644 ps
T886 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1699122817 Dec 20 12:28:31 PM PST 23 Dec 20 12:29:06 PM PST 23 557581717 ps
T887 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.96484417 Dec 20 12:28:58 PM PST 23 Dec 20 12:29:33 PM PST 23 464662123 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3586588199 Dec 20 12:27:57 PM PST 23 Dec 20 12:28:59 PM PST 23 14780701682 ps
T889 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.9755863 Dec 20 12:28:33 PM PST 23 Dec 20 12:29:07 PM PST 23 435913550 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.736989275 Dec 20 12:28:03 PM PST 23 Dec 20 12:28:44 PM PST 23 457792055 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3614736421 Dec 20 12:28:15 PM PST 23 Dec 20 12:28:55 PM PST 23 341137458 ps
T892 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1949726503 Dec 20 12:28:34 PM PST 23 Dec 20 12:29:25 PM PST 23 3888463386 ps
T893 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.25657585 Dec 20 12:27:55 PM PST 23 Dec 20 12:28:33 PM PST 23 896559285 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1543705417 Dec 20 12:27:52 PM PST 23 Dec 20 12:28:29 PM PST 23 443371199 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3058721819 Dec 20 12:28:31 PM PST 23 Dec 20 12:29:05 PM PST 23 317142746 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4087199285 Dec 20 12:27:53 PM PST 23 Dec 20 12:28:35 PM PST 23 4517268279 ps
T897 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.210673319 Dec 20 12:28:19 PM PST 23 Dec 20 12:29:01 PM PST 23 4266016316 ps
T898 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.266999449 Dec 20 12:28:33 PM PST 23 Dec 20 12:29:08 PM PST 23 555545373 ps
T899 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1539598406 Dec 20 12:28:29 PM PST 23 Dec 20 12:29:07 PM PST 23 722548477 ps
T900 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2853067600 Dec 20 12:28:29 PM PST 23 Dec 20 12:29:03 PM PST 23 508509809 ps
T901 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1428663668 Dec 20 12:28:29 PM PST 23 Dec 20 12:29:10 PM PST 23 8079909381 ps
T902 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.190421933 Dec 20 12:28:25 PM PST 23 Dec 20 12:29:00 PM PST 23 447174390 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2260228328 Dec 20 12:27:53 PM PST 23 Dec 20 12:28:31 PM PST 23 450812329 ps
T904 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.665859882 Dec 20 12:28:12 PM PST 23 Dec 20 12:28:58 PM PST 23 4153558121 ps
T905 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2327095117 Dec 20 12:28:05 PM PST 23 Dec 20 12:28:48 PM PST 23 667765278 ps
T906 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.859271453 Dec 20 12:28:11 PM PST 23 Dec 20 12:28:57 PM PST 23 4535356385 ps
T907 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3309721125 Dec 20 12:28:30 PM PST 23 Dec 20 12:29:07 PM PST 23 4712150648 ps
T908 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2156586162 Dec 20 12:28:17 PM PST 23 Dec 20 12:28:56 PM PST 23 375149291 ps
T909 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2050358624 Dec 20 12:28:23 PM PST 23 Dec 20 12:29:01 PM PST 23 8868867994 ps

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.779817682
Short name T5
Test name
Test status
Simulation time 1038703465 ps
CPU time 1.51 seconds
Started Dec 20 12:28:25 PM PST 23
Finished Dec 20 12:29:00 PM PST 23
Peak memory 201000 kb
Host smart-7efacf12-1ada-4d4a-89c8-6b733d62fa00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779817682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.779817682
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4166190067
Short name T3
Test name
Test status
Simulation time 4239668828 ps
CPU time 4.55 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 200880 kb
Host smart-9b7db0f6-ce4e-4683-8ab8-b643db0269c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166190067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4166190067
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.495731986
Short name T17
Test name
Test status
Simulation time 228496215578 ps
CPU time 176.39 seconds
Started Dec 20 12:48:27 PM PST 23
Finished Dec 20 12:52:28 PM PST 23
Peak memory 209572 kb
Host smart-13e1c801-042a-4638-a31a-f4f18862fc62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495731986 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.495731986
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1512843563
Short name T60
Test name
Test status
Simulation time 502743923020 ps
CPU time 338.07 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 12:56:10 PM PST 23
Peak memory 200824 kb
Host smart-2be3e2b4-d990-4fe9-8c86-bb4128af66a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512843563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1512843563
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.197717732
Short name T155
Test name
Test status
Simulation time 676749915184 ps
CPU time 125.1 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:52:37 PM PST 23
Peak memory 200752 kb
Host smart-45023562-efa9-45ca-a877-1de8f1b65c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197717732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
197717732
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3027857467
Short name T34
Test name
Test status
Simulation time 409190415669 ps
CPU time 199.66 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 209636 kb
Host smart-4fcbd5ef-84dd-4205-9dd5-61a2c901f5b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027857467 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3027857467
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2201777305
Short name T25
Test name
Test status
Simulation time 344306281 ps
CPU time 1.46 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 200368 kb
Host smart-717942c4-1af0-47a7-902a-d6950b5fb3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201777305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2201777305
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1058042519
Short name T110
Test name
Test status
Simulation time 492433084662 ps
CPU time 538.25 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:58:59 PM PST 23
Peak memory 200916 kb
Host smart-2d349d62-909d-4a53-85f7-dbb8537b1a93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058042519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1058042519
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1978361315
Short name T24
Test name
Test status
Simulation time 496165288865 ps
CPU time 578.2 seconds
Started Dec 20 12:49:58 PM PST 23
Finished Dec 20 01:00:22 PM PST 23
Peak memory 200976 kb
Host smart-a82aea81-2130-4a84-adcf-346e9ef46e9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978361315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1978361315
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.519908109
Short name T156
Test name
Test status
Simulation time 491471683444 ps
CPU time 314.39 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:55:26 PM PST 23
Peak memory 200988 kb
Host smart-e2b6d9e3-62fc-458f-9682-11a55103f9b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519908109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.519908109
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1432949485
Short name T108
Test name
Test status
Simulation time 264476998220 ps
CPU time 273.16 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:54:39 PM PST 23
Peak memory 209460 kb
Host smart-388c67d7-02e8-4242-acc5-f6f6daafeb03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432949485 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1432949485
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.54403009
Short name T114
Test name
Test status
Simulation time 500801605369 ps
CPU time 260.51 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:52:51 PM PST 23
Peak memory 200972 kb
Host smart-eeeaff66-3d1c-4d9b-a73e-ed28430a540e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54403009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating
.54403009
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.386951703
Short name T142
Test name
Test status
Simulation time 323699263662 ps
CPU time 112.34 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 12:52:12 PM PST 23
Peak memory 200892 kb
Host smart-6e69b3ba-e940-46b3-b83b-707015264dd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386951703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.386951703
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3752688909
Short name T233
Test name
Test status
Simulation time 502678110954 ps
CPU time 633.27 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 01:00:56 PM PST 23
Peak memory 201072 kb
Host smart-37dfab38-ac00-4e14-9580-57fb928e445a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752688909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3752688909
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2710996660
Short name T62
Test name
Test status
Simulation time 7898737020 ps
CPU time 19.68 seconds
Started Dec 20 12:28:22 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 200840 kb
Host smart-4b59ad6b-6bf8-49a1-9ff8-bcac934999a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710996660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2710996660
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.94283336
Short name T13
Test name
Test status
Simulation time 511824170135 ps
CPU time 1086.89 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 01:06:04 PM PST 23
Peak memory 200764 kb
Host smart-6db4f3fc-d12b-4587-b200-3f29b3fe2305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94283336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_wa
keup.94283336
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1991585518
Short name T96
Test name
Test status
Simulation time 499715535282 ps
CPU time 1193.26 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:10:27 PM PST 23
Peak memory 201076 kb
Host smart-16158fb0-0ce6-413c-9b32-6bc9543fcf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991585518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1991585518
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2008532195
Short name T176
Test name
Test status
Simulation time 499376826570 ps
CPU time 273.79 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:55:04 PM PST 23
Peak memory 201108 kb
Host smart-5ff6b513-3084-4abb-abfe-ba7b8400ce25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008532195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2008532195
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.44317518
Short name T258
Test name
Test status
Simulation time 163530614681 ps
CPU time 188.68 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:52:56 PM PST 23
Peak memory 200972 kb
Host smart-f28c0ec6-e8f2-47dd-9b46-77d806dcdb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44317518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.44317518
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3851429838
Short name T189
Test name
Test status
Simulation time 509894458823 ps
CPU time 1124.7 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 01:08:58 PM PST 23
Peak memory 201000 kb
Host smart-77805e0c-fdb8-452a-96ed-5a5fb50a26e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851429838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3851429838
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1105107990
Short name T4
Test name
Test status
Simulation time 42979597076 ps
CPU time 47.52 seconds
Started Dec 20 12:27:54 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 200896 kb
Host smart-f831f54c-9799-44f9-acd2-4f14c742bd7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105107990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1105107990
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3519909074
Short name T59
Test name
Test status
Simulation time 163584587123 ps
CPU time 363.2 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:56:33 PM PST 23
Peak memory 200968 kb
Host smart-41093862-32d0-425d-8f46-7b6bf15e2ba0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519909074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3519909074
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4145531814
Short name T242
Test name
Test status
Simulation time 82367589608 ps
CPU time 86.46 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:51:09 PM PST 23
Peak memory 209816 kb
Host smart-e58c4fc0-7a34-4486-a3e8-37b98cd6bb51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145531814 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4145531814
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1464945080
Short name T141
Test name
Test status
Simulation time 487977551751 ps
CPU time 265.06 seconds
Started Dec 20 12:49:14 PM PST 23
Finished Dec 20 12:54:41 PM PST 23
Peak memory 201000 kb
Host smart-200e8fca-22f8-4345-864b-cbb07182e946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464945080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1464945080
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3732055170
Short name T273
Test name
Test status
Simulation time 497907367052 ps
CPU time 810.85 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 01:03:38 PM PST 23
Peak memory 200948 kb
Host smart-80cfd3da-b845-4a18-a5c0-3cde885181a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732055170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3732055170
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2596996089
Short name T161
Test name
Test status
Simulation time 498288371759 ps
CPU time 117.8 seconds
Started Dec 20 12:49:21 PM PST 23
Finished Dec 20 12:52:18 PM PST 23
Peak memory 201032 kb
Host smart-2bd47348-a601-45f4-a482-35f7f7e8987a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596996089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2596996089
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.314815229
Short name T65
Test name
Test status
Simulation time 1012889576 ps
CPU time 2.77 seconds
Started Dec 20 12:27:59 PM PST 23
Finished Dec 20 12:28:39 PM PST 23
Peak memory 200884 kb
Host smart-61d38878-7935-4b79-9bbd-7625fd40557a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314815229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.314815229
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3287437110
Short name T207
Test name
Test status
Simulation time 435432705822 ps
CPU time 430.31 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:57:37 PM PST 23
Peak memory 216240 kb
Host smart-0e80b47a-58d4-4ddb-bf5b-db7a93f9f42b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287437110 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3287437110
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2060860712
Short name T113
Test name
Test status
Simulation time 417518997602 ps
CPU time 1015.85 seconds
Started Dec 20 12:49:21 PM PST 23
Finished Dec 20 01:07:16 PM PST 23
Peak memory 200816 kb
Host smart-b81a3e8a-5466-4235-823b-5e697dbf6041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060860712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2060860712
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1864636038
Short name T49
Test name
Test status
Simulation time 3558076638 ps
CPU time 4.59 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:49:42 PM PST 23
Peak memory 214920 kb
Host smart-2beca232-7f4f-43d2-883d-abecfbbfd6e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864636038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1864636038
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.564240648
Short name T277
Test name
Test status
Simulation time 501978580340 ps
CPU time 198.55 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:53:30 PM PST 23
Peak memory 200828 kb
Host smart-3cff694d-a3ca-4339-81bd-1b07af17b22e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564240648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.564240648
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4037170633
Short name T251
Test name
Test status
Simulation time 499848105122 ps
CPU time 287.63 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:55:02 PM PST 23
Peak memory 200960 kb
Host smart-51bbfc81-0f03-4406-9975-86fb462e9ca0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037170633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4037170633
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.444667650
Short name T237
Test name
Test status
Simulation time 453661148342 ps
CPU time 638.34 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 01:01:04 PM PST 23
Peak memory 209664 kb
Host smart-0c9bc45f-92ac-4407-8cb4-218005c24706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444667650 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.444667650
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2912184010
Short name T212
Test name
Test status
Simulation time 172226371379 ps
CPU time 96.32 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:51:24 PM PST 23
Peak memory 200960 kb
Host smart-6529e151-ba1b-4c28-965c-67cc3c6a7ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912184010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2912184010
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3932683600
Short name T188
Test name
Test status
Simulation time 486195122373 ps
CPU time 582.27 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:59:51 PM PST 23
Peak memory 201012 kb
Host smart-f65f9796-8800-4786-a622-ad9d113f0637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932683600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3932683600
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1299475229
Short name T430
Test name
Test status
Simulation time 465550537 ps
CPU time 0.9 seconds
Started Dec 20 12:47:32 PM PST 23
Finished Dec 20 12:48:51 PM PST 23
Peak memory 200736 kb
Host smart-43470099-8307-4cea-9e09-aea85ff41d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299475229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1299475229
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2316937625
Short name T260
Test name
Test status
Simulation time 333332914689 ps
CPU time 748.46 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 01:01:03 PM PST 23
Peak memory 200840 kb
Host smart-6293877a-4280-4dfc-8f2e-699263c4550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316937625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2316937625
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3887504243
Short name T131
Test name
Test status
Simulation time 499738359888 ps
CPU time 1095.58 seconds
Started Dec 20 12:49:27 PM PST 23
Finished Dec 20 01:08:40 PM PST 23
Peak memory 200904 kb
Host smart-cd637792-dc24-4ff8-b51a-8f38a72846c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887504243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3887504243
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.806401111
Short name T148
Test name
Test status
Simulation time 487147364452 ps
CPU time 1049.95 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:08:04 PM PST 23
Peak memory 200840 kb
Host smart-0e9b831a-26ae-40e7-b085-61ac004e024f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806401111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.806401111
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3100945646
Short name T315
Test name
Test status
Simulation time 491938586598 ps
CPU time 824.71 seconds
Started Dec 20 12:48:22 PM PST 23
Finished Dec 20 01:03:22 PM PST 23
Peak memory 200956 kb
Host smart-3714166e-68f2-470f-9a75-d1b9cd7698c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100945646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3100945646
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3429975883
Short name T121
Test name
Test status
Simulation time 176688219195 ps
CPU time 506.36 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:58:30 PM PST 23
Peak memory 209660 kb
Host smart-af4d9999-110d-4399-bc4c-521155c88fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429975883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3429975883
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2136589110
Short name T248
Test name
Test status
Simulation time 485107460115 ps
CPU time 296.35 seconds
Started Dec 20 12:49:16 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 200860 kb
Host smart-39cccb39-eb7d-4a26-b8f4-c033e237b62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136589110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2136589110
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3612965711
Short name T100
Test name
Test status
Simulation time 328357856695 ps
CPU time 236.55 seconds
Started Dec 20 12:49:51 PM PST 23
Finished Dec 20 12:54:35 PM PST 23
Peak memory 200724 kb
Host smart-e0500385-3598-4c45-b2f6-8aed85568fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612965711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3612965711
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2237195513
Short name T330
Test name
Test status
Simulation time 366036387018 ps
CPU time 827.14 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 01:04:04 PM PST 23
Peak memory 200904 kb
Host smart-a11c3142-703d-45b3-ae00-72cb30ae4c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237195513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2237195513
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1318952298
Short name T217
Test name
Test status
Simulation time 501806475882 ps
CPU time 97.6 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:49:27 PM PST 23
Peak memory 200972 kb
Host smart-0ccb6ad5-a8b1-4159-ab5e-80bb745417f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318952298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1318952298
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3393171558
Short name T255
Test name
Test status
Simulation time 492928765666 ps
CPU time 445.53 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 200960 kb
Host smart-c217b826-0807-4935-9592-1d708033c2c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393171558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3393171558
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2466678320
Short name T283
Test name
Test status
Simulation time 331071160542 ps
CPU time 354.64 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 12:56:30 PM PST 23
Peak memory 201084 kb
Host smart-9604a1c7-fad4-47f1-85ee-01d4858ad897
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466678320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2466678320
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2809113244
Short name T335
Test name
Test status
Simulation time 635855994905 ps
CPU time 810.14 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 01:03:25 PM PST 23
Peak memory 209700 kb
Host smart-a74f6ad4-59b4-48ed-86a1-74c6de406919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809113244 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2809113244
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1077449514
Short name T293
Test name
Test status
Simulation time 487862344115 ps
CPU time 388.41 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:56:34 PM PST 23
Peak memory 200968 kb
Host smart-f6d029d1-08fc-43b2-8b7f-ca95a1bca19d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077449514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1077449514
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1236856853
Short name T177
Test name
Test status
Simulation time 328920319636 ps
CPU time 209.44 seconds
Started Dec 20 12:49:35 PM PST 23
Finished Dec 20 12:53:59 PM PST 23
Peak memory 200872 kb
Host smart-fae03684-3eaa-46e0-ade2-e150eebed478
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236856853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1236856853
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.25657585
Short name T893
Test name
Test status
Simulation time 896559285 ps
CPU time 2.33 seconds
Started Dec 20 12:27:55 PM PST 23
Finished Dec 20 12:28:33 PM PST 23
Peak memory 200928 kb
Host smart-a703df63-368e-4bb9-b1a5-84f8d29957aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25657585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.25657585
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1751069829
Short name T159
Test name
Test status
Simulation time 676593909132 ps
CPU time 2536.09 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 01:32:35 PM PST 23
Peak memory 211316 kb
Host smart-e1548a81-f27c-47b8-b7a1-588c72684983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751069829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1751069829
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.634936537
Short name T245
Test name
Test status
Simulation time 326117170967 ps
CPU time 800.19 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 01:03:48 PM PST 23
Peak memory 200784 kb
Host smart-133d3ff5-a174-45ca-bc70-660c96d660ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634936537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.634936537
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1735322056
Short name T261
Test name
Test status
Simulation time 328411009264 ps
CPU time 749.46 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 01:03:00 PM PST 23
Peak memory 201044 kb
Host smart-916f3021-ea8c-4a2a-aa1f-2870cbee992f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735322056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1735322056
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1719841471
Short name T299
Test name
Test status
Simulation time 169781907689 ps
CPU time 248.68 seconds
Started Dec 20 12:49:35 PM PST 23
Finished Dec 20 12:54:38 PM PST 23
Peak memory 201024 kb
Host smart-400df1d3-77d8-4a28-a1b1-342d8a5df57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719841471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1719841471
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2592609617
Short name T133
Test name
Test status
Simulation time 332924254972 ps
CPU time 347.56 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:55:57 PM PST 23
Peak memory 209516 kb
Host smart-aa6d6107-8ad3-4e84-acd9-8f234d930559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592609617 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2592609617
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2551094623
Short name T319
Test name
Test status
Simulation time 329104146772 ps
CPU time 369.15 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 12:56:36 PM PST 23
Peak memory 200784 kb
Host smart-bc23a812-f9e5-4799-9323-ae68bb5d94de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551094623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2551094623
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.548650932
Short name T296
Test name
Test status
Simulation time 100546662688 ps
CPU time 153.19 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:53:06 PM PST 23
Peak memory 209372 kb
Host smart-4e09f8ea-c250-4ac5-8154-0f9ab4b6c628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548650932 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.548650932
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1676650749
Short name T266
Test name
Test status
Simulation time 327495071440 ps
CPU time 727.59 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 01:02:30 PM PST 23
Peak memory 200980 kb
Host smart-fa98fde2-7361-44be-aeb9-063f280ab665
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676650749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1676650749
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1381706059
Short name T291
Test name
Test status
Simulation time 159372124431 ps
CPU time 378.96 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 201120 kb
Host smart-e89a7a88-d1cc-49c4-98ff-f17b0c82e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381706059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1381706059
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4053845692
Short name T301
Test name
Test status
Simulation time 493473697789 ps
CPU time 308.08 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:55:27 PM PST 23
Peak memory 200780 kb
Host smart-3a3282d5-b877-4c4b-ae9d-726841f8785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053845692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4053845692
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1635954416
Short name T104
Test name
Test status
Simulation time 162284690345 ps
CPU time 369.62 seconds
Started Dec 20 12:50:02 PM PST 23
Finished Dec 20 12:56:56 PM PST 23
Peak memory 200928 kb
Host smart-9e4e5bae-ec76-48b8-af4a-701c12558bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635954416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1635954416
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.701918450
Short name T253
Test name
Test status
Simulation time 168753536302 ps
CPU time 370.78 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 200972 kb
Host smart-cbb97bec-4583-4837-9898-30f3b48cca01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701918450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.701918450
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1144229067
Short name T235
Test name
Test status
Simulation time 322183964204 ps
CPU time 782.21 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 01:02:51 PM PST 23
Peak memory 200976 kb
Host smart-4c1846ee-b17d-40df-a0ea-0ac7d74ce786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144229067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1144229067
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2787972738
Short name T213
Test name
Test status
Simulation time 360488985291 ps
CPU time 396.28 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 200980 kb
Host smart-dd2c728c-ca50-4f69-9ec4-35c4d5ed8dc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787972738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2787972738
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2483037343
Short name T312
Test name
Test status
Simulation time 324229219615 ps
CPU time 733.64 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 01:00:05 PM PST 23
Peak memory 200988 kb
Host smart-3bdbce6a-7e7d-4e07-ba3d-856fa67eb853
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483037343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2483037343
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2315852022
Short name T352
Test name
Test status
Simulation time 132108733123 ps
CPU time 515.5 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:58:43 PM PST 23
Peak memory 201312 kb
Host smart-141b553c-2809-4021-853f-06bb414fb78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315852022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2315852022
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.135768107
Short name T215
Test name
Test status
Simulation time 495187585761 ps
CPU time 791.42 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 01:01:20 PM PST 23
Peak memory 200912 kb
Host smart-dfb1b465-0460-4318-96d6-e44cc3f8da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135768107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.135768107
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2004824676
Short name T150
Test name
Test status
Simulation time 168162857590 ps
CPU time 110.89 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:52:21 PM PST 23
Peak memory 201020 kb
Host smart-d6e7884a-ecaa-4bc1-a568-c74f5b299115
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004824676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2004824676
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2415953548
Short name T269
Test name
Test status
Simulation time 168786677243 ps
CPU time 130.14 seconds
Started Dec 20 12:48:04 PM PST 23
Finished Dec 20 12:51:26 PM PST 23
Peak memory 200984 kb
Host smart-7555715a-d57c-41e3-aaf5-1b86789aeb14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415953548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2415953548
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.208774259
Short name T7
Test name
Test status
Simulation time 353072563 ps
CPU time 1.01 seconds
Started Dec 20 12:27:56 PM PST 23
Finished Dec 20 12:28:35 PM PST 23
Peak memory 200596 kb
Host smart-454c4be1-ced9-46ac-b0be-9c4020ae827a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208774259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.208774259
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.885140354
Short name T343
Test name
Test status
Simulation time 4242628006 ps
CPU time 6.6 seconds
Started Dec 20 12:28:32 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 200924 kb
Host smart-4dc11195-d114-4a8a-b4b1-d1a2f15a5285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885140354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.885140354
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3893835154
Short name T95
Test name
Test status
Simulation time 499168447471 ps
CPU time 1221.74 seconds
Started Dec 20 12:48:28 PM PST 23
Finished Dec 20 01:10:07 PM PST 23
Peak memory 201072 kb
Host smart-8fabefa6-e15d-4362-99d3-66f6a5b20a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893835154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3893835154
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1774347152
Short name T265
Test name
Test status
Simulation time 410454589206 ps
CPU time 895.61 seconds
Started Dec 20 12:49:01 PM PST 23
Finished Dec 20 01:04:59 PM PST 23
Peak memory 201372 kb
Host smart-8cded945-777f-4d9d-bf1d-1b20cc05cc40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774347152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1774347152
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1923916613
Short name T236
Test name
Test status
Simulation time 170272939338 ps
CPU time 376.21 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 201048 kb
Host smart-bbd7ac6a-bda4-4477-a53d-e5981795cf63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923916613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1923916613
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2998890173
Short name T264
Test name
Test status
Simulation time 167461649472 ps
CPU time 394.29 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:56:46 PM PST 23
Peak memory 200908 kb
Host smart-ef9bb7ec-f212-4cbc-a688-e5a256a1cd74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998890173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2998890173
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.945162415
Short name T51
Test name
Test status
Simulation time 232273011670 ps
CPU time 166.68 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:53:17 PM PST 23
Peak memory 209312 kb
Host smart-e5c418aa-069d-4b54-ae0b-98ac731b56be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945162415 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.945162415
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.994493024
Short name T884
Test name
Test status
Simulation time 420928739 ps
CPU time 2.51 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 200904 kb
Host smart-a1f3c649-795e-419a-8788-489dac3ba06e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994493024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.994493024
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4164525852
Short name T311
Test name
Test status
Simulation time 324130953459 ps
CPU time 370.53 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 201028 kb
Host smart-07bc935b-1a10-478e-8b95-86ee6550381b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164525852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4164525852
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3965821323
Short name T206
Test name
Test status
Simulation time 100993395324 ps
CPU time 321.16 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 201052 kb
Host smart-4cfc5a87-78b2-4394-9ab7-f73c399e3520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965821323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3965821323
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3081559860
Short name T259
Test name
Test status
Simulation time 186707649424 ps
CPU time 82 seconds
Started Dec 20 12:49:11 PM PST 23
Finished Dec 20 12:51:35 PM PST 23
Peak memory 211456 kb
Host smart-2e34fda9-d689-4fec-b54a-7245bddff0cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081559860 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3081559860
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.392213317
Short name T297
Test name
Test status
Simulation time 488492770634 ps
CPU time 232.04 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:54:00 PM PST 23
Peak memory 200884 kb
Host smart-8c4b8775-5c9c-4fd2-980f-255ac82c1873
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392213317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.392213317
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3948529834
Short name T325
Test name
Test status
Simulation time 331371286834 ps
CPU time 198.67 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:53:25 PM PST 23
Peak memory 201080 kb
Host smart-45911ef8-ed73-4f73-bca2-3fa72d970cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948529834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3948529834
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2266771591
Short name T840
Test name
Test status
Simulation time 200719567982 ps
CPU time 182.08 seconds
Started Dec 20 12:49:17 PM PST 23
Finished Dec 20 12:53:21 PM PST 23
Peak memory 209568 kb
Host smart-3aa81ac1-683e-4ada-8958-344a4b4dc80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266771591 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2266771591
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.821786
Short name T228
Test name
Test status
Simulation time 489578740543 ps
CPU time 1110.8 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 01:08:37 PM PST 23
Peak memory 201004 kb
Host smart-778650f9-79e0-45b5-aafc-93d2893b44f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.821786
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3641500804
Short name T281
Test name
Test status
Simulation time 161570158318 ps
CPU time 100.44 seconds
Started Dec 20 12:49:14 PM PST 23
Finished Dec 20 12:52:01 PM PST 23
Peak memory 200824 kb
Host smart-a5d811b1-948f-43fa-888f-62b2646b6c94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641500804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3641500804
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3706965489
Short name T205
Test name
Test status
Simulation time 63540629086 ps
CPU time 340.81 seconds
Started Dec 20 12:49:28 PM PST 23
Finished Dec 20 12:56:06 PM PST 23
Peak memory 201420 kb
Host smart-56b45648-9ea3-4e90-a452-e9e056bd5113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706965489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3706965489
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.43710002
Short name T263
Test name
Test status
Simulation time 360349119910 ps
CPU time 155.45 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:52:54 PM PST 23
Peak memory 209228 kb
Host smart-8faa2564-9807-4eb1-9e2c-68592e931271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43710002 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.43710002
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3178306399
Short name T224
Test name
Test status
Simulation time 221157500961 ps
CPU time 265.89 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:52:24 PM PST 23
Peak memory 200984 kb
Host smart-118d14ed-ca76-471e-a61b-2af95a33e30f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178306399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3178306399
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2799117396
Short name T54
Test name
Test status
Simulation time 494271986391 ps
CPU time 1093.75 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 01:08:47 PM PST 23
Peak memory 200968 kb
Host smart-76e4b4c4-1eb9-4190-8954-7723dca2d433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799117396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2799117396
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3922371395
Short name T348
Test name
Test status
Simulation time 77717075878 ps
CPU time 43.11 seconds
Started Dec 20 12:50:05 PM PST 23
Finished Dec 20 12:51:31 PM PST 23
Peak memory 209704 kb
Host smart-bf139480-96dc-43cf-a1bc-dd3b75bac00e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922371395 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3922371395
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1449976359
Short name T173
Test name
Test status
Simulation time 495436698781 ps
CPU time 293.41 seconds
Started Dec 20 12:50:12 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 201024 kb
Host smart-97544c15-c1c7-4a69-8ec1-f0845de9d4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449976359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1449976359
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3162707479
Short name T304
Test name
Test status
Simulation time 492866413795 ps
CPU time 1139.97 seconds
Started Dec 20 12:47:54 PM PST 23
Finished Dec 20 01:08:21 PM PST 23
Peak memory 200896 kb
Host smart-47cc3f27-9b32-455f-8fd6-0f1fd513bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162707479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3162707479
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1632406302
Short name T250
Test name
Test status
Simulation time 322795870155 ps
CPU time 346.07 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:54:06 PM PST 23
Peak memory 200916 kb
Host smart-1b50453d-21fc-4217-96ee-47d8dff11731
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632406302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1632406302
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3526359481
Short name T125
Test name
Test status
Simulation time 497095023456 ps
CPU time 1131.62 seconds
Started Dec 20 12:48:19 PM PST 23
Finished Dec 20 01:08:34 PM PST 23
Peak memory 201024 kb
Host smart-989c6ec3-6445-4513-9245-d4225d20cb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526359481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3526359481
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2492839441
Short name T339
Test name
Test status
Simulation time 322228548815 ps
CPU time 700.06 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 01:01:29 PM PST 23
Peak memory 200828 kb
Host smart-a9f58da3-8eb0-42e0-9d14-b515da5360ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492839441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2492839441
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3425649910
Short name T77
Test name
Test status
Simulation time 1002400320 ps
CPU time 3.47 seconds
Started Dec 20 12:28:07 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 200748 kb
Host smart-5ec918da-cda5-4369-95ae-cadfef5c9fc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425649910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3425649910
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4016406941
Short name T70
Test name
Test status
Simulation time 766152341 ps
CPU time 1.16 seconds
Started Dec 20 12:27:54 PM PST 23
Finished Dec 20 12:28:31 PM PST 23
Peak memory 200620 kb
Host smart-c399d424-4e84-4ab3-9cf7-fdeb77ba40db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016406941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4016406941
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1619735048
Short name T27
Test name
Test status
Simulation time 321411246 ps
CPU time 0.93 seconds
Started Dec 20 12:28:12 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 200672 kb
Host smart-bef98525-49dc-4223-99d6-89309493c790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619735048 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1619735048
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1261745463
Short name T76
Test name
Test status
Simulation time 405440966 ps
CPU time 1.24 seconds
Started Dec 20 12:27:46 PM PST 23
Finished Dec 20 12:28:21 PM PST 23
Peak memory 200624 kb
Host smart-eadf37d2-5601-45e7-bd23-4a009d2325c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261745463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1261745463
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.398677497
Short name T373
Test name
Test status
Simulation time 394014265 ps
CPU time 1.06 seconds
Started Dec 20 12:28:12 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 200540 kb
Host smart-29e29351-828b-4729-91ad-1d29211f7090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398677497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.398677497
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.278883261
Short name T383
Test name
Test status
Simulation time 2235075212 ps
CPU time 7.17 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:35 PM PST 23
Peak memory 200836 kb
Host smart-4b259082-9a49-4530-8033-0ec79ded4623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278883261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.278883261
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.859271453
Short name T906
Test name
Test status
Simulation time 4535356385 ps
CPU time 6.58 seconds
Started Dec 20 12:28:11 PM PST 23
Finished Dec 20 12:28:57 PM PST 23
Peak memory 200708 kb
Host smart-eba56711-3007-4316-8e0d-95716b23b6d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859271453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.859271453
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2973675125
Short name T385
Test name
Test status
Simulation time 1378726533 ps
CPU time 2.46 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:27 PM PST 23
Peak memory 200884 kb
Host smart-559da4a5-47e3-48c8-8ca9-8266fa610eb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973675125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2973675125
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3586588199
Short name T888
Test name
Test status
Simulation time 14780701682 ps
CPU time 24.13 seconds
Started Dec 20 12:27:57 PM PST 23
Finished Dec 20 12:28:59 PM PST 23
Peak memory 200852 kb
Host smart-67c8c90d-19f6-45d1-851f-dcce659c410f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586588199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3586588199
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1796350614
Short name T69
Test name
Test status
Simulation time 779848284 ps
CPU time 0.97 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 200636 kb
Host smart-23490551-1a6a-496b-8ec1-85684e3780ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796350614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1796350614
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3710210188
Short name T35
Test name
Test status
Simulation time 478225572 ps
CPU time 1.69 seconds
Started Dec 20 12:29:32 PM PST 23
Finished Dec 20 12:29:54 PM PST 23
Peak memory 200572 kb
Host smart-35202350-b75c-4a3b-aef5-a2afb4d3f0ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710210188 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3710210188
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1543705417
Short name T894
Test name
Test status
Simulation time 443371199 ps
CPU time 1.33 seconds
Started Dec 20 12:27:52 PM PST 23
Finished Dec 20 12:28:29 PM PST 23
Peak memory 200608 kb
Host smart-e79c05e5-a30e-4d94-8869-6a556e5ad343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543705417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1543705417
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2132684757
Short name T11
Test name
Test status
Simulation time 2165385682 ps
CPU time 5.3 seconds
Started Dec 20 12:27:57 PM PST 23
Finished Dec 20 12:28:40 PM PST 23
Peak memory 200668 kb
Host smart-be75ef4d-720d-4eee-b962-0713d7f378b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132684757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2132684757
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2425059153
Short name T342
Test name
Test status
Simulation time 4904571863 ps
CPU time 7.36 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:36 PM PST 23
Peak memory 200912 kb
Host smart-09791c39-4866-4e49-bc2d-288db7afd2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425059153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2425059153
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1485360097
Short name T399
Test name
Test status
Simulation time 563300845 ps
CPU time 1.38 seconds
Started Dec 20 12:28:18 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 200696 kb
Host smart-f3bfa7a8-8db4-4331-ba96-48c488e713ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485360097 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1485360097
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3042531749
Short name T865
Test name
Test status
Simulation time 294349794 ps
CPU time 1.33 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:04 PM PST 23
Peak memory 200720 kb
Host smart-f2423506-37b0-4afb-9230-d716bf68c9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042531749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3042531749
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3025119732
Short name T29
Test name
Test status
Simulation time 493429113 ps
CPU time 0.83 seconds
Started Dec 20 12:28:14 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 200396 kb
Host smart-8f115e3f-4a88-445f-9e89-587f90dcdd67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025119732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3025119732
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4193925705
Short name T864
Test name
Test status
Simulation time 1957252118 ps
CPU time 2.38 seconds
Started Dec 20 12:28:13 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200696 kb
Host smart-f6c7a633-92b0-4f57-9034-102d621ac55c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193925705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4193925705
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.447121698
Short name T61
Test name
Test status
Simulation time 4346639287 ps
CPU time 9.02 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 200920 kb
Host smart-67adb0ce-420a-40ad-bed6-fa733a882b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447121698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.447121698
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1038078602
Short name T355
Test name
Test status
Simulation time 507664770 ps
CPU time 1.19 seconds
Started Dec 20 12:28:18 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 200716 kb
Host smart-db3a9a07-0fca-4183-8e8f-0303b32733e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038078602 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1038078602
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1219565868
Short name T30
Test name
Test status
Simulation time 446125572 ps
CPU time 1.88 seconds
Started Dec 20 12:28:21 PM PST 23
Finished Dec 20 12:28:58 PM PST 23
Peak memory 200488 kb
Host smart-5c4c632a-bbdd-498d-8da1-ffa2168bbc9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219565868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1219565868
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1805911001
Short name T28
Test name
Test status
Simulation time 371541726 ps
CPU time 1.05 seconds
Started Dec 20 12:28:15 PM PST 23
Finished Dec 20 12:28:54 PM PST 23
Peak memory 200380 kb
Host smart-3431cf76-9bd1-4b12-be21-65b6570c3dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805911001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1805911001
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3386229933
Short name T371
Test name
Test status
Simulation time 633365430 ps
CPU time 1.9 seconds
Started Dec 20 12:28:26 PM PST 23
Finished Dec 20 12:29:01 PM PST 23
Peak memory 200904 kb
Host smart-97baaef1-6d62-4bd1-89f9-e48bc7fccf4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386229933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3386229933
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2050358624
Short name T909
Test name
Test status
Simulation time 8868867994 ps
CPU time 3.69 seconds
Started Dec 20 12:28:23 PM PST 23
Finished Dec 20 12:29:01 PM PST 23
Peak memory 200776 kb
Host smart-593c41d2-77a4-458d-b782-4379c4794e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050358624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2050358624
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3049001089
Short name T10
Test name
Test status
Simulation time 693344743 ps
CPU time 0.96 seconds
Started Dec 20 12:28:31 PM PST 23
Finished Dec 20 12:29:04 PM PST 23
Peak memory 200748 kb
Host smart-340670e8-4019-4cf7-9a1c-41444be967b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049001089 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3049001089
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4104800663
Short name T82
Test name
Test status
Simulation time 387915650 ps
CPU time 0.9 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:03 PM PST 23
Peak memory 200656 kb
Host smart-8dc6d4d0-d667-4eb5-85ee-b65cb5e0f853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104800663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4104800663
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3058721819
Short name T895
Test name
Test status
Simulation time 317142746 ps
CPU time 1.31 seconds
Started Dec 20 12:28:31 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 200484 kb
Host smart-6cf20701-ac32-483b-9bcb-934d66f6306d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058721819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3058721819
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3441587117
Short name T362
Test name
Test status
Simulation time 4937306698 ps
CPU time 8.95 seconds
Started Dec 20 12:28:31 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 200904 kb
Host smart-3347f8b8-faf0-4a9c-8514-6a0770d52c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441587117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3441587117
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.266999449
Short name T898
Test name
Test status
Simulation time 555545373 ps
CPU time 2.44 seconds
Started Dec 20 12:28:33 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200932 kb
Host smart-1ae290b5-eb2e-4d63-bcbc-e2869563fe5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266999449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.266999449
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.887950276
Short name T67
Test name
Test status
Simulation time 413807190 ps
CPU time 1.21 seconds
Started Dec 20 12:28:33 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 200700 kb
Host smart-ba90b04f-bec3-48d2-a814-38a9ca1cd60d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887950276 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.887950276
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.525001982
Short name T874
Test name
Test status
Simulation time 569482083 ps
CPU time 2.17 seconds
Started Dec 20 12:28:20 PM PST 23
Finished Dec 20 12:28:58 PM PST 23
Peak memory 200632 kb
Host smart-c8dcfb31-645e-4989-b1c6-34cca0fd139f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525001982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.525001982
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2853067600
Short name T900
Test name
Test status
Simulation time 508509809 ps
CPU time 0.83 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:03 PM PST 23
Peak memory 200568 kb
Host smart-5473dcf4-21ae-40d8-a460-f9d498bdb06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853067600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2853067600
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3948810306
Short name T386
Test name
Test status
Simulation time 3909106830 ps
CPU time 8.56 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 200948 kb
Host smart-905c3335-017e-4ca6-a98c-b3f87b686657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948810306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3948810306
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2336975851
Short name T66
Test name
Test status
Simulation time 737386957 ps
CPU time 1.92 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 200936 kb
Host smart-b8334a62-4f56-4b0f-80f1-6ee6bdbcc43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336975851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2336975851
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1506227459
Short name T196
Test name
Test status
Simulation time 8420948057 ps
CPU time 6.34 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 200788 kb
Host smart-203b9c6a-ffef-436f-9df9-4e07797c29d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506227459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1506227459
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1211124336
Short name T365
Test name
Test status
Simulation time 414261259 ps
CPU time 0.98 seconds
Started Dec 20 12:28:30 PM PST 23
Finished Dec 20 12:29:04 PM PST 23
Peak memory 200736 kb
Host smart-ba2fd4f8-702b-41c5-9558-3278ab63b54e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211124336 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1211124336
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1468504850
Short name T79
Test name
Test status
Simulation time 456179310 ps
CPU time 1.31 seconds
Started Dec 20 12:28:25 PM PST 23
Finished Dec 20 12:29:00 PM PST 23
Peak memory 200592 kb
Host smart-11036986-f76f-470f-9063-d356e69691da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468504850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1468504850
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1277796364
Short name T84
Test name
Test status
Simulation time 457192969 ps
CPU time 0.71 seconds
Started Dec 20 12:28:32 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 200312 kb
Host smart-d214d4be-bdf3-4b5e-9d11-c20f085a15c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277796364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1277796364
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4019472090
Short name T393
Test name
Test status
Simulation time 2327095624 ps
CPU time 8.14 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200728 kb
Host smart-26b00382-519f-4720-9739-41faefb92bd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019472090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.4019472090
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1539598406
Short name T899
Test name
Test status
Simulation time 722548477 ps
CPU time 2.23 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200764 kb
Host smart-2265df53-3476-4fa0-93de-f9658c8d8dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539598406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1539598406
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.255763675
Short name T64
Test name
Test status
Simulation time 4172624210 ps
CPU time 11.46 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:18 PM PST 23
Peak memory 200948 kb
Host smart-62857ef8-cc6c-4784-a76a-ccc7d685dde9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255763675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.255763675
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3624429320
Short name T191
Test name
Test status
Simulation time 511238929 ps
CPU time 1.3 seconds
Started Dec 20 12:28:19 PM PST 23
Finished Dec 20 12:28:57 PM PST 23
Peak memory 200724 kb
Host smart-f15ee871-2b29-473e-bbe6-a87233dfe5e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624429320 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3624429320
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1024707231
Short name T880
Test name
Test status
Simulation time 553342671 ps
CPU time 0.99 seconds
Started Dec 20 12:28:18 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 200564 kb
Host smart-b7faa66e-c494-487e-94d7-8c491fced6de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024707231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1024707231
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1475919990
Short name T879
Test name
Test status
Simulation time 356074893 ps
CPU time 1.41 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200120 kb
Host smart-9c5c2aa1-91ff-4c79-8ab5-afb3f99d83d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475919990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1475919990
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3271851231
Short name T368
Test name
Test status
Simulation time 1886494165 ps
CPU time 3.45 seconds
Started Dec 20 12:28:26 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200672 kb
Host smart-c433302d-a3ee-4841-b7fb-ad5409445c14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271851231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3271851231
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4231365127
Short name T859
Test name
Test status
Simulation time 434015600 ps
CPU time 2.2 seconds
Started Dec 20 12:28:32 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200904 kb
Host smart-fee227a5-c302-4dc7-babc-770c6423cc6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231365127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4231365127
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.190421933
Short name T902
Test name
Test status
Simulation time 447174390 ps
CPU time 1.87 seconds
Started Dec 20 12:28:25 PM PST 23
Finished Dec 20 12:29:00 PM PST 23
Peak memory 200700 kb
Host smart-679f65f2-d668-4b69-b76c-5238ff1038f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190421933 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.190421933
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2854239013
Short name T73
Test name
Test status
Simulation time 526360606 ps
CPU time 0.99 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200684 kb
Host smart-b208a387-8f00-4639-8c70-447469ff4bec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854239013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2854239013
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2598443901
Short name T372
Test name
Test status
Simulation time 479704512 ps
CPU time 0.83 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:03 PM PST 23
Peak memory 200336 kb
Host smart-d165f665-dc9d-4f3d-ab85-b419c34303dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598443901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2598443901
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3735533845
Short name T378
Test name
Test status
Simulation time 4771061420 ps
CPU time 3.87 seconds
Started Dec 20 12:28:07 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 200680 kb
Host smart-2e0236ea-189a-4a6b-a669-6054379e4324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735533845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3735533845
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.699059959
Short name T395
Test name
Test status
Simulation time 349417563 ps
CPU time 2.24 seconds
Started Dec 20 12:28:26 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200876 kb
Host smart-17799d35-b5da-491f-bb33-3c436cf50e46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699059959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.699059959
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3309721125
Short name T907
Test name
Test status
Simulation time 4712150648 ps
CPU time 4.16 seconds
Started Dec 20 12:28:30 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200892 kb
Host smart-85c634bf-4632-4b51-994f-f2f1a2e76579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309721125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3309721125
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3291436193
Short name T194
Test name
Test status
Simulation time 556643713 ps
CPU time 1.11 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 200776 kb
Host smart-c0066d8d-4645-4e16-831e-d901557f6da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291436193 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3291436193
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3446637826
Short name T858
Test name
Test status
Simulation time 444715014 ps
CPU time 1.67 seconds
Started Dec 20 12:29:32 PM PST 23
Finished Dec 20 12:29:55 PM PST 23
Peak memory 200648 kb
Host smart-aae57c10-a2a3-444d-942f-1ae46d515374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446637826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3446637826
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.47674821
Short name T360
Test name
Test status
Simulation time 371858642 ps
CPU time 0.71 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:01 PM PST 23
Peak memory 200356 kb
Host smart-38541ab5-d3a1-417d-b66d-297d767d52ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47674821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.47674821
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2972162757
Short name T192
Test name
Test status
Simulation time 5141856313 ps
CPU time 2.34 seconds
Started Dec 20 12:28:20 PM PST 23
Finished Dec 20 12:28:58 PM PST 23
Peak memory 200888 kb
Host smart-138a59b6-a359-448b-9ac4-16dcb4b6a88d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972162757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2972162757
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3588941363
Short name T872
Test name
Test status
Simulation time 567146261 ps
CPU time 2.47 seconds
Started Dec 20 12:28:06 PM PST 23
Finished Dec 20 12:28:48 PM PST 23
Peak memory 200940 kb
Host smart-1000dc56-06d7-4981-b357-db98ce8044be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588941363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3588941363
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.210673319
Short name T897
Test name
Test status
Simulation time 4266016316 ps
CPU time 5.59 seconds
Started Dec 20 12:28:19 PM PST 23
Finished Dec 20 12:29:01 PM PST 23
Peak memory 200940 kb
Host smart-bfe4dbfa-3ef0-40c0-a227-707d8b2e00eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210673319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.210673319
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.133480723
Short name T857
Test name
Test status
Simulation time 526987859 ps
CPU time 2.28 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 200804 kb
Host smart-f2d7c26d-55d8-478d-8199-fd16c961885e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133480723 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.133480723
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2867560445
Short name T81
Test name
Test status
Simulation time 539404990 ps
CPU time 1.39 seconds
Started Dec 20 12:28:30 PM PST 23
Finished Dec 20 12:29:04 PM PST 23
Peak memory 200684 kb
Host smart-e220e767-2c52-4c60-b8cf-22653c854364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867560445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2867560445
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3728914394
Short name T6
Test name
Test status
Simulation time 423872526 ps
CPU time 0.73 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200648 kb
Host smart-a9e32bcd-7ceb-4932-99f4-98e8e88a98e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728914394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3728914394
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3625496042
Short name T8
Test name
Test status
Simulation time 2836350603 ps
CPU time 1.51 seconds
Started Dec 20 12:28:15 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200684 kb
Host smart-46121ca3-467c-4278-a9f7-ddc01d8b71b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625496042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3625496042
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.281339786
Short name T41
Test name
Test status
Simulation time 316470778 ps
CPU time 3.17 seconds
Started Dec 20 12:28:31 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200956 kb
Host smart-c292c9f0-1637-4cc2-954f-b2e2ac2446bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281339786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.281339786
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2079699113
Short name T88
Test name
Test status
Simulation time 8057856771 ps
CPU time 11.36 seconds
Started Dec 20 12:28:09 PM PST 23
Finished Dec 20 12:29:01 PM PST 23
Peak memory 200924 kb
Host smart-bf40b753-65ab-401e-bb5c-93c378afd6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079699113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2079699113
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3206658765
Short name T877
Test name
Test status
Simulation time 511077562 ps
CPU time 1.17 seconds
Started Dec 20 12:28:12 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 200700 kb
Host smart-7dff5474-99ae-453e-8c7d-c8af8734ec4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206658765 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3206658765
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.917910149
Short name T392
Test name
Test status
Simulation time 550545004 ps
CPU time 0.79 seconds
Started Dec 20 12:28:20 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 200648 kb
Host smart-b19d0cb0-70d1-4c15-86d9-04a9a6460565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917910149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.917910149
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2318478721
Short name T40
Test name
Test status
Simulation time 464596370 ps
CPU time 1.16 seconds
Started Dec 20 12:28:28 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200392 kb
Host smart-1adeaec9-2478-4618-bc55-dfa79ab23c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318478721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2318478721
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1949726503
Short name T892
Test name
Test status
Simulation time 3888463386 ps
CPU time 19.32 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 200880 kb
Host smart-777aeac2-c3d8-4657-8ffc-9ba164a8eb15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949726503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1949726503
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.87844296
Short name T396
Test name
Test status
Simulation time 380713478 ps
CPU time 2.89 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 217252 kb
Host smart-229010aa-6820-4642-ac31-d3ef0048404f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87844296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.87844296
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.304409860
Short name T344
Test name
Test status
Simulation time 7924018307 ps
CPU time 11.01 seconds
Started Dec 20 12:28:18 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 200904 kb
Host smart-195673cf-d98e-4139-8f22-2c4d8bdb10fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304409860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.304409860
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.620774146
Short name T71
Test name
Test status
Simulation time 702702630 ps
CPU time 2.07 seconds
Started Dec 20 12:27:57 PM PST 23
Finished Dec 20 12:28:37 PM PST 23
Peak memory 200852 kb
Host smart-b7093810-5509-4f9d-8b52-804459a5aa7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620774146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.620774146
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2006763030
Short name T875
Test name
Test status
Simulation time 1124308167 ps
CPU time 5.45 seconds
Started Dec 20 12:28:05 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 200788 kb
Host smart-0cfd5840-948f-40da-821a-4c36c8c3accb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006763030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2006763030
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1187544425
Short name T871
Test name
Test status
Simulation time 892297215 ps
CPU time 1.13 seconds
Started Dec 20 12:28:22 PM PST 23
Finished Dec 20 12:28:57 PM PST 23
Peak memory 200652 kb
Host smart-87bb395a-d3e8-4ab8-8945-bc66aaaa03a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187544425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1187544425
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.503929951
Short name T861
Test name
Test status
Simulation time 398872490 ps
CPU time 1.7 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 200408 kb
Host smart-793b4a53-ca59-46f5-9f0f-62503266879e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503929951 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.503929951
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.930370907
Short name T72
Test name
Test status
Simulation time 570373229 ps
CPU time 0.91 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:20 PM PST 23
Peak memory 200656 kb
Host smart-1deca009-0a07-4b24-a5be-211b77e2754f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930370907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.930370907
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3244240411
Short name T379
Test name
Test status
Simulation time 525055881 ps
CPU time 0.9 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 200088 kb
Host smart-2eb2db8d-e0d3-4b62-8a1a-b2f02787f324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244240411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3244240411
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2268730166
Short name T866
Test name
Test status
Simulation time 2426354435 ps
CPU time 6.03 seconds
Started Dec 20 12:27:55 PM PST 23
Finished Dec 20 12:28:37 PM PST 23
Peak memory 200708 kb
Host smart-a6dc4828-c055-48e2-9f0b-a60274b6ffbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268730166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2268730166
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2260228328
Short name T903
Test name
Test status
Simulation time 450812329 ps
CPU time 2.25 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:31 PM PST 23
Peak memory 200884 kb
Host smart-4a51c806-f0f7-431d-b7a6-edf70af0f413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260228328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2260228328
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1815664937
Short name T87
Test name
Test status
Simulation time 8548138553 ps
CPU time 7.06 seconds
Started Dec 20 12:27:59 PM PST 23
Finished Dec 20 12:28:44 PM PST 23
Peak memory 200832 kb
Host smart-73c7630a-1911-4d59-ac79-e3dd67499b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815664937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1815664937
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2220182526
Short name T381
Test name
Test status
Simulation time 434412398 ps
CPU time 0.9 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200344 kb
Host smart-65b4d3a1-97fc-4c8f-9f02-42fb414f3245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220182526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2220182526
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.9755863
Short name T889
Test name
Test status
Simulation time 435913550 ps
CPU time 1.62 seconds
Started Dec 20 12:28:33 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200528 kb
Host smart-d2733d2e-783f-4268-b84c-8fc34782fdc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9755863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.9755863
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.1476642612
Short name T376
Test name
Test status
Simulation time 484560346 ps
CPU time 0.73 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:14 PM PST 23
Peak memory 200164 kb
Host smart-c5b47b88-d37e-4b04-8872-ddee2ab05450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476642612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.1476642612
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2720964133
Short name T359
Test name
Test status
Simulation time 442956058 ps
CPU time 1.15 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 200476 kb
Host smart-463bcf04-e654-4316-a6e1-0cb2726eec75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720964133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2720964133
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2199491733
Short name T860
Test name
Test status
Simulation time 400461779 ps
CPU time 0.79 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 200280 kb
Host smart-c4b1ef82-847b-4e60-a707-cfe9365fa5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199491733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2199491733
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3420674491
Short name T870
Test name
Test status
Simulation time 431013725 ps
CPU time 1.65 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 200488 kb
Host smart-1b98573f-611e-4d86-b045-b408c1c695df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420674491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3420674491
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4045406326
Short name T389
Test name
Test status
Simulation time 523582444 ps
CPU time 1.91 seconds
Started Dec 20 12:28:30 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 200504 kb
Host smart-46b0118c-4928-42fb-8e92-2c388a1fb0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045406326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4045406326
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1435212358
Short name T366
Test name
Test status
Simulation time 285186788 ps
CPU time 1.23 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 200364 kb
Host smart-bc264902-a57a-42d9-b3a4-ccbae0bc03b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435212358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1435212358
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2473828884
Short name T873
Test name
Test status
Simulation time 418496128 ps
CPU time 0.81 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:29:24 PM PST 23
Peak memory 200340 kb
Host smart-809bc182-ec5c-4409-8d40-251470633855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473828884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2473828884
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3835096490
Short name T867
Test name
Test status
Simulation time 472582513 ps
CPU time 0.68 seconds
Started Dec 20 12:29:23 PM PST 23
Finished Dec 20 12:29:47 PM PST 23
Peak memory 200324 kb
Host smart-3e7aa9d1-6724-4d9d-8e4a-0506ae8c0b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835096490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3835096490
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2313583976
Short name T374
Test name
Test status
Simulation time 947566331 ps
CPU time 1.92 seconds
Started Dec 20 12:28:14 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200900 kb
Host smart-e78d3a57-710c-4845-9374-bb4d98b43a6b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313583976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2313583976
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3176703427
Short name T382
Test name
Test status
Simulation time 53004343780 ps
CPU time 70.75 seconds
Started Dec 20 12:27:56 PM PST 23
Finished Dec 20 12:29:44 PM PST 23
Peak memory 200840 kb
Host smart-9c515f87-72c3-4630-9315-ad01d2a19423
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176703427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3176703427
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2395539019
Short name T83
Test name
Test status
Simulation time 1230141741 ps
CPU time 3.62 seconds
Started Dec 20 12:27:52 PM PST 23
Finished Dec 20 12:28:31 PM PST 23
Peak memory 200700 kb
Host smart-945fb19a-67a6-4b1e-9801-58ade17d7dde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395539019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2395539019
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2042085840
Short name T882
Test name
Test status
Simulation time 352904855 ps
CPU time 1.1 seconds
Started Dec 20 12:28:23 PM PST 23
Finished Dec 20 12:28:58 PM PST 23
Peak memory 200632 kb
Host smart-87f1b00a-5a61-4539-9a9d-5ec1e153bb27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042085840 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2042085840
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1612303891
Short name T75
Test name
Test status
Simulation time 552826912 ps
CPU time 1 seconds
Started Dec 20 12:27:57 PM PST 23
Finished Dec 20 12:28:36 PM PST 23
Peak memory 200540 kb
Host smart-a4ecb1d8-0e99-4c0d-b659-2d7ae3a6440f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612303891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1612303891
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2177511460
Short name T856
Test name
Test status
Simulation time 290870840 ps
CPU time 1.2 seconds
Started Dec 20 12:30:21 PM PST 23
Finished Dec 20 12:31:26 PM PST 23
Peak memory 200060 kb
Host smart-e7b121cb-0a5a-4252-a146-de28411564c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177511460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2177511460
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1817759978
Short name T361
Test name
Test status
Simulation time 4274578578 ps
CPU time 10.98 seconds
Started Dec 20 12:28:20 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200880 kb
Host smart-48103acb-32b8-4c13-a53c-ae0831ca0b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817759978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1817759978
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2706415995
Short name T89
Test name
Test status
Simulation time 1067615514 ps
CPU time 1.69 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 200568 kb
Host smart-7622bf25-7a65-460f-8dcf-ae49c256704a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706415995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2706415995
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4087199285
Short name T896
Test name
Test status
Simulation time 4517268279 ps
CPU time 6.91 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:35 PM PST 23
Peak memory 201076 kb
Host smart-91bc4193-eaec-4349-8104-23fe72dc3c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087199285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.4087199285
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1260271149
Short name T878
Test name
Test status
Simulation time 393000282 ps
CPU time 1.54 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200620 kb
Host smart-c29c5283-d637-44ea-b54c-71ff9bb5c352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260271149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1260271149
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.463646893
Short name T387
Test name
Test status
Simulation time 408305714 ps
CPU time 1.7 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:18 PM PST 23
Peak memory 200408 kb
Host smart-167ce86a-9153-4957-9d48-4ed58f234451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463646893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.463646893
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4215833135
Short name T375
Test name
Test status
Simulation time 461835468 ps
CPU time 1.62 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200540 kb
Host smart-56b12b04-d161-4f03-b3b0-0cec5c9332d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215833135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4215833135
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.575524087
Short name T357
Test name
Test status
Simulation time 477970118 ps
CPU time 1.35 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200404 kb
Host smart-64a82dcb-8325-4139-87d0-83868832e1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575524087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.575524087
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1191266107
Short name T369
Test name
Test status
Simulation time 482656210 ps
CPU time 0.9 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200388 kb
Host smart-12955a1f-b856-43d6-9cbc-3dcca8f2a400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191266107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1191266107
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.96484417
Short name T887
Test name
Test status
Simulation time 464662123 ps
CPU time 1.67 seconds
Started Dec 20 12:28:58 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 200656 kb
Host smart-93917ed8-5369-4470-8459-298fd9e83c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96484417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.96484417
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2356795166
Short name T377
Test name
Test status
Simulation time 532729933 ps
CPU time 0.94 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 200248 kb
Host smart-24cff78a-dfb8-4154-beb9-10d5cc4679b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356795166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2356795166
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3657280528
Short name T26
Test name
Test status
Simulation time 369114942 ps
CPU time 0.88 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:18 PM PST 23
Peak memory 200328 kb
Host smart-9cbdfdfe-ac57-4ee6-abd4-7bde33722969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657280528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3657280528
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.942821002
Short name T197
Test name
Test status
Simulation time 489199622 ps
CPU time 1.75 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 200336 kb
Host smart-4b8e391e-bc9c-4029-b1bb-cad27cbec3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942821002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.942821002
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3953591491
Short name T862
Test name
Test status
Simulation time 420404577 ps
CPU time 1.61 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 200448 kb
Host smart-ac250e10-db81-41ab-bd86-30008a7dd425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953591491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3953591491
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3204566189
Short name T2
Test name
Test status
Simulation time 601534817 ps
CPU time 2.69 seconds
Started Dec 20 12:28:07 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 200716 kb
Host smart-e2fcab35-fbec-47a6-b96d-30650cb2327a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204566189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3204566189
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1663824324
Short name T80
Test name
Test status
Simulation time 23778856802 ps
CPU time 31.88 seconds
Started Dec 20 12:28:07 PM PST 23
Finished Dec 20 12:29:20 PM PST 23
Peak memory 200936 kb
Host smart-364ac5ee-7ff6-46c4-ad5f-5d9f5ed9c89e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663824324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1663824324
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2030661658
Short name T391
Test name
Test status
Simulation time 1055300239 ps
CPU time 1.69 seconds
Started Dec 20 12:28:24 PM PST 23
Finished Dec 20 12:28:59 PM PST 23
Peak memory 200712 kb
Host smart-ddf95da0-e654-48f6-96de-f35398966f30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030661658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2030661658
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.460671353
Short name T885
Test name
Test status
Simulation time 316450644 ps
CPU time 1.46 seconds
Started Dec 20 12:28:10 PM PST 23
Finished Dec 20 12:28:52 PM PST 23
Peak memory 200500 kb
Host smart-75d240df-4e97-4116-b29f-3a75c604cd67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460671353 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.460671353
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.736989275
Short name T890
Test name
Test status
Simulation time 457792055 ps
CPU time 1.71 seconds
Started Dec 20 12:28:03 PM PST 23
Finished Dec 20 12:28:44 PM PST 23
Peak memory 200572 kb
Host smart-2ade3f7e-ca7e-4ce7-b8b4-7c244f320e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736989275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.736989275
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1553875723
Short name T358
Test name
Test status
Simulation time 525638924 ps
CPU time 1.06 seconds
Started Dec 20 12:28:08 PM PST 23
Finished Dec 20 12:28:49 PM PST 23
Peak memory 200516 kb
Host smart-906138e1-7e34-4dc9-acc2-77349156c43c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553875723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1553875723
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1185735415
Short name T398
Test name
Test status
Simulation time 2584981336 ps
CPU time 3.59 seconds
Started Dec 20 12:28:11 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200780 kb
Host smart-e7a184cc-0112-4b66-b4e0-9318cfe12a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185735415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1185735415
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3375320481
Short name T868
Test name
Test status
Simulation time 446382004 ps
CPU time 2.58 seconds
Started Dec 20 12:28:02 PM PST 23
Finished Dec 20 12:28:43 PM PST 23
Peak memory 200892 kb
Host smart-b60ea7c9-4b7b-4840-a34c-98c177b35ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375320481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3375320481
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1795897381
Short name T193
Test name
Test status
Simulation time 4262985883 ps
CPU time 4.09 seconds
Started Dec 20 12:28:09 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 200856 kb
Host smart-cb943abe-02ee-44bb-8bea-f72054c1ec10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795897381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1795897381
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.312838957
Short name T363
Test name
Test status
Simulation time 473133141 ps
CPU time 0.87 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 200244 kb
Host smart-8900400b-3e6c-47cf-a301-71c04824d655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312838957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.312838957
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1115314918
Short name T394
Test name
Test status
Simulation time 351173182 ps
CPU time 0.8 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 200384 kb
Host smart-69e67c94-c93a-4346-83a4-26d1c2c415be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115314918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1115314918
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.771393326
Short name T883
Test name
Test status
Simulation time 496226241 ps
CPU time 1.2 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200580 kb
Host smart-a69969ba-7afb-4c60-a6b1-4866c72ecc04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771393326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.771393326
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3929141192
Short name T863
Test name
Test status
Simulation time 375492593 ps
CPU time 1.55 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 200284 kb
Host smart-1b31e567-aee8-432f-8096-197c83e5d10f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929141192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3929141192
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3470548278
Short name T388
Test name
Test status
Simulation time 415782630 ps
CPU time 0.83 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 200648 kb
Host smart-c82c306a-3549-4e75-aad6-bbd79e2ed954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470548278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3470548278
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.444458632
Short name T400
Test name
Test status
Simulation time 547134620 ps
CPU time 0.96 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 200544 kb
Host smart-ffacab09-52a6-42f8-81c0-c48f45f870a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444458632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.444458632
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1492041772
Short name T390
Test name
Test status
Simulation time 437734473 ps
CPU time 1.17 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 200272 kb
Host smart-8a3ff149-652e-4fb7-84f7-114b6abbe759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492041772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1492041772
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3377858284
Short name T367
Test name
Test status
Simulation time 451958657 ps
CPU time 0.87 seconds
Started Dec 20 12:28:44 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 200284 kb
Host smart-4dafebfd-a469-4254-9bea-bf8c7197bcbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377858284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3377858284
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3229860234
Short name T198
Test name
Test status
Simulation time 298772435 ps
CPU time 1.24 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 200492 kb
Host smart-5792f5af-dea2-465e-8ba2-ea5955541184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229860234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3229860234
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.722456993
Short name T869
Test name
Test status
Simulation time 389810552 ps
CPU time 1.69 seconds
Started Dec 20 12:28:04 PM PST 23
Finished Dec 20 12:28:45 PM PST 23
Peak memory 200588 kb
Host smart-16594fcd-b94e-4360-9e92-45693727d8fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722456993 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.722456993
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.312443943
Short name T85
Test name
Test status
Simulation time 332180589 ps
CPU time 0.81 seconds
Started Dec 20 12:28:28 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200620 kb
Host smart-10a485fa-b013-4c6b-9917-0741a0596a3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312443943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.312443943
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.997620289
Short name T31
Test name
Test status
Simulation time 452420343 ps
CPU time 0.79 seconds
Started Dec 20 12:28:25 PM PST 23
Finished Dec 20 12:28:59 PM PST 23
Peak memory 200568 kb
Host smart-e7c3053e-a078-4403-91de-1d5b177004ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997620289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.997620289
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2522539004
Short name T397
Test name
Test status
Simulation time 2191515756 ps
CPU time 2.3 seconds
Started Dec 20 12:28:30 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 200724 kb
Host smart-17e96857-c8fe-43c5-9548-ede8c7ce8d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522539004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2522539004
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.665859882
Short name T904
Test name
Test status
Simulation time 4153558121 ps
CPU time 6.47 seconds
Started Dec 20 12:28:12 PM PST 23
Finished Dec 20 12:28:58 PM PST 23
Peak memory 201080 kb
Host smart-fa588667-37dc-4126-bbbf-8abcca68ea8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665859882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.665859882
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1320175521
Short name T881
Test name
Test status
Simulation time 526555002 ps
CPU time 1.41 seconds
Started Dec 20 12:28:11 PM PST 23
Finished Dec 20 12:28:52 PM PST 23
Peak memory 200724 kb
Host smart-aef346bf-f779-4adb-b04e-ba9685774890
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320175521 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1320175521
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3345255323
Short name T78
Test name
Test status
Simulation time 508690713 ps
CPU time 1.02 seconds
Started Dec 20 12:28:33 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 200656 kb
Host smart-9ab4790c-2b63-4513-8434-34b84830c941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345255323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3345255323
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2156586162
Short name T908
Test name
Test status
Simulation time 375149291 ps
CPU time 1.49 seconds
Started Dec 20 12:28:17 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 200352 kb
Host smart-8c15c806-1bdd-4cc2-bc6d-38645bb4a723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156586162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2156586162
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1412902839
Short name T364
Test name
Test status
Simulation time 2352296217 ps
CPU time 8.69 seconds
Started Dec 20 12:28:02 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 200752 kb
Host smart-6d0ffd1d-425a-4bb3-ba46-ef145b4fec43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412902839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1412902839
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.355859410
Short name T38
Test name
Test status
Simulation time 587046360 ps
CPU time 1.39 seconds
Started Dec 20 12:28:07 PM PST 23
Finished Dec 20 12:28:48 PM PST 23
Peak memory 200884 kb
Host smart-0735892b-620b-49e1-9609-170c9b8d8124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355859410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.355859410
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.104894167
Short name T195
Test name
Test status
Simulation time 4609556694 ps
CPU time 3.79 seconds
Started Dec 20 12:28:12 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 201056 kb
Host smart-bebdcea7-259a-492a-87cf-1a143d0a5dd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104894167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.104894167
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1699122817
Short name T886
Test name
Test status
Simulation time 557581717 ps
CPU time 1.51 seconds
Started Dec 20 12:28:31 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 200596 kb
Host smart-71dc1711-b8ce-4d1b-bf8c-1936f098cd53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699122817 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1699122817
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3354354242
Short name T74
Test name
Test status
Simulation time 401612221 ps
CPU time 1.2 seconds
Started Dec 20 12:28:15 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200668 kb
Host smart-38ed57bb-3217-49fa-8ac1-f1dfdaf75b10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354354242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3354354242
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2705565778
Short name T356
Test name
Test status
Simulation time 457432840 ps
CPU time 0.93 seconds
Started Dec 20 12:28:13 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 200248 kb
Host smart-aac250fa-4caa-4129-8d47-d16135d9dbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705565778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2705565778
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3057767409
Short name T380
Test name
Test status
Simulation time 4268330773 ps
CPU time 14.79 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:37 PM PST 23
Peak memory 200872 kb
Host smart-779449b9-7b9c-4a8b-8a6d-a390589e3e6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057767409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3057767409
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2327095117
Short name T905
Test name
Test status
Simulation time 667765278 ps
CPU time 3.13 seconds
Started Dec 20 12:28:05 PM PST 23
Finished Dec 20 12:28:48 PM PST 23
Peak memory 200848 kb
Host smart-90cf13a2-dd8e-438c-babb-56a725afd07d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327095117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2327095117
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1403502511
Short name T1
Test name
Test status
Simulation time 8969878683 ps
CPU time 25.61 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 200968 kb
Host smart-51e14b35-0473-4b03-a72c-89e1c379b65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403502511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1403502511
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3528995768
Short name T86
Test name
Test status
Simulation time 550195699 ps
CPU time 1.33 seconds
Started Dec 20 12:28:05 PM PST 23
Finished Dec 20 12:28:45 PM PST 23
Peak memory 209084 kb
Host smart-57930952-55dc-4a0e-89f6-10e70061f46f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528995768 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3528995768
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4147601129
Short name T9
Test name
Test status
Simulation time 377885584 ps
CPU time 0.76 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 200688 kb
Host smart-f529fa82-a925-4972-b809-ba274d22aa25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147601129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4147601129
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3614736421
Short name T891
Test name
Test status
Simulation time 341137458 ps
CPU time 0.8 seconds
Started Dec 20 12:28:15 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200316 kb
Host smart-441f1578-cfd5-406b-86ba-ec85e638fc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614736421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3614736421
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2760103436
Short name T32
Test name
Test status
Simulation time 2266592710 ps
CPU time 1.26 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 200676 kb
Host smart-0939e417-200a-4d66-aedf-79e99e2e2b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760103436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2760103436
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1074624113
Short name T63
Test name
Test status
Simulation time 427957640 ps
CPU time 2.32 seconds
Started Dec 20 12:28:27 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 200884 kb
Host smart-044799d2-d532-45b7-b622-2bf9fc5daa52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074624113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1074624113
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.236863908
Short name T68
Test name
Test status
Simulation time 4594848096 ps
CPU time 4.05 seconds
Started Dec 20 12:28:21 PM PST 23
Finished Dec 20 12:29:00 PM PST 23
Peak memory 200852 kb
Host smart-f3e59009-0a15-48a4-b325-a58ee5a50758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236863908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.236863908
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.353725934
Short name T384
Test name
Test status
Simulation time 458817847 ps
CPU time 1.75 seconds
Started Dec 20 12:28:10 PM PST 23
Finished Dec 20 12:28:52 PM PST 23
Peak memory 200748 kb
Host smart-d3840170-0c6c-4637-9eb4-a5dac89f29b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353725934 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.353725934
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.893729161
Short name T876
Test name
Test status
Simulation time 412973163 ps
CPU time 1.12 seconds
Started Dec 20 12:28:17 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 200704 kb
Host smart-da5daaea-3d72-4bd0-b4e0-bcfcc395e7c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893729161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.893729161
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2115201040
Short name T370
Test name
Test status
Simulation time 336905402 ps
CPU time 0.84 seconds
Started Dec 20 12:28:16 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200404 kb
Host smart-edd70ae4-5581-4816-ac24-0bf2948f6178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115201040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2115201040
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3604429549
Short name T33
Test name
Test status
Simulation time 4285416307 ps
CPU time 5.16 seconds
Started Dec 20 12:28:18 PM PST 23
Finished Dec 20 12:29:00 PM PST 23
Peak memory 200900 kb
Host smart-ddce84a8-6654-46b4-a1b2-ea0afd08a7e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604429549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3604429549
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2584828372
Short name T39
Test name
Test status
Simulation time 434129339 ps
CPU time 1.56 seconds
Started Dec 20 12:28:15 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 200944 kb
Host smart-23f67e3a-56f6-4a23-bf59-c81e24ef81ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584828372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2584828372
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1428663668
Short name T901
Test name
Test status
Simulation time 8079909381 ps
CPU time 7.81 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 200940 kb
Host smart-b6928e14-5088-456b-89b3-5883346f38c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428663668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1428663668
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.537114664
Short name T338
Test name
Test status
Simulation time 326967450665 ps
CPU time 375.65 seconds
Started Dec 20 12:47:17 PM PST 23
Finished Dec 20 12:54:26 PM PST 23
Peak memory 201004 kb
Host smart-33126198-bf0c-4967-832c-541fbdd9f3a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537114664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.537114664
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.151679991
Short name T771
Test name
Test status
Simulation time 331689163951 ps
CPU time 484.65 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 201004 kb
Host smart-6807f45d-452f-4f27-92c3-8355a89c8f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151679991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.151679991
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2096464913
Short name T174
Test name
Test status
Simulation time 325152897747 ps
CPU time 173.34 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:51:06 PM PST 23
Peak memory 200992 kb
Host smart-1025cb5b-2651-4c53-b59d-90154f99171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096464913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2096464913
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.944367217
Short name T838
Test name
Test status
Simulation time 489905948002 ps
CPU time 1151.83 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 01:07:16 PM PST 23
Peak memory 201032 kb
Host smart-f990986f-3f5b-450a-ada6-fcfd3e5e588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944367217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.944367217
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2364208533
Short name T639
Test name
Test status
Simulation time 325855733448 ps
CPU time 385.79 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:54:55 PM PST 23
Peak memory 200744 kb
Host smart-db1fc00a-c188-40fd-9fda-f09340b0e0b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364208533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2364208533
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1106529997
Short name T845
Test name
Test status
Simulation time 490682924356 ps
CPU time 299.78 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:53:29 PM PST 23
Peak memory 200904 kb
Host smart-eb8e7597-f58b-481e-9d26-6d9fdb6a54d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106529997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1106529997
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.401921778
Short name T527
Test name
Test status
Simulation time 44384923462 ps
CPU time 7.45 seconds
Started Dec 20 12:47:24 PM PST 23
Finished Dec 20 12:48:37 PM PST 23
Peak memory 200548 kb
Host smart-093e2328-43b3-4fcf-8fac-339e3dbad8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401921778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.401921778
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3184246326
Short name T412
Test name
Test status
Simulation time 4712955602 ps
CPU time 3.25 seconds
Started Dec 20 12:47:35 PM PST 23
Finished Dec 20 12:48:58 PM PST 23
Peak memory 200480 kb
Host smart-8f91a8fc-d0ff-4623-9b1f-efaca9a89c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184246326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3184246326
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3680813831
Short name T545
Test name
Test status
Simulation time 5934366451 ps
CPU time 13.66 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 12:48:13 PM PST 23
Peak memory 200768 kb
Host smart-58ae2b5e-f0ec-4c7a-948d-b339042636b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680813831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3680813831
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3006774420
Short name T307
Test name
Test status
Simulation time 229636006524 ps
CPU time 735.99 seconds
Started Dec 20 12:47:44 PM PST 23
Finished Dec 20 01:01:27 PM PST 23
Peak memory 209476 kb
Host smart-572514ca-5ad5-4957-a365-639d75aabd94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006774420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3006774420
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3059786201
Short name T340
Test name
Test status
Simulation time 3446125879 ps
CPU time 8.41 seconds
Started Dec 20 12:47:44 PM PST 23
Finished Dec 20 12:49:21 PM PST 23
Peak memory 201084 kb
Host smart-93879b29-c60c-4a72-ad57-0c22a4d37f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059786201 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3059786201
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.4169614368
Short name T44
Test name
Test status
Simulation time 367041719 ps
CPU time 1.4 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:48:21 PM PST 23
Peak memory 200660 kb
Host smart-1946b22b-e4fa-4d84-94b6-e0aff902d386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169614368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.4169614368
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3135354062
Short name T736
Test name
Test status
Simulation time 160659599878 ps
CPU time 213.78 seconds
Started Dec 20 12:47:52 PM PST 23
Finished Dec 20 12:53:05 PM PST 23
Peak memory 201044 kb
Host smart-9c4612eb-5d33-416a-b7d7-f880f458702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135354062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3135354062
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1847593855
Short name T16
Test name
Test status
Simulation time 169408280990 ps
CPU time 72.71 seconds
Started Dec 20 12:48:04 PM PST 23
Finished Dec 20 12:50:28 PM PST 23
Peak memory 200892 kb
Host smart-4fed8c7b-713e-4561-98d1-b3c503a1582e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847593855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1847593855
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2598232568
Short name T620
Test name
Test status
Simulation time 163264583542 ps
CPU time 369.84 seconds
Started Dec 20 12:47:50 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 201004 kb
Host smart-dc684f90-158e-4d0f-a933-52fb2b492e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598232568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2598232568
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2408185895
Short name T314
Test name
Test status
Simulation time 525549581408 ps
CPU time 1176.25 seconds
Started Dec 20 12:48:16 PM PST 23
Finished Dec 20 01:09:21 PM PST 23
Peak memory 200952 kb
Host smart-727a0b32-7c91-4ead-a218-f778cc9fe503
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408185895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2408185895
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1913183129
Short name T453
Test name
Test status
Simulation time 160648467719 ps
CPU time 101.4 seconds
Started Dec 20 12:48:15 PM PST 23
Finished Dec 20 12:51:33 PM PST 23
Peak memory 201000 kb
Host smart-7c8aac92-11c0-441c-b6b5-ec6c54aaa094
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913183129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1913183129
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2664570652
Short name T617
Test name
Test status
Simulation time 71551109755 ps
CPU time 235.61 seconds
Started Dec 20 12:47:52 PM PST 23
Finished Dec 20 12:53:12 PM PST 23
Peak memory 201376 kb
Host smart-408ac825-14b5-47ab-835a-ec353cd7fa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664570652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2664570652
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.975738217
Short name T500
Test name
Test status
Simulation time 30965022745 ps
CPU time 19.99 seconds
Started Dec 20 12:47:08 PM PST 23
Finished Dec 20 12:48:11 PM PST 23
Peak memory 200852 kb
Host smart-c1181e6e-52d0-4280-be94-8a6654012671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975738217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.975738217
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3975687880
Short name T680
Test name
Test status
Simulation time 4953506229 ps
CPU time 6.56 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:48:27 PM PST 23
Peak memory 200804 kb
Host smart-0ed053f2-8fb6-446a-8ddc-881613b35868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975687880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3975687880
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2715986316
Short name T48
Test name
Test status
Simulation time 4420729484 ps
CPU time 7.5 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:48:14 PM PST 23
Peak memory 216232 kb
Host smart-d9e729ff-df7d-4ace-8518-12fe9f4ac5df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715986316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2715986316
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.430520717
Short name T487
Test name
Test status
Simulation time 6111576264 ps
CPU time 4.7 seconds
Started Dec 20 12:47:47 PM PST 23
Finished Dec 20 12:49:19 PM PST 23
Peak memory 200768 kb
Host smart-e8ffd57d-be94-4d22-9320-6cf6efe090bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430520717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.430520717
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1588990818
Short name T278
Test name
Test status
Simulation time 230937155119 ps
CPU time 280.62 seconds
Started Dec 20 12:47:04 PM PST 23
Finished Dec 20 12:52:27 PM PST 23
Peak memory 209768 kb
Host smart-e0554e74-013c-437a-a89c-ab0266b46c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588990818 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1588990818
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3997714455
Short name T853
Test name
Test status
Simulation time 538554647 ps
CPU time 0.81 seconds
Started Dec 20 12:48:30 PM PST 23
Finished Dec 20 12:49:35 PM PST 23
Peak memory 200784 kb
Host smart-90ecc02e-40e9-4192-bf8a-68e21a95c617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997714455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3997714455
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3627252634
Short name T766
Test name
Test status
Simulation time 335227883623 ps
CPU time 173.92 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:52:39 PM PST 23
Peak memory 201036 kb
Host smart-2eb2e213-1d4e-4ad9-9a21-1ffa266b5d50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627252634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3627252634
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2179582579
Short name T524
Test name
Test status
Simulation time 165125597673 ps
CPU time 390.23 seconds
Started Dec 20 12:48:21 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 201112 kb
Host smart-06870a34-1d5b-4f1e-894b-d46ad4f7dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179582579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2179582579
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2004938876
Short name T244
Test name
Test status
Simulation time 162199078260 ps
CPU time 377.51 seconds
Started Dec 20 12:48:20 PM PST 23
Finished Dec 20 12:55:46 PM PST 23
Peak memory 200988 kb
Host smart-477f6f03-6ee8-4f23-b871-3805adf9dd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004938876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2004938876
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2190821656
Short name T517
Test name
Test status
Simulation time 494109926083 ps
CPU time 383.49 seconds
Started Dec 20 12:48:21 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 200944 kb
Host smart-797056e1-a1d8-44ff-992d-1be4209e1ebe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190821656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2190821656
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1362692745
Short name T122
Test name
Test status
Simulation time 495009026850 ps
CPU time 370.71 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:55:58 PM PST 23
Peak memory 200928 kb
Host smart-397b520e-6444-43cb-ab55-8818fb076bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362692745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1362692745
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1401137463
Short name T444
Test name
Test status
Simulation time 164081382415 ps
CPU time 195.28 seconds
Started Dec 20 12:48:15 PM PST 23
Finished Dec 20 12:52:54 PM PST 23
Peak memory 200904 kb
Host smart-2753903d-8573-4ae8-8a11-a07f8515b804
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401137463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1401137463
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1966910362
Short name T729
Test name
Test status
Simulation time 169422755467 ps
CPU time 405.18 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 12:56:32 PM PST 23
Peak memory 201012 kb
Host smart-30c6d195-566f-4c8f-ad14-50ea1fdfc848
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966910362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1966910362
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1194989318
Short name T472
Test name
Test status
Simulation time 165525226874 ps
CPU time 384.94 seconds
Started Dec 20 12:48:19 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 200952 kb
Host smart-6bea7455-ff24-4ee2-8a35-dae12fb38fa8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194989318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1194989318
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3180055172
Short name T201
Test name
Test status
Simulation time 113162756951 ps
CPU time 384.47 seconds
Started Dec 20 12:48:20 PM PST 23
Finished Dec 20 12:56:18 PM PST 23
Peak memory 201496 kb
Host smart-81b36352-e78e-4fcf-86fe-bfb84a1fdacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180055172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3180055172
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2443648143
Short name T685
Test name
Test status
Simulation time 36913797509 ps
CPU time 39.55 seconds
Started Dec 20 12:48:20 PM PST 23
Finished Dec 20 12:50:08 PM PST 23
Peak memory 200756 kb
Host smart-61cdc6bb-ec62-434f-8d94-ee77c5e6d095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443648143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2443648143
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3966450985
Short name T403
Test name
Test status
Simulation time 3801402941 ps
CPU time 5.05 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:49:39 PM PST 23
Peak memory 200800 kb
Host smart-46cfb2cc-3dfa-4a18-a0e7-59391bd6b98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966450985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3966450985
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3128638143
Short name T701
Test name
Test status
Simulation time 5671611152 ps
CPU time 13.38 seconds
Started Dec 20 12:48:19 PM PST 23
Finished Dec 20 12:50:00 PM PST 23
Peak memory 200704 kb
Host smart-05434de4-508b-4d97-86aa-3e3663d5bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128638143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3128638143
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.624052999
Short name T828
Test name
Test status
Simulation time 202036783477 ps
CPU time 243.66 seconds
Started Dec 20 12:48:55 PM PST 23
Finished Dec 20 12:54:12 PM PST 23
Peak memory 200996 kb
Host smart-314dd923-8e5b-4605-b274-ae87aa7ec82f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624052999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
624052999
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1042374932
Short name T588
Test name
Test status
Simulation time 268912115233 ps
CPU time 401.79 seconds
Started Dec 20 12:48:19 PM PST 23
Finished Dec 20 12:56:29 PM PST 23
Peak memory 209696 kb
Host smart-f5e19bfc-6955-4a4e-a9f6-b40c20cc32cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042374932 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1042374932
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3696235280
Short name T52
Test name
Test status
Simulation time 549620072 ps
CPU time 0.89 seconds
Started Dec 20 12:48:25 PM PST 23
Finished Dec 20 12:49:40 PM PST 23
Peak memory 200704 kb
Host smart-b0ddadbf-b611-4f91-ae10-cf9576d42679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696235280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3696235280
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.4080574057
Short name T302
Test name
Test status
Simulation time 495919555086 ps
CPU time 1180.5 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 01:09:20 PM PST 23
Peak memory 200968 kb
Host smart-79a43625-1306-46d5-92c2-425267896c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080574057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.4080574057
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3551364720
Short name T704
Test name
Test status
Simulation time 496410042499 ps
CPU time 263.26 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:54:08 PM PST 23
Peak memory 201000 kb
Host smart-d0bc9635-2b55-428a-8af4-368610d28128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551364720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3551364720
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2569905246
Short name T107
Test name
Test status
Simulation time 484358101829 ps
CPU time 130 seconds
Started Dec 20 12:48:28 PM PST 23
Finished Dec 20 12:51:57 PM PST 23
Peak memory 201032 kb
Host smart-14ec3847-b0ae-4865-a0c3-c4f7ea7dde8f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569905246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2569905246
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.425253909
Short name T424
Test name
Test status
Simulation time 166642122589 ps
CPU time 93.27 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:51:20 PM PST 23
Peak memory 200928 kb
Host smart-816d3549-221d-4f6a-9581-c02e52bd2517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425253909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.425253909
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.635477907
Short name T449
Test name
Test status
Simulation time 500878556691 ps
CPU time 619.91 seconds
Started Dec 20 12:48:26 PM PST 23
Finished Dec 20 12:59:52 PM PST 23
Peak memory 201020 kb
Host smart-4cd3b102-5fb6-4b14-b747-788edbde8719
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=635477907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.635477907
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3779284787
Short name T676
Test name
Test status
Simulation time 338821513188 ps
CPU time 806.28 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 01:03:24 PM PST 23
Peak memory 200944 kb
Host smart-9f1462cb-8e00-462b-aa41-79cc356dfb2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779284787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3779284787
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2105169605
Short name T809
Test name
Test status
Simulation time 498721709853 ps
CPU time 1168.15 seconds
Started Dec 20 12:48:54 PM PST 23
Finished Dec 20 01:09:25 PM PST 23
Peak memory 200940 kb
Host smart-8d2aad01-c648-4c96-97d1-74995a9b172e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105169605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2105169605
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2613903837
Short name T347
Test name
Test status
Simulation time 114800437806 ps
CPU time 334.76 seconds
Started Dec 20 12:48:54 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 201200 kb
Host smart-e7b85665-bf96-49da-a5f8-10d3d8377e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613903837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2613903837
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1195661669
Short name T563
Test name
Test status
Simulation time 32810075434 ps
CPU time 70.29 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:50:47 PM PST 23
Peak memory 200756 kb
Host smart-34c86ad3-f2d1-4c8b-8088-e1348b117107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195661669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1195661669
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3971640305
Short name T450
Test name
Test status
Simulation time 5169203617 ps
CPU time 4.65 seconds
Started Dec 20 12:48:27 PM PST 23
Finished Dec 20 12:49:37 PM PST 23
Peak memory 200764 kb
Host smart-2bba33af-d4cf-44b9-bd7c-e58c881363ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971640305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3971640305
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.792113009
Short name T606
Test name
Test status
Simulation time 5537479949 ps
CPU time 7.66 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 12:50:02 PM PST 23
Peak memory 200796 kb
Host smart-d68f8dc5-a9d0-4919-8fb4-900afd5dec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792113009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.792113009
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.762818230
Short name T284
Test name
Test status
Simulation time 375218288656 ps
CPU time 783.48 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 01:02:52 PM PST 23
Peak memory 200996 kb
Host smart-7ac4da63-2147-4624-ae1f-14f5fc4c35aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762818230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
762818230
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.608112869
Short name T222
Test name
Test status
Simulation time 226880517744 ps
CPU time 92.09 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:51:07 PM PST 23
Peak memory 209196 kb
Host smart-242b677f-355f-40a6-a677-f2a2f0e9e08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608112869 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.608112869
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3257326545
Short name T490
Test name
Test status
Simulation time 442261518 ps
CPU time 1.71 seconds
Started Dec 20 12:48:24 PM PST 23
Finished Dec 20 12:49:37 PM PST 23
Peak memory 200732 kb
Host smart-1ed5441f-c2eb-468d-8bdf-79044832299b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257326545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3257326545
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1368445470
Short name T223
Test name
Test status
Simulation time 331845562351 ps
CPU time 211.31 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:53:27 PM PST 23
Peak memory 200988 kb
Host smart-10aa1f87-d382-49fd-b34e-4839314010eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368445470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1368445470
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3995212700
Short name T669
Test name
Test status
Simulation time 332205135417 ps
CPU time 195.88 seconds
Started Dec 20 12:48:26 PM PST 23
Finished Dec 20 12:52:48 PM PST 23
Peak memory 201020 kb
Host smart-963dff30-7e06-4392-b29d-83803e83d9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995212700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3995212700
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1885925189
Short name T272
Test name
Test status
Simulation time 330303691146 ps
CPU time 158.27 seconds
Started Dec 20 12:48:24 PM PST 23
Finished Dec 20 12:52:13 PM PST 23
Peak memory 200948 kb
Host smart-f8661082-7a0b-4f09-95cd-89a9f71458d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885925189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1885925189
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1527961868
Short name T165
Test name
Test status
Simulation time 331151745202 ps
CPU time 436.13 seconds
Started Dec 20 12:48:24 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 200956 kb
Host smart-b384fe34-716f-4aa1-8019-760e63895018
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527961868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1527961868
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.4060167633
Short name T476
Test name
Test status
Simulation time 324425069930 ps
CPU time 198.53 seconds
Started Dec 20 12:48:26 PM PST 23
Finished Dec 20 12:52:51 PM PST 23
Peak memory 200988 kb
Host smart-b8f860f0-f012-4a66-8ed8-c6995d100ca4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060167633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.4060167633
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.774409066
Short name T810
Test name
Test status
Simulation time 169994304294 ps
CPU time 208.36 seconds
Started Dec 20 12:48:48 PM PST 23
Finished Dec 20 12:53:19 PM PST 23
Peak memory 200884 kb
Host smart-c74b8bf1-6ee5-4b89-8afb-0d63c3d0b6b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774409066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.774409066
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1560190016
Short name T485
Test name
Test status
Simulation time 327194230714 ps
CPU time 598.66 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:59:36 PM PST 23
Peak memory 200972 kb
Host smart-a0faec21-002b-48ca-a27b-002bf2968496
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560190016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1560190016
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1504963000
Short name T648
Test name
Test status
Simulation time 103312144941 ps
CPU time 342.75 seconds
Started Dec 20 12:48:26 PM PST 23
Finished Dec 20 12:55:18 PM PST 23
Peak memory 201416 kb
Host smart-dffef241-1d79-4d93-a82f-d946d9988138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504963000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1504963000
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3556038541
Short name T621
Test name
Test status
Simulation time 33377213299 ps
CPU time 22.75 seconds
Started Dec 20 12:48:22 PM PST 23
Finished Dec 20 12:50:12 PM PST 23
Peak memory 200680 kb
Host smart-e57bb85a-d601-496d-bcbe-4abcdab619a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556038541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3556038541
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.4244109151
Short name T504
Test name
Test status
Simulation time 4853564765 ps
CPU time 13.12 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:50:08 PM PST 23
Peak memory 200756 kb
Host smart-fd55ebab-4556-4f2c-9951-786d29ddbaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244109151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4244109151
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2458734656
Short name T570
Test name
Test status
Simulation time 5971895245 ps
CPU time 6.87 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:49:43 PM PST 23
Peak memory 200580 kb
Host smart-caad9d35-edb4-4c98-b969-e12a3bf939e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458734656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2458734656
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1038272300
Short name T349
Test name
Test status
Simulation time 91620769415 ps
CPU time 389.61 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:56:07 PM PST 23
Peak memory 201260 kb
Host smart-46f3eb41-f9c2-4e81-b3f1-7c5314e6a0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038272300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1038272300
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.117887299
Short name T672
Test name
Test status
Simulation time 81427278923 ps
CPU time 98.81 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:51:19 PM PST 23
Peak memory 209196 kb
Host smart-8e124299-2303-4eaf-8ced-c11e159c3091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117887299 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.117887299
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4167121750
Short name T610
Test name
Test status
Simulation time 322022247 ps
CPU time 1.33 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:49:35 PM PST 23
Peak memory 200720 kb
Host smart-b681b6cc-0452-4912-b904-f2acfe76ef37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167121750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4167121750
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.918360579
Short name T759
Test name
Test status
Simulation time 327107827102 ps
CPU time 206.07 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 201060 kb
Host smart-0d016a85-db5d-4ee1-8393-532409afc349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918360579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.918360579
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.938107444
Short name T674
Test name
Test status
Simulation time 481008986569 ps
CPU time 196.69 seconds
Started Dec 20 12:48:28 PM PST 23
Finished Dec 20 12:53:02 PM PST 23
Peak memory 201036 kb
Host smart-7fbdecfa-ced9-4726-a7bb-c53fc0799b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938107444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.938107444
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1189126153
Short name T851
Test name
Test status
Simulation time 329686630922 ps
CPU time 729.68 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 01:02:06 PM PST 23
Peak memory 200984 kb
Host smart-2668cc2d-f779-467f-bafd-e0d7c25452e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189126153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1189126153
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.348219667
Short name T569
Test name
Test status
Simulation time 324209342263 ps
CPU time 399.91 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 200792 kb
Host smart-9e08ff79-18a5-4495-9a60-f38b120ecf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348219667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.348219667
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1667144058
Short name T482
Test name
Test status
Simulation time 166612272605 ps
CPU time 52.48 seconds
Started Dec 20 12:48:42 PM PST 23
Finished Dec 20 12:50:56 PM PST 23
Peak memory 200760 kb
Host smart-fecb3214-3237-49b5-b7c3-7f9218e13f4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667144058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1667144058
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.211109027
Short name T179
Test name
Test status
Simulation time 165346471412 ps
CPU time 100.39 seconds
Started Dec 20 12:48:22 PM PST 23
Finished Dec 20 12:51:30 PM PST 23
Peak memory 200824 kb
Host smart-9d1b36b8-4e94-49e9-9331-7cd7c4523fda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211109027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.211109027
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2723626464
Short name T119
Test name
Test status
Simulation time 166512170564 ps
CPU time 208.41 seconds
Started Dec 20 12:48:23 PM PST 23
Finished Dec 20 12:53:09 PM PST 23
Peak memory 200984 kb
Host smart-fc50fb21-c3fc-4455-9277-a288c308f516
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723626464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2723626464
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2973871190
Short name T94
Test name
Test status
Simulation time 125928784702 ps
CPU time 668.07 seconds
Started Dec 20 12:48:27 PM PST 23
Finished Dec 20 01:01:02 PM PST 23
Peak memory 201364 kb
Host smart-b29b5eec-9d2e-4fd3-ac6b-80bfae92c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973871190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2973871190
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4002674820
Short name T817
Test name
Test status
Simulation time 40820950406 ps
CPU time 94.23 seconds
Started Dec 20 12:48:25 PM PST 23
Finished Dec 20 12:51:13 PM PST 23
Peak memory 200740 kb
Host smart-7241531f-a138-42bd-8268-b4e5c73b7f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002674820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4002674820
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2226089002
Short name T788
Test name
Test status
Simulation time 4553768315 ps
CPU time 6.37 seconds
Started Dec 20 12:48:27 PM PST 23
Finished Dec 20 12:49:51 PM PST 23
Peak memory 200580 kb
Host smart-d0d997a7-c439-4d80-9a78-6cb2a7d7ebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226089002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2226089002
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1058514214
Short name T782
Test name
Test status
Simulation time 5688077907 ps
CPU time 3.8 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:50:01 PM PST 23
Peak memory 200852 kb
Host smart-3f27c948-d974-4142-b8ef-c1373e7bc25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058514214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1058514214
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2714133114
Short name T722
Test name
Test status
Simulation time 334600802546 ps
CPU time 674.27 seconds
Started Dec 20 12:48:25 PM PST 23
Finished Dec 20 01:00:54 PM PST 23
Peak memory 200900 kb
Host smart-d4e3bb40-1a49-4593-9445-793236474773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714133114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2714133114
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2426239577
Short name T183
Test name
Test status
Simulation time 507833474 ps
CPU time 1.67 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:49:49 PM PST 23
Peak memory 200720 kb
Host smart-4abe963e-bf26-49e1-92ae-d48a6720d145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426239577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2426239577
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1902707460
Short name T180
Test name
Test status
Simulation time 164636916032 ps
CPU time 158.74 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:52:17 PM PST 23
Peak memory 200932 kb
Host smart-66175f6e-9d85-4dc7-a471-7c693258b144
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902707460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1902707460
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3266955136
Short name T320
Test name
Test status
Simulation time 164899161587 ps
CPU time 93.4 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:51:08 PM PST 23
Peak memory 200980 kb
Host smart-82460ef4-d2e6-44ff-97d5-5452ac8a0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266955136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3266955136
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3578653212
Short name T586
Test name
Test status
Simulation time 166543254305 ps
CPU time 108.76 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:51:52 PM PST 23
Peak memory 200800 kb
Host smart-d7e642c6-3592-443d-ad89-9121e047c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578653212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3578653212
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2210915160
Short name T478
Test name
Test status
Simulation time 493167948809 ps
CPU time 1118.4 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 01:08:36 PM PST 23
Peak memory 200788 kb
Host smart-90865009-a8b9-4cef-bc98-9e054c78558d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210915160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2210915160
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1866805331
Short name T655
Test name
Test status
Simulation time 157535029387 ps
CPU time 354.42 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:55:42 PM PST 23
Peak memory 200944 kb
Host smart-ec97164d-79e8-4a49-923d-2f4aed94790d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866805331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1866805331
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1391559050
Short name T280
Test name
Test status
Simulation time 333588344061 ps
CPU time 784.19 seconds
Started Dec 20 12:48:35 PM PST 23
Finished Dec 20 01:03:00 PM PST 23
Peak memory 200900 kb
Host smart-db7e8b54-4c29-44f1-b735-fcf83518f4f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391559050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1391559050
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3552905399
Short name T505
Test name
Test status
Simulation time 332327990861 ps
CPU time 181.02 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:52:56 PM PST 23
Peak memory 200972 kb
Host smart-26c84944-885b-4a33-a346-f8d9ee6728b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552905399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3552905399
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2836595839
Short name T488
Test name
Test status
Simulation time 90459185579 ps
CPU time 280.98 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:54:20 PM PST 23
Peak memory 201352 kb
Host smart-467f54ac-bece-463e-b0cc-ebe87f993b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836595839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2836595839
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3778353241
Short name T551
Test name
Test status
Simulation time 46150484214 ps
CPU time 28.17 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:50:02 PM PST 23
Peak memory 200680 kb
Host smart-b87048fb-641c-4aa2-bca5-63ab3b681747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778353241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3778353241
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3311426995
Short name T520
Test name
Test status
Simulation time 3657016266 ps
CPU time 2.35 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 12:50:08 PM PST 23
Peak memory 200648 kb
Host smart-fddd7022-866a-4af2-9fd8-25484cc416fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311426995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3311426995
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4172585588
Short name T445
Test name
Test status
Simulation time 5946082800 ps
CPU time 4.23 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 200612 kb
Host smart-ee5e3682-20d7-4b15-bee2-ad856aa0ed81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172585588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4172585588
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1080846580
Short name T668
Test name
Test status
Simulation time 184308111993 ps
CPU time 66.16 seconds
Started Dec 20 12:48:44 PM PST 23
Finished Dec 20 12:51:02 PM PST 23
Peak memory 209220 kb
Host smart-dd951b25-76d5-4f97-a0ba-43f4beb60e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080846580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1080846580
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2267621735
Short name T566
Test name
Test status
Simulation time 480755772 ps
CPU time 1.54 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:50:03 PM PST 23
Peak memory 200628 kb
Host smart-5fd7e4c4-d1d5-458e-91d6-50d25af43f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267621735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2267621735
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3232236824
Short name T582
Test name
Test status
Simulation time 158585892718 ps
CPU time 106.04 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:51:38 PM PST 23
Peak memory 200880 kb
Host smart-1e79d233-29b5-4a2e-a801-e3b81b12a027
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232236824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3232236824
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.934063006
Short name T227
Test name
Test status
Simulation time 493194630542 ps
CPU time 524.16 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:58:50 PM PST 23
Peak memory 200832 kb
Host smart-9f65131a-30ad-4396-aada-c4e654012c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934063006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.934063006
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4097724364
Short name T601
Test name
Test status
Simulation time 328291594281 ps
CPU time 110.2 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:51:24 PM PST 23
Peak memory 200984 kb
Host smart-adc4519e-19cf-4ae3-a44d-85a71e0a7669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097724364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4097724364
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3062839324
Short name T539
Test name
Test status
Simulation time 496271713461 ps
CPU time 1047.69 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 01:07:16 PM PST 23
Peak memory 200908 kb
Host smart-44429e58-70bc-43ed-b343-2ff44966b14c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062839324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3062839324
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.795790927
Short name T254
Test name
Test status
Simulation time 492435819127 ps
CPU time 1102.44 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 01:08:08 PM PST 23
Peak memory 201004 kb
Host smart-0772c5e0-ce5c-4cb5-9e0f-e5c04c5e1335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795790927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.795790927
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2519508329
Short name T646
Test name
Test status
Simulation time 161292155967 ps
CPU time 188.81 seconds
Started Dec 20 12:48:35 PM PST 23
Finished Dec 20 12:53:02 PM PST 23
Peak memory 200880 kb
Host smart-cbac83e9-6c11-4421-a3be-8f9816f18593
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519508329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2519508329
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3708983330
Short name T123
Test name
Test status
Simulation time 167193665666 ps
CPU time 181.58 seconds
Started Dec 20 12:48:48 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 200936 kb
Host smart-c09bc2db-c12f-4cc4-9eb8-b7385e3f72b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708983330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3708983330
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.509415242
Short name T693
Test name
Test status
Simulation time 327044348897 ps
CPU time 312 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:54:54 PM PST 23
Peak memory 200988 kb
Host smart-11a50d11-3fb8-4b66-b3ae-98089eeab61a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509415242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.509415242
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.903412561
Short name T203
Test name
Test status
Simulation time 71210732954 ps
CPU time 241.13 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:53:50 PM PST 23
Peak memory 201516 kb
Host smart-cd970fd7-213b-449d-bb64-05a135e394ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903412561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.903412561
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1283674582
Short name T547
Test name
Test status
Simulation time 36121506846 ps
CPU time 21.03 seconds
Started Dec 20 12:49:01 PM PST 23
Finished Dec 20 12:50:23 PM PST 23
Peak memory 200736 kb
Host smart-7a7c7401-fb01-4c85-8358-8893f01d545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283674582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1283674582
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.307543137
Short name T631
Test name
Test status
Simulation time 3111192714 ps
CPU time 1.17 seconds
Started Dec 20 12:48:30 PM PST 23
Finished Dec 20 12:49:50 PM PST 23
Peak memory 200848 kb
Host smart-574d15b9-4cd9-4099-8044-c4a0759cca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307543137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.307543137
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3683423740
Short name T815
Test name
Test status
Simulation time 5578295990 ps
CPU time 3.58 seconds
Started Dec 20 12:48:48 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 200748 kb
Host smart-a50e7dc6-2ae3-4d1a-9a7c-d181f3040464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683423740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3683423740
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.263437247
Short name T469
Test name
Test status
Simulation time 27405544035 ps
CPU time 65.32 seconds
Started Dec 20 12:48:35 PM PST 23
Finished Dec 20 12:50:57 PM PST 23
Peak memory 201172 kb
Host smart-20c5d845-2a71-43fc-a780-833cadf7dc25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263437247 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.263437247
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2268311134
Short name T596
Test name
Test status
Simulation time 506627372 ps
CPU time 1.32 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 12:49:49 PM PST 23
Peak memory 200708 kb
Host smart-6562bec4-e8fd-4f08-9315-91777bdcb839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268311134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2268311134
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3462131802
Short name T751
Test name
Test status
Simulation time 510437187798 ps
CPU time 385.15 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 200944 kb
Host smart-a37234ca-f535-4053-a9cf-166c047e6d24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462131802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3462131802
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1616220665
Short name T730
Test name
Test status
Simulation time 488674585448 ps
CPU time 553.24 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:59:16 PM PST 23
Peak memory 200968 kb
Host smart-be8a2b8f-1c78-4617-8605-6bc3b9af450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616220665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1616220665
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2588042891
Short name T823
Test name
Test status
Simulation time 324617014259 ps
CPU time 206.34 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 201036 kb
Host smart-d163c370-bfcd-4c87-b7f5-cc6099dfd45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588042891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2588042891
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3409760438
Short name T632
Test name
Test status
Simulation time 494235626071 ps
CPU time 1193.59 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 01:09:40 PM PST 23
Peak memory 200984 kb
Host smart-5e6fcf0f-6bd5-4fec-98db-b9fe5196840e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409760438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3409760438
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3629255160
Short name T717
Test name
Test status
Simulation time 169983168526 ps
CPU time 249.4 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 12:53:56 PM PST 23
Peak memory 201068 kb
Host smart-c52c1d50-050a-44bf-a8c4-59a1cd191b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629255160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3629255160
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3415467460
Short name T716
Test name
Test status
Simulation time 163067304364 ps
CPU time 369.21 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 200824 kb
Host smart-69715a4d-e68c-4ef1-b867-6b90b65173c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415467460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3415467460
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1130793382
Short name T230
Test name
Test status
Simulation time 492508008900 ps
CPU time 572.11 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:59:21 PM PST 23
Peak memory 200936 kb
Host smart-a4fbe4e9-dcfa-472f-9b2d-d8f509311dc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130793382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1130793382
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3114225403
Short name T560
Test name
Test status
Simulation time 492768350368 ps
CPU time 275.27 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:54:26 PM PST 23
Peak memory 200948 kb
Host smart-db8a7d31-4231-48d4-881a-0bcf8779c392
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114225403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3114225403
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3896023283
Short name T778
Test name
Test status
Simulation time 107753736757 ps
CPU time 449.19 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 201348 kb
Host smart-256765d4-e182-4e9b-aa42-62aa8fbf6b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896023283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3896023283
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1028289675
Short name T456
Test name
Test status
Simulation time 27358821130 ps
CPU time 29.11 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:50:38 PM PST 23
Peak memory 200800 kb
Host smart-0860f606-3bac-4757-bfad-e2a87a5068ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028289675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1028289675
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2080974220
Short name T510
Test name
Test status
Simulation time 3841559517 ps
CPU time 9.44 seconds
Started Dec 20 12:48:30 PM PST 23
Finished Dec 20 12:49:44 PM PST 23
Peak memory 200796 kb
Host smart-7c7fef19-8306-4843-999b-615e5cf6a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080974220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2080974220
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1799138520
Short name T153
Test name
Test status
Simulation time 5874006815 ps
CPU time 7.75 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:49:53 PM PST 23
Peak memory 200792 kb
Host smart-2007803f-7a5c-4f9b-b40f-bd914a22364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799138520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1799138520
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.292369526
Short name T574
Test name
Test status
Simulation time 37254725101 ps
CPU time 79.92 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:51:09 PM PST 23
Peak memory 200792 kb
Host smart-9d294735-cb2f-4d6f-8c68-1156261d1219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292369526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
292369526
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2100441889
Short name T279
Test name
Test status
Simulation time 285112479267 ps
CPU time 303.15 seconds
Started Dec 20 12:48:53 PM PST 23
Finished Dec 20 12:55:00 PM PST 23
Peak memory 209692 kb
Host smart-419d92a5-2f57-4d23-a83c-11388b8b45d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100441889 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2100441889
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2911250917
Short name T638
Test name
Test status
Simulation time 509058912 ps
CPU time 1.78 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:49:38 PM PST 23
Peak memory 200644 kb
Host smart-e716f365-d468-4de4-8a1b-328badcbb6c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911250917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2911250917
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1287709109
Short name T843
Test name
Test status
Simulation time 162015568214 ps
CPU time 347.64 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 200832 kb
Host smart-f39ccd4f-0e78-4d22-9628-05738ea77183
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287709109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1287709109
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.38332623
Short name T805
Test name
Test status
Simulation time 334747704155 ps
CPU time 206.64 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 12:53:16 PM PST 23
Peak memory 200984 kb
Host smart-f042e6f1-38a7-4f11-953f-4a85261124dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38332623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.38332623
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1241011463
Short name T97
Test name
Test status
Simulation time 323605458809 ps
CPU time 198.3 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 201004 kb
Host smart-8fed7949-35d4-4e93-83e9-bfa903adaab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241011463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1241011463
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.573327623
Short name T768
Test name
Test status
Simulation time 327059563857 ps
CPU time 196.83 seconds
Started Dec 20 12:49:21 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 200936 kb
Host smart-c5ca411d-58bb-48bf-bdbf-ae16863f4e1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=573327623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.573327623
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.942234862
Short name T127
Test name
Test status
Simulation time 323345113198 ps
CPU time 753.44 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 01:02:48 PM PST 23
Peak memory 200884 kb
Host smart-d641b34f-cb19-4f81-ad4b-5fcf918ac85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942234862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.942234862
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2364826628
Short name T741
Test name
Test status
Simulation time 166376864657 ps
CPU time 44.81 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 12:50:22 PM PST 23
Peak memory 200908 kb
Host smart-e1eff7a3-3e52-4343-b4bb-5e87215516db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364826628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2364826628
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3467200228
Short name T231
Test name
Test status
Simulation time 324327405302 ps
CPU time 371.51 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:56:34 PM PST 23
Peak memory 200800 kb
Host smart-be76275c-1eab-405c-b25e-5b44488fedd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467200228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3467200228
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.306641767
Short name T740
Test name
Test status
Simulation time 330384453588 ps
CPU time 763.87 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 01:02:39 PM PST 23
Peak memory 200804 kb
Host smart-c243e999-c0b7-4832-9990-1dd224917f37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306641767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.306641767
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3152367978
Short name T37
Test name
Test status
Simulation time 92376693578 ps
CPU time 469.56 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 12:57:40 PM PST 23
Peak memory 201456 kb
Host smart-ab290ee5-0480-4beb-8654-e5116ddc3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152367978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3152367978
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2871581103
Short name T553
Test name
Test status
Simulation time 40830124562 ps
CPU time 24.71 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:50:06 PM PST 23
Peak memory 200668 kb
Host smart-c48f972e-2580-42ac-97a1-edee37947b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871581103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2871581103
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3047697160
Short name T526
Test name
Test status
Simulation time 5313345294 ps
CPU time 3.75 seconds
Started Dec 20 12:48:47 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 200848 kb
Host smart-38f8cbd7-57f2-4f0c-b9ed-03587073ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047697160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3047697160
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.4010109748
Short name T164
Test name
Test status
Simulation time 5922847964 ps
CPU time 13.42 seconds
Started Dec 20 12:48:43 PM PST 23
Finished Dec 20 12:50:02 PM PST 23
Peak memory 200800 kb
Host smart-20f467e4-27bf-4354-81d5-89141cfd21f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010109748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.4010109748
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2545061839
Short name T313
Test name
Test status
Simulation time 262366039520 ps
CPU time 395.21 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 210304 kb
Host smart-772ec42b-6267-43db-a4f5-e4326d36748c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545061839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2545061839
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.660558344
Short name T747
Test name
Test status
Simulation time 305367434 ps
CPU time 0.91 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:49:48 PM PST 23
Peak memory 200696 kb
Host smart-b3fd0324-2755-49a0-8149-bd890e11ed30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660558344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.660558344
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1203016131
Short name T221
Test name
Test status
Simulation time 491531532191 ps
CPU time 1189.33 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 01:10:02 PM PST 23
Peak memory 200932 kb
Host smart-bc1588b4-10a2-4966-ac87-129951c464b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203016131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1203016131
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2664327032
Short name T275
Test name
Test status
Simulation time 337706362061 ps
CPU time 813.37 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 01:03:10 PM PST 23
Peak memory 201096 kb
Host smart-2b647226-1f1a-4eae-8073-5789dc9ee05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664327032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2664327032
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3572669889
Short name T496
Test name
Test status
Simulation time 493757148841 ps
CPU time 91.43 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 12:51:27 PM PST 23
Peak memory 200940 kb
Host smart-f6ddcb64-8fca-40a1-a802-63956f0ed1e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572669889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3572669889
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.569790923
Short name T658
Test name
Test status
Simulation time 325032329007 ps
CPU time 213.36 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:53:43 PM PST 23
Peak memory 200920 kb
Host smart-b218a2db-fb4d-4039-9557-4ad42b0382f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569790923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.569790923
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2723699089
Short name T727
Test name
Test status
Simulation time 168652436970 ps
CPU time 98.14 seconds
Started Dec 20 12:49:16 PM PST 23
Finished Dec 20 12:51:55 PM PST 23
Peak memory 200816 kb
Host smart-206b5baf-c1ac-413f-9021-88fe8d211fcd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723699089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2723699089
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2227734101
Short name T803
Test name
Test status
Simulation time 633365804325 ps
CPU time 388.43 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 12:56:15 PM PST 23
Peak memory 200916 kb
Host smart-879b63c8-b68f-45a6-b2e2-6dda1ee377ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227734101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2227734101
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2876471963
Short name T791
Test name
Test status
Simulation time 328413009495 ps
CPU time 780.86 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 01:02:53 PM PST 23
Peak memory 201020 kb
Host smart-00b6d221-749c-4e91-b5f3-523b2364e2c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876471963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2876471963
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2686344014
Short name T784
Test name
Test status
Simulation time 100708470600 ps
CPU time 554.89 seconds
Started Dec 20 12:48:51 PM PST 23
Finished Dec 20 12:59:10 PM PST 23
Peak memory 201440 kb
Host smart-ad3eebd7-fbca-4a0c-ac82-41ef765e05e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686344014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2686344014
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3830760786
Short name T779
Test name
Test status
Simulation time 27662380622 ps
CPU time 62.06 seconds
Started Dec 20 12:48:48 PM PST 23
Finished Dec 20 12:50:55 PM PST 23
Peak memory 200792 kb
Host smart-d7852f9d-fa31-4142-aef4-51d3033834f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830760786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3830760786
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3943638425
Short name T536
Test name
Test status
Simulation time 5424953448 ps
CPU time 13.15 seconds
Started Dec 20 12:48:55 PM PST 23
Finished Dec 20 12:50:10 PM PST 23
Peak memory 200864 kb
Host smart-26533872-aa99-451f-acc5-7e234589e87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943638425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3943638425
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.432666245
Short name T459
Test name
Test status
Simulation time 5696537593 ps
CPU time 13.77 seconds
Started Dec 20 12:48:34 PM PST 23
Finished Dec 20 12:50:03 PM PST 23
Peak memory 200708 kb
Host smart-f3018e09-3a5c-4fb5-90c6-0a78c6142af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432666245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.432666245
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.289935247
Short name T309
Test name
Test status
Simulation time 29746520112 ps
CPU time 23.21 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 12:50:28 PM PST 23
Peak memory 209496 kb
Host smart-ae798119-f55a-4ec1-97f1-6ca0466112d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289935247 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.289935247
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3773693272
Short name T750
Test name
Test status
Simulation time 536635006 ps
CPU time 1.12 seconds
Started Dec 20 12:48:44 PM PST 23
Finished Dec 20 12:49:49 PM PST 23
Peak memory 200524 kb
Host smart-01b1e7e1-1384-4f22-ad07-e6770efc1ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773693272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3773693272
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.921550918
Short name T262
Test name
Test status
Simulation time 165296156218 ps
CPU time 362.77 seconds
Started Dec 20 12:49:13 PM PST 23
Finished Dec 20 12:56:17 PM PST 23
Peak memory 200956 kb
Host smart-f5329fd3-bc12-4dc8-8a1d-6e8d28cde191
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921550918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.921550918
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3969141329
Short name T528
Test name
Test status
Simulation time 169818422521 ps
CPU time 386.31 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 200852 kb
Host smart-e81e20fe-448b-4743-a6fe-f84fc134e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969141329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3969141329
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2004585926
Short name T419
Test name
Test status
Simulation time 325485893347 ps
CPU time 731.97 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 01:01:59 PM PST 23
Peak memory 200692 kb
Host smart-e4ea9f28-967c-4e7a-92d3-babf1754eacb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004585926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2004585926
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1929324422
Short name T609
Test name
Test status
Simulation time 321320796215 ps
CPU time 195.38 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:53:01 PM PST 23
Peak memory 201036 kb
Host smart-c827446e-e431-4db8-ac18-1fbad6493116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929324422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1929324422
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1646533317
Short name T848
Test name
Test status
Simulation time 165527112506 ps
CPU time 21.95 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 200860 kb
Host smart-65551cfa-07ba-4feb-9b45-c524fa8329ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646533317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1646533317
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.920674332
Short name T636
Test name
Test status
Simulation time 164610179274 ps
CPU time 210.54 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:53:18 PM PST 23
Peak memory 200892 kb
Host smart-614e6d0f-e501-4f4d-a363-5f8bcb0efe52
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920674332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.920674332
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2107691838
Short name T351
Test name
Test status
Simulation time 123711557370 ps
CPU time 488.66 seconds
Started Dec 20 12:48:45 PM PST 23
Finished Dec 20 12:57:57 PM PST 23
Peak memory 201268 kb
Host smart-8fb8b675-72eb-4ac7-aa0a-43287945eb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107691838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2107691838
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2773655237
Short name T600
Test name
Test status
Simulation time 24155513538 ps
CPU time 29.29 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:50:15 PM PST 23
Peak memory 200908 kb
Host smart-2e660b70-5c5d-4d60-ac01-b50d9ca1f123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773655237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2773655237
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2165418230
Short name T686
Test name
Test status
Simulation time 3947379498 ps
CPU time 3.93 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:49:46 PM PST 23
Peak memory 200908 kb
Host smart-ca9e20cd-9d7e-40de-ae92-1814b9354336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165418230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2165418230
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.371477790
Short name T855
Test name
Test status
Simulation time 5962436290 ps
CPU time 13.89 seconds
Started Dec 20 12:48:38 PM PST 23
Finished Dec 20 12:50:02 PM PST 23
Peak memory 200780 kb
Host smart-995ad57f-945c-40a4-ae1d-c62264082a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371477790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.371477790
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.381013451
Short name T613
Test name
Test status
Simulation time 371467660 ps
CPU time 1.04 seconds
Started Dec 20 12:47:24 PM PST 23
Finished Dec 20 12:48:31 PM PST 23
Peak memory 200728 kb
Host smart-0cf045cb-3af2-4603-a759-3eceff85b8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381013451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.381013451
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2233322128
Short name T562
Test name
Test status
Simulation time 161938025644 ps
CPU time 100.08 seconds
Started Dec 20 12:47:19 PM PST 23
Finished Dec 20 12:49:53 PM PST 23
Peak memory 201032 kb
Host smart-72cbe6bd-b1d8-4b64-aa11-889f8e7e0479
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233322128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2233322128
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1837938793
Short name T241
Test name
Test status
Simulation time 519006449023 ps
CPU time 1190.09 seconds
Started Dec 20 12:47:01 PM PST 23
Finished Dec 20 01:07:32 PM PST 23
Peak memory 200792 kb
Host smart-b6762578-0035-4da4-a849-9973bc56085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837938793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1837938793
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4022451075
Short name T654
Test name
Test status
Simulation time 159935936347 ps
CPU time 301.77 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:53:00 PM PST 23
Peak memory 200972 kb
Host smart-b1219442-858b-402e-b583-4206a0110058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022451075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4022451075
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1741350012
Short name T428
Test name
Test status
Simulation time 166566804371 ps
CPU time 359.38 seconds
Started Dec 20 12:47:05 PM PST 23
Finished Dec 20 12:53:47 PM PST 23
Peak memory 200872 kb
Host smart-601c2793-804e-4ebb-912f-ffde78d868d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741350012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1741350012
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.540388345
Short name T294
Test name
Test status
Simulation time 486629686592 ps
CPU time 280.11 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 200772 kb
Host smart-d2c0b34b-8183-4555-a829-8ffe12ec9315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540388345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.540388345
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2562044904
Short name T529
Test name
Test status
Simulation time 335645468783 ps
CPU time 757.76 seconds
Started Dec 20 12:47:23 PM PST 23
Finished Dec 20 01:01:07 PM PST 23
Peak memory 200804 kb
Host smart-dd393466-4f64-4618-bce6-13c0162826ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562044904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2562044904
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1041675979
Short name T316
Test name
Test status
Simulation time 331672394460 ps
CPU time 666.85 seconds
Started Dec 20 12:47:31 PM PST 23
Finished Dec 20 12:59:55 PM PST 23
Peak memory 200824 kb
Host smart-ae3f3fc5-a8aa-4c99-b152-5cd1a1a9e39a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041675979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1041675979
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.701030843
Short name T458
Test name
Test status
Simulation time 332556810092 ps
CPU time 809.25 seconds
Started Dec 20 12:47:11 PM PST 23
Finished Dec 20 01:01:29 PM PST 23
Peak memory 200984 kb
Host smart-ac7db3a4-cb06-4ce8-96f2-4f7aefb242d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701030843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.701030843
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3624983557
Short name T446
Test name
Test status
Simulation time 29727383187 ps
CPU time 69.29 seconds
Started Dec 20 12:47:21 PM PST 23
Finished Dec 20 12:49:39 PM PST 23
Peak memory 200504 kb
Host smart-52733b0e-3d75-4a90-979b-76b848be504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624983557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3624983557
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2494328259
Short name T568
Test name
Test status
Simulation time 4796082016 ps
CPU time 1.36 seconds
Started Dec 20 12:47:12 PM PST 23
Finished Dec 20 12:48:04 PM PST 23
Peak memory 200532 kb
Host smart-505c85f6-afab-430e-bc14-10a04fe141c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494328259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2494328259
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3148023018
Short name T46
Test name
Test status
Simulation time 7522578447 ps
CPU time 9.96 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:48:09 PM PST 23
Peak memory 217196 kb
Host smart-e13687d9-a187-4f65-a4fb-d9339baf4708
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148023018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3148023018
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.990292480
Short name T467
Test name
Test status
Simulation time 6021423990 ps
CPU time 14.36 seconds
Started Dec 20 12:46:58 PM PST 23
Finished Dec 20 12:47:52 PM PST 23
Peak memory 200660 kb
Host smart-f3991cba-0f2d-4438-b993-ca0b8c362b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990292480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.990292480
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1913066499
Short name T200
Test name
Test status
Simulation time 406904971146 ps
CPU time 486.8 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:56:09 PM PST 23
Peak memory 209444 kb
Host smart-66beb9e1-3373-43ce-a2d8-a1a432f3a66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913066499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1913066499
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3661279152
Short name T285
Test name
Test status
Simulation time 242158975641 ps
CPU time 90.17 seconds
Started Dec 20 12:47:07 PM PST 23
Finished Dec 20 12:49:23 PM PST 23
Peak memory 217884 kb
Host smart-15d13b52-9465-4d78-8e6c-14c1c8a90c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661279152 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3661279152
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2325909908
Short name T42
Test name
Test status
Simulation time 435425062 ps
CPU time 1.38 seconds
Started Dec 20 12:48:44 PM PST 23
Finished Dec 20 12:49:58 PM PST 23
Peak memory 200800 kb
Host smart-b05b7b00-d7f1-46cd-b1f8-4e8e3cea1181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325909908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2325909908
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3760407826
Short name T341
Test name
Test status
Simulation time 168825004463 ps
CPU time 97.83 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:51:13 PM PST 23
Peak memory 201012 kb
Host smart-685dd017-fc27-4616-9c3d-3c5dc1b5d193
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760407826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3760407826
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2793807772
Short name T185
Test name
Test status
Simulation time 489883965721 ps
CPU time 305.67 seconds
Started Dec 20 12:48:34 PM PST 23
Finished Dec 20 12:54:46 PM PST 23
Peak memory 200976 kb
Host smart-b3a7752d-03f9-4d37-b0c7-779b873a66d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793807772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2793807772
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4112431986
Short name T220
Test name
Test status
Simulation time 499731146662 ps
CPU time 263.71 seconds
Started Dec 20 12:48:34 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 200912 kb
Host smart-fb3a3981-0daf-4249-8c74-ed7068227dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112431986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4112431986
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1734668652
Short name T835
Test name
Test status
Simulation time 163986956887 ps
CPU time 66.7 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:50:54 PM PST 23
Peak memory 201068 kb
Host smart-fe791046-f6b5-40bd-9a0f-48633180800b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734668652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1734668652
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2084168710
Short name T830
Test name
Test status
Simulation time 493748576481 ps
CPU time 302.48 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:54:55 PM PST 23
Peak memory 200940 kb
Host smart-3f67bd44-db8b-4b0d-85e5-beb2ab3f2b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084168710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2084168710
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.985674602
Short name T502
Test name
Test status
Simulation time 160924681299 ps
CPU time 178.49 seconds
Started Dec 20 12:48:53 PM PST 23
Finished Dec 20 12:53:05 PM PST 23
Peak memory 200964 kb
Host smart-b69299d7-fc65-4f4a-925e-602b0de24fb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=985674602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.985674602
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3696711177
Short name T57
Test name
Test status
Simulation time 163122449929 ps
CPU time 198.42 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:53:03 PM PST 23
Peak memory 200984 kb
Host smart-2f8bbc8e-83c9-4cc8-a84a-4e93733915f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696711177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3696711177
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1983230879
Short name T836
Test name
Test status
Simulation time 491215145432 ps
CPU time 1062.88 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 01:07:36 PM PST 23
Peak memory 201008 kb
Host smart-3ac9367a-ba5b-423e-bd19-3bf6723338a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983230879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1983230879
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2648590464
Short name T595
Test name
Test status
Simulation time 85799810076 ps
CPU time 449.06 seconds
Started Dec 20 12:48:51 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 201356 kb
Host smart-d51e8801-518a-421a-8464-e130e318dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648590464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2648590464
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2404445989
Short name T604
Test name
Test status
Simulation time 27966897168 ps
CPU time 16.86 seconds
Started Dec 20 12:48:48 PM PST 23
Finished Dec 20 12:50:10 PM PST 23
Peak memory 200820 kb
Host smart-98a18526-e6a9-491b-a5c2-2d3a530b4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404445989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2404445989
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.932495554
Short name T812
Test name
Test status
Simulation time 4944271349 ps
CPU time 3.84 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:49:40 PM PST 23
Peak memory 200856 kb
Host smart-54d122a0-7061-4e4d-b6e8-f7d0f8f27227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932495554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.932495554
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3482680323
Short name T659
Test name
Test status
Simulation time 6046572407 ps
CPU time 13.69 seconds
Started Dec 20 12:48:31 PM PST 23
Finished Dec 20 12:50:01 PM PST 23
Peak memory 200704 kb
Host smart-b6a7c584-9464-47c6-8ef2-d70022506746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482680323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3482680323
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2114803212
Short name T298
Test name
Test status
Simulation time 65111594549 ps
CPU time 41.6 seconds
Started Dec 20 12:49:22 PM PST 23
Finished Dec 20 12:51:03 PM PST 23
Peak memory 209340 kb
Host smart-12efa0e8-7cd3-4612-9875-d7f15285ff34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114803212 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2114803212
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3250996117
Short name T417
Test name
Test status
Simulation time 507541151 ps
CPU time 0.89 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:50:04 PM PST 23
Peak memory 200748 kb
Host smart-6cbe7235-bc96-4988-a521-9b9323e8eb9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250996117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3250996117
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.10391589
Short name T132
Test name
Test status
Simulation time 318753706482 ps
CPU time 723 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 01:01:59 PM PST 23
Peak memory 201100 kb
Host smart-258aa7d2-51f7-445e-b31a-b56a9c2ba149
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gatin
g.10391589
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3539854764
Short name T271
Test name
Test status
Simulation time 326807241629 ps
CPU time 236.67 seconds
Started Dec 20 12:48:44 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 201032 kb
Host smart-ff24c14a-2e37-47ef-a440-44a0e9ef1e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539854764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3539854764
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2728026726
Short name T328
Test name
Test status
Simulation time 168256380067 ps
CPU time 426.81 seconds
Started Dec 20 12:49:27 PM PST 23
Finished Dec 20 12:57:31 PM PST 23
Peak memory 200928 kb
Host smart-d1ef334b-c540-4032-b9f2-868f4a68a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728026726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2728026726
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1305938069
Short name T703
Test name
Test status
Simulation time 503209123527 ps
CPU time 264.25 seconds
Started Dec 20 12:48:49 PM PST 23
Finished Dec 20 12:54:25 PM PST 23
Peak memory 201004 kb
Host smart-f288f81f-f6fa-40a8-b1ca-f9ff4d1781cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305938069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1305938069
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3456502575
Short name T625
Test name
Test status
Simulation time 334682858296 ps
CPU time 761.87 seconds
Started Dec 20 12:48:54 PM PST 23
Finished Dec 20 01:02:39 PM PST 23
Peak memory 200824 kb
Host smart-84c9a999-1be9-4ec8-9d38-9d69d0a219eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456502575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3456502575
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1714805228
Short name T567
Test name
Test status
Simulation time 329292943266 ps
CPU time 489.74 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 200944 kb
Host smart-ba538036-a245-4382-9909-22853f404622
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714805228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1714805228
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.4058684650
Short name T770
Test name
Test status
Simulation time 488370512722 ps
CPU time 314.21 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:55:13 PM PST 23
Peak memory 201020 kb
Host smart-544875f1-a7aa-4c4f-bd07-793d6f53af7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058684650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.4058684650
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.405044181
Short name T149
Test name
Test status
Simulation time 487622131202 ps
CPU time 246.82 seconds
Started Dec 20 12:49:15 PM PST 23
Finished Dec 20 12:54:22 PM PST 23
Peak memory 200984 kb
Host smart-b3dbf78a-80fc-4d13-a7a6-c4ee29d4aaa1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405044181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.405044181
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2488265873
Short name T199
Test name
Test status
Simulation time 114313956626 ps
CPU time 422.84 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:57:10 PM PST 23
Peak memory 201456 kb
Host smart-3d2a921a-3a18-44d1-bef9-847cf37be560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488265873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2488265873
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1363610716
Short name T721
Test name
Test status
Simulation time 36998413103 ps
CPU time 87.37 seconds
Started Dec 20 12:49:26 PM PST 23
Finished Dec 20 12:51:51 PM PST 23
Peak memory 200872 kb
Host smart-7060fd6a-457d-4e9d-99c9-4507168889c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363610716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1363610716
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3709450438
Short name T427
Test name
Test status
Simulation time 3397396139 ps
CPU time 1.51 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:50:11 PM PST 23
Peak memory 200796 kb
Host smart-4fdd09f2-ba58-4b96-802c-463f3f18852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709450438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3709450438
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3717809639
Short name T554
Test name
Test status
Simulation time 5977293184 ps
CPU time 3.37 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:50:04 PM PST 23
Peak memory 200764 kb
Host smart-24455b4e-4523-4041-8d47-537f668227a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717809639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3717809639
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3200197101
Short name T331
Test name
Test status
Simulation time 330189442196 ps
CPU time 213.68 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:53:38 PM PST 23
Peak memory 200968 kb
Host smart-378f7268-6286-4a36-86c0-d4ad6d56fa1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200197101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3200197101
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1760983205
Short name T90
Test name
Test status
Simulation time 46845965022 ps
CPU time 57.96 seconds
Started Dec 20 12:49:25 PM PST 23
Finished Dec 20 12:51:21 PM PST 23
Peak memory 216996 kb
Host smart-4337ba2b-59fb-4c3a-b519-7f9ccacf7944
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760983205 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1760983205
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4117655077
Short name T531
Test name
Test status
Simulation time 520592895 ps
CPU time 0.69 seconds
Started Dec 20 12:49:16 PM PST 23
Finished Dec 20 12:50:18 PM PST 23
Peak memory 200676 kb
Host smart-30007fe7-45d7-455d-9fa2-d20c436eb042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117655077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4117655077
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3478525989
Short name T137
Test name
Test status
Simulation time 323486449331 ps
CPU time 217.33 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:53:44 PM PST 23
Peak memory 200928 kb
Host smart-1c92e750-6ed4-4daa-bf0e-7cff45cb3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478525989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3478525989
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4039125810
Short name T633
Test name
Test status
Simulation time 165358822905 ps
CPU time 107.14 seconds
Started Dec 20 12:48:54 PM PST 23
Finished Dec 20 12:51:44 PM PST 23
Peak memory 200760 kb
Host smart-1be94289-7c03-4eb0-b435-071e1d844a81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039125810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4039125810
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3121643488
Short name T628
Test name
Test status
Simulation time 166176789916 ps
CPU time 190.31 seconds
Started Dec 20 12:48:54 PM PST 23
Finished Dec 20 12:53:06 PM PST 23
Peak memory 200740 kb
Host smart-39d52987-4c3a-4f1d-80a1-d4ec69e7d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121643488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3121643488
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1773446743
Short name T697
Test name
Test status
Simulation time 326325320223 ps
CPU time 350.24 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:55:47 PM PST 23
Peak memory 200876 kb
Host smart-55230cbd-34ab-4ae0-8c3c-e83dc858e11a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773446743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1773446743
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3900522806
Short name T671
Test name
Test status
Simulation time 159754500321 ps
CPU time 317.82 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:55:25 PM PST 23
Peak memory 200908 kb
Host smart-d46bbead-1d59-4d69-ad57-b866c8ca70a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900522806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3900522806
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2718806196
Short name T675
Test name
Test status
Simulation time 333615399394 ps
CPU time 413.56 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 200832 kb
Host smart-92510b93-750a-48f8-896f-481b4f00d37f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718806196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2718806196
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1651351588
Short name T451
Test name
Test status
Simulation time 80190978712 ps
CPU time 413.75 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:57:07 PM PST 23
Peak memory 201288 kb
Host smart-aa06c1b2-b0ae-420b-9bae-dc1b4ab33094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651351588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1651351588
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2104413692
Short name T163
Test name
Test status
Simulation time 38913483084 ps
CPU time 87.53 seconds
Started Dec 20 12:48:54 PM PST 23
Finished Dec 20 12:51:24 PM PST 23
Peak memory 200764 kb
Host smart-0273ed03-edae-4c90-8c91-554c99d4ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104413692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2104413692
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3634203782
Short name T464
Test name
Test status
Simulation time 4566470460 ps
CPU time 5.02 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:50:03 PM PST 23
Peak memory 200856 kb
Host smart-774bf9eb-a537-47bb-b6c6-a359ed2444bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634203782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3634203782
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3129822640
Short name T841
Test name
Test status
Simulation time 5760333071 ps
CPU time 14.08 seconds
Started Dec 20 12:48:55 PM PST 23
Finished Dec 20 12:50:10 PM PST 23
Peak memory 200516 kb
Host smart-abf64219-b96f-4cb2-b97e-a7226db51013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129822640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3129822640
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2152193791
Short name T804
Test name
Test status
Simulation time 203487366526 ps
CPU time 407.06 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:56:59 PM PST 23
Peak memory 200972 kb
Host smart-a1e87cc4-6d62-4651-a839-fb2d604e3d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152193791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2152193791
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1974558728
Short name T735
Test name
Test status
Simulation time 56054414081 ps
CPU time 108.09 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:52:01 PM PST 23
Peak memory 209716 kb
Host smart-a670291d-a8e6-4e3a-9ef1-1e8ad1c408d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974558728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1974558728
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1833788855
Short name T420
Test name
Test status
Simulation time 522150132 ps
CPU time 1.72 seconds
Started Dec 20 12:49:35 PM PST 23
Finished Dec 20 12:50:31 PM PST 23
Peak memory 200748 kb
Host smart-e566e334-c6ea-4a6e-bcd7-d91ac7202449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833788855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1833788855
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.354668522
Short name T790
Test name
Test status
Simulation time 169631009457 ps
CPU time 209.21 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:53:37 PM PST 23
Peak memory 201060 kb
Host smart-ea77baf2-6087-425f-96b0-d53c9eed14dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354668522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.354668522
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.421831475
Short name T229
Test name
Test status
Simulation time 495055585381 ps
CPU time 1153.74 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 01:09:21 PM PST 23
Peak memory 201044 kb
Host smart-2ff7561a-8e19-4c27-b397-ce06799ce5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421831475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.421831475
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2733342960
Short name T769
Test name
Test status
Simulation time 488214281656 ps
CPU time 1107.92 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 01:08:44 PM PST 23
Peak memory 200972 kb
Host smart-13367b18-b2e6-4f30-aef5-91760ae4834b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733342960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2733342960
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1015519349
Short name T147
Test name
Test status
Simulation time 488678648554 ps
CPU time 106.45 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:51:58 PM PST 23
Peak memory 200904 kb
Host smart-d524b25c-e109-4c01-a843-a81711ad95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015519349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1015519349
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2249578967
Short name T498
Test name
Test status
Simulation time 162665276278 ps
CPU time 195.03 seconds
Started Dec 20 12:49:18 PM PST 23
Finished Dec 20 12:53:33 PM PST 23
Peak memory 201004 kb
Host smart-e6a45a73-e4d1-48c5-b99e-af6d5f506474
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249578967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2249578967
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1868702835
Short name T329
Test name
Test status
Simulation time 194634614708 ps
CPU time 492.44 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:58:26 PM PST 23
Peak memory 200900 kb
Host smart-b0d4c165-edd4-4db8-9063-007103f4a0eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868702835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1868702835
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2861373634
Short name T171
Test name
Test status
Simulation time 322467733143 ps
CPU time 177.1 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 200952 kb
Host smart-be948455-9da1-4523-beaf-ed4f96fb126b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861373634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2861373634
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4156689419
Short name T12
Test name
Test status
Simulation time 110100529761 ps
CPU time 581.66 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:59:53 PM PST 23
Peak memory 201372 kb
Host smart-a09a5fdb-4bea-49fb-82ea-e8f807eb79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156689419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4156689419
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3096935817
Short name T773
Test name
Test status
Simulation time 31837136592 ps
CPU time 19.19 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:50:25 PM PST 23
Peak memory 200764 kb
Host smart-b6148f19-30cb-4a12-b957-0909d21adcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096935817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3096935817
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2238669977
Short name T537
Test name
Test status
Simulation time 3544569692 ps
CPU time 2.97 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 200724 kb
Host smart-dfbf7fdc-5dde-4c3f-a82d-0a0c00661465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238669977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2238669977
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.318247474
Short name T166
Test name
Test status
Simulation time 5903057180 ps
CPU time 4.09 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:50:09 PM PST 23
Peak memory 200728 kb
Host smart-a8531ed8-161f-43de-8a99-119a9e7fddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318247474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.318247474
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2559183817
Short name T136
Test name
Test status
Simulation time 176057784357 ps
CPU time 78.03 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:51:29 PM PST 23
Peak memory 200916 kb
Host smart-0e88a565-51d7-4904-bc07-9671a31a1b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559183817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2559183817
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.703757000
Short name T218
Test name
Test status
Simulation time 43743211440 ps
CPU time 86.86 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:51:39 PM PST 23
Peak memory 209356 kb
Host smart-487ea99d-b3ab-484b-aff7-27f370e7159c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703757000 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.703757000
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3118803924
Short name T521
Test name
Test status
Simulation time 469426615 ps
CPU time 0.67 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:50:11 PM PST 23
Peak memory 200576 kb
Host smart-0518ddec-0792-4bab-8035-ed40022f1d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118803924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3118803924
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3546436524
Short name T700
Test name
Test status
Simulation time 330940739531 ps
CPU time 582.1 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:59:46 PM PST 23
Peak memory 200920 kb
Host smart-2bfcfe5a-10a3-46a1-8272-fb013b67709b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546436524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3546436524
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.486791242
Short name T849
Test name
Test status
Simulation time 329533760493 ps
CPU time 190.92 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:53:20 PM PST 23
Peak memory 200780 kb
Host smart-38395a0f-3b04-489d-b608-fd208e7e97c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486791242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.486791242
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.249999122
Short name T755
Test name
Test status
Simulation time 165621515409 ps
CPU time 97.73 seconds
Started Dec 20 12:49:28 PM PST 23
Finished Dec 20 12:52:03 PM PST 23
Peak memory 200708 kb
Host smart-8de38937-6897-4f0e-bcfe-fcf9e6e96c4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=249999122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.249999122
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.399404389
Short name T511
Test name
Test status
Simulation time 500749314728 ps
CPU time 249.09 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:54:25 PM PST 23
Peak memory 200968 kb
Host smart-e20b9fa4-3f0c-4e61-a248-e03369a6bc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399404389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.399404389
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2480804367
Short name T584
Test name
Test status
Simulation time 326105338432 ps
CPU time 759.06 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 01:02:45 PM PST 23
Peak memory 200872 kb
Host smart-bec2f682-256d-44bb-a377-6fb19486b77c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480804367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2480804367
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1138238608
Short name T209
Test name
Test status
Simulation time 88193844303 ps
CPU time 488.24 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:58:19 PM PST 23
Peak memory 201228 kb
Host smart-5dca7f27-9d1c-4796-83ea-2e7c4136d2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138238608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1138238608
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.992555443
Short name T151
Test name
Test status
Simulation time 44905722448 ps
CPU time 52.48 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:51:00 PM PST 23
Peak memory 200804 kb
Host smart-c64a95a0-0b82-4119-ae1f-ab6f7abd43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992555443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.992555443
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1883605633
Short name T436
Test name
Test status
Simulation time 5213666398 ps
CPU time 6.79 seconds
Started Dec 20 12:49:22 PM PST 23
Finished Dec 20 12:50:29 PM PST 23
Peak memory 200668 kb
Host smart-83748781-0045-47e5-aa21-89b3b06c1ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883605633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1883605633
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.990992157
Short name T577
Test name
Test status
Simulation time 5945929735 ps
CPU time 16.62 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 12:50:37 PM PST 23
Peak memory 200804 kb
Host smart-af27c98a-2c90-46b6-8030-3527ff87e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990992157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.990992157
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.727568413
Short name T168
Test name
Test status
Simulation time 309758462553 ps
CPU time 592.19 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 12:59:56 PM PST 23
Peak memory 209536 kb
Host smart-cdb595e3-f86b-474d-98bd-11259c12b953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727568413 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.727568413
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2125828689
Short name T43
Test name
Test status
Simulation time 458916754 ps
CPU time 0.89 seconds
Started Dec 20 12:48:53 PM PST 23
Finished Dec 20 12:49:56 PM PST 23
Peak memory 200684 kb
Host smart-4f74038a-9b19-4fb2-9801-12060d9f1578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125828689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2125828689
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2255254555
Short name T824
Test name
Test status
Simulation time 165493331394 ps
CPU time 203.91 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 200964 kb
Host smart-ed65f451-a898-4752-b1a0-50d46aceba96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255254555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2255254555
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4037516131
Short name T333
Test name
Test status
Simulation time 169401115488 ps
CPU time 167.41 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 12:52:43 PM PST 23
Peak memory 201024 kb
Host smart-812005d4-2a39-40cf-8003-e19dd9341541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037516131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4037516131
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1616502940
Short name T844
Test name
Test status
Simulation time 324105021967 ps
CPU time 212.6 seconds
Started Dec 20 12:49:17 PM PST 23
Finished Dec 20 12:53:51 PM PST 23
Peak memory 200984 kb
Host smart-2060b153-31e4-4e1c-978a-ee39ef3f8f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616502940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1616502940
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1048836079
Short name T706
Test name
Test status
Simulation time 499295759148 ps
CPU time 295.74 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 200832 kb
Host smart-57560a0f-da0e-4a38-90ff-f516595ebf60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048836079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1048836079
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2963623473
Short name T318
Test name
Test status
Simulation time 331429979207 ps
CPU time 188.69 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:53:20 PM PST 23
Peak memory 200804 kb
Host smart-5ed25c4d-3046-4a3b-bceb-97ac4d8b1415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963623473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2963623473
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3243994009
Short name T154
Test name
Test status
Simulation time 327509145705 ps
CPU time 46.23 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:50:53 PM PST 23
Peak memory 200876 kb
Host smart-4a3ba9ab-2de6-4399-bda3-bd691ff55709
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243994009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3243994009
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3968863262
Short name T624
Test name
Test status
Simulation time 329764347587 ps
CPU time 795.05 seconds
Started Dec 20 12:48:58 PM PST 23
Finished Dec 20 01:03:15 PM PST 23
Peak memory 200948 kb
Host smart-8b919f0d-645a-4bbf-9f1c-06e622886094
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968863262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3968863262
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1682824900
Short name T540
Test name
Test status
Simulation time 79003997938 ps
CPU time 429.17 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:57:18 PM PST 23
Peak memory 201328 kb
Host smart-2ec23e17-d780-4e06-b22d-48503c4c10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682824900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1682824900
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.142173864
Short name T763
Test name
Test status
Simulation time 25602293150 ps
CPU time 14.99 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:50:22 PM PST 23
Peak memory 200820 kb
Host smart-f3277638-2bd6-4c18-87d0-ad0cfe9e7f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142173864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.142173864
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4042031471
Short name T169
Test name
Test status
Simulation time 4902565540 ps
CPU time 1.85 seconds
Started Dec 20 12:48:55 PM PST 23
Finished Dec 20 12:49:59 PM PST 23
Peak memory 200804 kb
Host smart-7646e41f-84c3-4b05-81d0-d2350d0fae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042031471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4042031471
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3382019263
Short name T434
Test name
Test status
Simulation time 6113642816 ps
CPU time 4.86 seconds
Started Dec 20 12:48:55 PM PST 23
Finished Dec 20 12:50:01 PM PST 23
Peak memory 200716 kb
Host smart-912c7598-4815-4ed4-9a69-e08925c48acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382019263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3382019263
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.113577540
Short name T647
Test name
Test status
Simulation time 518839617043 ps
CPU time 382.59 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 200844 kb
Host smart-763692dc-dc66-4fc5-bee3-b174d194d70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113577540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
113577540
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3425011932
Short name T847
Test name
Test status
Simulation time 457730066 ps
CPU time 0.66 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 12:50:20 PM PST 23
Peak memory 200668 kb
Host smart-59fed50d-ba9f-4b8d-86c0-66187d997e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425011932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3425011932
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3555399528
Short name T789
Test name
Test status
Simulation time 329627531737 ps
CPU time 198.93 seconds
Started Dec 20 12:49:11 PM PST 23
Finished Dec 20 12:53:32 PM PST 23
Peak memory 200960 kb
Host smart-12e5a409-6674-45f8-8deb-713be0fca7cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555399528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3555399528
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2235127476
Short name T660
Test name
Test status
Simulation time 332924816537 ps
CPU time 823.99 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 01:03:51 PM PST 23
Peak memory 201056 kb
Host smart-b05430fd-64a6-47f4-988e-108fde3596de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235127476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2235127476
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1148027809
Short name T23
Test name
Test status
Simulation time 165623162588 ps
CPU time 187.06 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 200892 kb
Host smart-bf1a23e0-d75a-4b97-a591-ae23adeb2adc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148027809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1148027809
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3864703401
Short name T308
Test name
Test status
Simulation time 327470246556 ps
CPU time 290.24 seconds
Started Dec 20 12:49:01 PM PST 23
Finished Dec 20 12:54:53 PM PST 23
Peak memory 201000 kb
Host smart-8addbd15-9a70-424b-ac9d-0e87167aad91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864703401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3864703401
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1753407878
Short name T731
Test name
Test status
Simulation time 167434393176 ps
CPU time 70.03 seconds
Started Dec 20 12:49:01 PM PST 23
Finished Dec 20 12:51:14 PM PST 23
Peak memory 200708 kb
Host smart-605bace0-6ec6-4c4b-b3fe-c20508ff67d5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753407878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1753407878
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1985970855
Short name T796
Test name
Test status
Simulation time 126369356807 ps
CPU time 457.92 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:57:48 PM PST 23
Peak memory 201440 kb
Host smart-fcbc803f-a0b2-453c-8921-28177c871505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985970855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1985970855
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1065772409
Short name T724
Test name
Test status
Simulation time 33628805539 ps
CPU time 11.4 seconds
Started Dec 20 12:49:30 PM PST 23
Finished Dec 20 12:50:37 PM PST 23
Peak memory 200572 kb
Host smart-12cca261-e765-4f30-b9e6-1d65223a0bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065772409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1065772409
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3916021381
Short name T413
Test name
Test status
Simulation time 4166704321 ps
CPU time 2.14 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 200784 kb
Host smart-e65f6a2b-0686-4076-b45a-72ec6a52c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916021381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3916021381
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3229691530
Short name T777
Test name
Test status
Simulation time 5873757143 ps
CPU time 7.73 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:50:24 PM PST 23
Peak memory 200740 kb
Host smart-894cbe5e-9a17-49f0-a24a-50c0ec466795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229691530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3229691530
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2526064903
Short name T698
Test name
Test status
Simulation time 31742541490 ps
CPU time 38.76 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:50:39 PM PST 23
Peak memory 209388 kb
Host smart-8b5246e7-b8ec-4039-ad5b-ceaaba98d41b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526064903 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2526064903
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2976341408
Short name T618
Test name
Test status
Simulation time 495385453 ps
CPU time 0.91 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:50:09 PM PST 23
Peak memory 200592 kb
Host smart-09e08348-b033-450b-bdd0-9368ea9d9a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976341408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2976341408
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3477937327
Short name T737
Test name
Test status
Simulation time 329743464496 ps
CPU time 103.85 seconds
Started Dec 20 12:49:15 PM PST 23
Finished Dec 20 12:52:01 PM PST 23
Peak memory 200868 kb
Host smart-b5a3dc14-b332-4d8f-a4d5-c73fa53f5e8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477937327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3477937327
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2246632303
Short name T538
Test name
Test status
Simulation time 166523519678 ps
CPU time 89.93 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:51:49 PM PST 23
Peak memory 201036 kb
Host smart-be1f7fe6-66b4-4ecb-b289-68017e8d9e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246632303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2246632303
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2436113705
Short name T324
Test name
Test status
Simulation time 489557611757 ps
CPU time 353.38 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:56:03 PM PST 23
Peak memory 200924 kb
Host smart-d9e85533-f434-46f0-9fad-b9622e48a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436113705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2436113705
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3051273745
Short name T479
Test name
Test status
Simulation time 329688301451 ps
CPU time 789.96 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 01:03:15 PM PST 23
Peak memory 200972 kb
Host smart-42ddfa44-d320-4f1e-b01e-0be63d0a7c14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051273745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3051273745
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3826062406
Short name T322
Test name
Test status
Simulation time 491144995373 ps
CPU time 422.15 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:57:15 PM PST 23
Peak memory 200944 kb
Host smart-842106f8-a5b9-44de-8ba9-6a9be1e6bcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826062406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3826062406
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.972981326
Short name T682
Test name
Test status
Simulation time 491429745814 ps
CPU time 1148.72 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 01:09:20 PM PST 23
Peak memory 200868 kb
Host smart-e4c01da1-7cf8-45a3-8bb3-107f7fd50871
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=972981326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.972981326
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.609569209
Short name T833
Test name
Test status
Simulation time 184589111145 ps
CPU time 100.59 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:51:51 PM PST 23
Peak memory 200996 kb
Host smart-2c0b51d6-a6e0-442d-b7e3-2f9b41275069
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609569209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.609569209
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2202058113
Short name T481
Test name
Test status
Simulation time 488875554970 ps
CPU time 172.04 seconds
Started Dec 20 12:49:02 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 200760 kb
Host smart-b91120be-76b1-4ba3-ab46-4dfaad887332
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202058113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2202058113
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1241361400
Short name T170
Test name
Test status
Simulation time 127050030566 ps
CPU time 492.28 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 12:58:19 PM PST 23
Peak memory 201256 kb
Host smart-f7fe600d-05d0-4437-a159-8c23a2045da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241361400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1241361400
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2808364603
Short name T56
Test name
Test status
Simulation time 30780163563 ps
CPU time 70.67 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:51:30 PM PST 23
Peak memory 200872 kb
Host smart-a3e4e50f-69e0-435d-b58b-6aee046e7b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808364603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2808364603
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3312215451
Short name T753
Test name
Test status
Simulation time 5214718906 ps
CPU time 7.38 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:50:18 PM PST 23
Peak memory 200852 kb
Host smart-ff8da2e6-bc1e-4a1c-9be7-61bbc91e6990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312215451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3312215451
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3268599196
Short name T793
Test name
Test status
Simulation time 5772183702 ps
CPU time 4.57 seconds
Started Dec 20 12:49:18 PM PST 23
Finished Dec 20 12:50:23 PM PST 23
Peak memory 200796 kb
Host smart-185b5d45-3956-408e-af6a-6c5fee3476e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268599196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3268599196
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3749281244
Short name T506
Test name
Test status
Simulation time 279376251 ps
CPU time 1.21 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:50:10 PM PST 23
Peak memory 200724 kb
Host smart-d579fabb-308d-48d4-8774-6d59656bdbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749281244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3749281244
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.970769056
Short name T145
Test name
Test status
Simulation time 493279705495 ps
CPU time 306.02 seconds
Started Dec 20 12:49:30 PM PST 23
Finished Dec 20 12:55:32 PM PST 23
Peak memory 200928 kb
Host smart-8bfd46a7-b401-49f5-a2cd-f7e5fa98fbc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970769056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.970769056
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.239624090
Short name T489
Test name
Test status
Simulation time 161056676594 ps
CPU time 83.29 seconds
Started Dec 20 12:48:53 PM PST 23
Finished Dec 20 12:51:30 PM PST 23
Peak memory 200916 kb
Host smart-0c7819b6-46fd-414d-8658-b85c574b7d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239624090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.239624090
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1649280571
Short name T712
Test name
Test status
Simulation time 166835096229 ps
CPU time 105.99 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:51:53 PM PST 23
Peak memory 200848 kb
Host smart-ae8eefed-2310-4bfb-9d33-dab514e16e53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649280571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1649280571
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1340260694
Short name T714
Test name
Test status
Simulation time 326152310759 ps
CPU time 362.08 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:56:04 PM PST 23
Peak memory 200744 kb
Host smart-40faff1c-0dd0-44f7-8faf-8705a84a13b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340260694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1340260694
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2883563816
Short name T126
Test name
Test status
Simulation time 498687272753 ps
CPU time 306.46 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:55:34 PM PST 23
Peak memory 200860 kb
Host smart-b9fa3a4b-de73-4b9a-9df3-83b3e920e77a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883563816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2883563816
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1832336637
Short name T50
Test name
Test status
Simulation time 167647899293 ps
CPU time 360.36 seconds
Started Dec 20 12:48:58 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 200916 kb
Host smart-b16396af-0213-4158-aafe-e248fa730f76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832336637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1832336637
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3641780633
Short name T692
Test name
Test status
Simulation time 488310380200 ps
CPU time 1112.09 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 01:08:59 PM PST 23
Peak memory 200892 kb
Host smart-0fca207b-915a-45a5-8ffd-13ca3a107182
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641780633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3641780633
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4068655727
Short name T354
Test name
Test status
Simulation time 86882734473 ps
CPU time 472.65 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 201164 kb
Host smart-33754812-d4e5-424f-bbe5-19b21ad76aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068655727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4068655727
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3417067727
Short name T501
Test name
Test status
Simulation time 43979571319 ps
CPU time 26.74 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200744 kb
Host smart-bd8067ad-a8c8-4112-9811-6422e16359f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417067727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3417067727
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2687683885
Short name T513
Test name
Test status
Simulation time 3678462272 ps
CPU time 1.23 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:50:09 PM PST 23
Peak memory 200768 kb
Host smart-b3c9fb57-ef70-497d-a8c7-e88686cfea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687683885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2687683885
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2673748994
Short name T402
Test name
Test status
Simulation time 5755999775 ps
CPU time 3.51 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:50:17 PM PST 23
Peak memory 200800 kb
Host smart-c2d16164-0ce9-4cef-8cfd-16efff3c1840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673748994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2673748994
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1062925645
Short name T787
Test name
Test status
Simulation time 434885233 ps
CPU time 0.75 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:50:06 PM PST 23
Peak memory 200752 kb
Host smart-385a524b-4b1b-4cbd-9dd7-317dc3f432c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062925645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1062925645
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.734046191
Short name T305
Test name
Test status
Simulation time 167502664697 ps
CPU time 49.43 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:51:08 PM PST 23
Peak memory 200776 kb
Host smart-3b598217-632c-428b-94d9-0b3c4a2123fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734046191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.734046191
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2378277735
Short name T683
Test name
Test status
Simulation time 331298826235 ps
CPU time 774.47 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 01:03:23 PM PST 23
Peak memory 200928 kb
Host smart-3ee0f733-6a2e-4222-9c2f-571c18be7110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378277735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2378277735
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3516547957
Short name T627
Test name
Test status
Simulation time 491678213383 ps
CPU time 75.5 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:51:16 PM PST 23
Peak memory 201048 kb
Host smart-c0e159ed-f776-4a51-9576-445366f6de43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516547957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3516547957
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.793852920
Short name T268
Test name
Test status
Simulation time 165482600624 ps
CPU time 190.71 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:53:16 PM PST 23
Peak memory 201060 kb
Host smart-cc16e60a-4a52-46c3-a0ce-a66af168a1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793852920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.793852920
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.4246024504
Short name T460
Test name
Test status
Simulation time 487397918314 ps
CPU time 559.91 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:59:34 PM PST 23
Peak memory 200976 kb
Host smart-a6ffa6d7-28e2-4351-b80a-e4359c90ae48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246024504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.4246024504
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4233822667
Short name T530
Test name
Test status
Simulation time 165511042552 ps
CPU time 394.27 seconds
Started Dec 20 12:49:00 PM PST 23
Finished Dec 20 12:56:38 PM PST 23
Peak memory 200728 kb
Host smart-c7a5a079-00b8-49de-a9e2-3c8f1db7b65f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233822667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4233822667
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1588313800
Short name T598
Test name
Test status
Simulation time 165534163488 ps
CPU time 413.52 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:57:02 PM PST 23
Peak memory 200964 kb
Host smart-b81429ee-f0e4-44c3-8730-87394ad18c27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588313800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1588313800
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.809106011
Short name T204
Test name
Test status
Simulation time 114218970359 ps
CPU time 478.84 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:58:03 PM PST 23
Peak memory 201392 kb
Host smart-d5fe9899-6545-4fa3-b31a-06ddd0c08a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809106011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.809106011
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3398863416
Short name T410
Test name
Test status
Simulation time 23935863850 ps
CPU time 4.54 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 200760 kb
Host smart-6364f55b-5acb-4721-b356-2e1927171871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398863416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3398863416
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3799989368
Short name T53
Test name
Test status
Simulation time 4392545703 ps
CPU time 2.45 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:50:25 PM PST 23
Peak memory 200812 kb
Host smart-c26333b6-cdcd-4545-a0ca-64321fd174e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799989368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3799989368
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1214698366
Short name T744
Test name
Test status
Simulation time 5602652415 ps
CPU time 7.55 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 200512 kb
Host smart-25ded2e4-5dda-4a82-8da3-e1b3cce4d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214698366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1214698366
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1279654727
Short name T713
Test name
Test status
Simulation time 428600673 ps
CPU time 1.64 seconds
Started Dec 20 12:47:57 PM PST 23
Finished Dec 20 12:49:12 PM PST 23
Peak memory 200812 kb
Host smart-ae43c4f1-1a38-40e9-977c-39304f05feeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279654727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1279654727
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3210276087
Short name T282
Test name
Test status
Simulation time 198844032022 ps
CPU time 106.34 seconds
Started Dec 20 12:47:16 PM PST 23
Finished Dec 20 12:49:56 PM PST 23
Peak memory 200984 kb
Host smart-f2b09ccd-de42-423f-afb0-ee581db1f741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210276087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3210276087
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2975547660
Short name T814
Test name
Test status
Simulation time 333116974025 ps
CPU time 181.18 seconds
Started Dec 20 12:47:13 PM PST 23
Finished Dec 20 12:51:09 PM PST 23
Peak memory 200976 kb
Host smart-260769b3-ae93-4ec0-b558-ff2e5f5f7240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975547660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2975547660
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.815119346
Short name T728
Test name
Test status
Simulation time 488791203715 ps
CPU time 1170.45 seconds
Started Dec 20 12:47:06 PM PST 23
Finished Dec 20 01:07:19 PM PST 23
Peak memory 200980 kb
Host smart-724a9012-c368-47fd-b72e-79ed680005ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=815119346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.815119346
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3817100502
Short name T256
Test name
Test status
Simulation time 329932126685 ps
CPU time 192.45 seconds
Started Dec 20 12:47:35 PM PST 23
Finished Dec 20 12:52:07 PM PST 23
Peak memory 200712 kb
Host smart-c35360c4-151a-430b-9bd1-ca4508737a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817100502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3817100502
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3523908581
Short name T689
Test name
Test status
Simulation time 324931142722 ps
CPU time 765.88 seconds
Started Dec 20 12:47:31 PM PST 23
Finished Dec 20 01:01:34 PM PST 23
Peak memory 200724 kb
Host smart-d37b9ae7-ce87-44ea-bc54-d5eac9b25c20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523908581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3523908581
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4201593589
Short name T486
Test name
Test status
Simulation time 162926887259 ps
CPU time 100.81 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:49:39 PM PST 23
Peak memory 200696 kb
Host smart-0b795a37-1ba9-450b-8db6-e3fbec1f9de9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201593589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4201593589
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3444139200
Short name T825
Test name
Test status
Simulation time 39515667590 ps
CPU time 7.64 seconds
Started Dec 20 12:47:39 PM PST 23
Finished Dec 20 12:49:06 PM PST 23
Peak memory 200780 kb
Host smart-2536089a-f686-4221-ba61-09a7020f9322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444139200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3444139200
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3061490295
Short name T519
Test name
Test status
Simulation time 3448404468 ps
CPU time 8.92 seconds
Started Dec 20 12:48:52 PM PST 23
Finished Dec 20 12:50:04 PM PST 23
Peak memory 200392 kb
Host smart-aa1e3839-86c8-4d4d-9849-00d265168394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061490295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3061490295
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.487493305
Short name T47
Test name
Test status
Simulation time 7223935238 ps
CPU time 8.47 seconds
Started Dec 20 12:47:26 PM PST 23
Finished Dec 20 12:48:49 PM PST 23
Peak memory 217208 kb
Host smart-8ff99b72-ad63-4ecf-b689-dbd8c1493b24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487493305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.487493305
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2964859007
Short name T684
Test name
Test status
Simulation time 5938197827 ps
CPU time 4.46 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:48:10 PM PST 23
Peak memory 200568 kb
Host smart-0ac0d3ce-0086-4233-b108-671e3d16cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964859007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2964859007
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2186751036
Short name T797
Test name
Test status
Simulation time 204965073538 ps
CPU time 491.96 seconds
Started Dec 20 12:47:26 PM PST 23
Finished Dec 20 12:56:51 PM PST 23
Peak memory 201012 kb
Host smart-556eacd3-db6f-4374-9e52-c131852f9559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186751036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2186751036
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1261165124
Short name T765
Test name
Test status
Simulation time 99793554504 ps
CPU time 140.48 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:52:19 PM PST 23
Peak memory 216680 kb
Host smart-4b69aa04-6b1c-4ae7-af95-9a3a3bab969e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261165124 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1261165124
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1194280694
Short name T480
Test name
Test status
Simulation time 415365464 ps
CPU time 1.62 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:50:32 PM PST 23
Peak memory 200704 kb
Host smart-5bf424c0-09f9-48c5-b5ae-cb347fae4943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194280694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1194280694
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.50164378
Short name T326
Test name
Test status
Simulation time 164442018645 ps
CPU time 83.37 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:51:37 PM PST 23
Peak memory 200872 kb
Host smart-0e0317bd-f81f-4b24-9b53-d2608233e817
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50164378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gatin
g.50164378
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2375502572
Short name T134
Test name
Test status
Simulation time 331888597439 ps
CPU time 193.79 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:53:24 PM PST 23
Peak memory 201056 kb
Host smart-fea12c5e-d5d7-40b0-8956-db8daac3eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375502572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2375502572
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.20427906
Short name T470
Test name
Test status
Simulation time 492899568007 ps
CPU time 1174.27 seconds
Started Dec 20 12:49:16 PM PST 23
Finished Dec 20 01:09:51 PM PST 23
Peak memory 200988 kb
Host smart-8e145419-8ced-48f5-8b25-aacc98b1e109
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=20427906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt
_fixed.20427906
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.316780927
Short name T827
Test name
Test status
Simulation time 484199759943 ps
CPU time 548.15 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:59:36 PM PST 23
Peak memory 201020 kb
Host smart-74b384d0-025c-48d6-abf5-a294bea2b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316780927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.316780927
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2961941582
Short name T407
Test name
Test status
Simulation time 328630141701 ps
CPU time 797.54 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 01:03:27 PM PST 23
Peak memory 200928 kb
Host smart-4864384e-e906-44d6-8d5b-60d6017cd3ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961941582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2961941582
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.873733551
Short name T821
Test name
Test status
Simulation time 489283266638 ps
CPU time 1170.47 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 01:09:38 PM PST 23
Peak memory 201024 kb
Host smart-904c86b5-1567-4344-808d-05490f97c4af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873733551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.873733551
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1885233166
Short name T564
Test name
Test status
Simulation time 172771270414 ps
CPU time 94.18 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:51:36 PM PST 23
Peak memory 200960 kb
Host smart-fa431e76-0a77-47da-b548-37a658fcc5e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885233166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1885233166
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2175104213
Short name T651
Test name
Test status
Simulation time 133963898158 ps
CPU time 523.2 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:58:42 PM PST 23
Peak memory 201400 kb
Host smart-0ebfe60f-876c-43ae-8bf4-eb0fc0756430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175104213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2175104213
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3614913596
Short name T437
Test name
Test status
Simulation time 24340364972 ps
CPU time 59.06 seconds
Started Dec 20 12:48:57 PM PST 23
Finished Dec 20 12:50:57 PM PST 23
Peak memory 200616 kb
Host smart-3104cbec-06ea-401a-901a-055502fb5385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614913596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3614913596
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.630082092
Short name T21
Test name
Test status
Simulation time 4148686726 ps
CPU time 10.48 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:50:30 PM PST 23
Peak memory 200876 kb
Host smart-879ebcc0-015f-41d8-95fb-c5ed799dd8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630082092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.630082092
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2103700322
Short name T677
Test name
Test status
Simulation time 5686028930 ps
CPU time 4.18 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 12:50:33 PM PST 23
Peak memory 200560 kb
Host smart-cb335f6b-2548-4e67-bd1c-11f4c5eb5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103700322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2103700322
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1617143128
Short name T140
Test name
Test status
Simulation time 20708558776 ps
CPU time 47.92 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:50:58 PM PST 23
Peak memory 201320 kb
Host smart-bdd81bd6-9e27-4254-bd5f-5ebf1236a958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617143128 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1617143128
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2107255194
Short name T662
Test name
Test status
Simulation time 520372299 ps
CPU time 1.17 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:50:01 PM PST 23
Peak memory 200636 kb
Host smart-27a2cd51-ad9d-4732-b6e4-9402bdec5431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107255194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2107255194
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3745215677
Short name T238
Test name
Test status
Simulation time 328944199751 ps
CPU time 716.1 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 01:02:09 PM PST 23
Peak memory 200868 kb
Host smart-b05d312a-ea7b-4f64-ab67-d6cd5ef3a2f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745215677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3745215677
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.608966687
Short name T602
Test name
Test status
Simulation time 327319232754 ps
CPU time 772.03 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 01:02:58 PM PST 23
Peak memory 200908 kb
Host smart-79e95330-f2ef-4199-bbce-d4c520b13a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608966687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.608966687
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1738481479
Short name T240
Test name
Test status
Simulation time 328838313305 ps
CPU time 202.6 seconds
Started Dec 20 12:49:19 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 201092 kb
Host smart-c263ac24-c6ff-4ea2-85ef-907ac638d85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738481479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1738481479
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1131868280
Short name T691
Test name
Test status
Simulation time 493967097200 ps
CPU time 499.56 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:58:28 PM PST 23
Peak memory 200764 kb
Host smart-8bc3c552-fb53-4ec3-bddf-740d53974f62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131868280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1131868280
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2849413819
Short name T144
Test name
Test status
Simulation time 169140628977 ps
CPU time 101.17 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:52:12 PM PST 23
Peak memory 200972 kb
Host smart-86d04b35-bcce-4f70-9129-22c7496d7c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849413819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2849413819
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3517208115
Short name T408
Test name
Test status
Simulation time 335651691134 ps
CPU time 196.33 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:53:16 PM PST 23
Peak memory 201000 kb
Host smart-7069902d-0001-4e51-bac2-3b700ec6807d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517208115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3517208115
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.214843199
Short name T614
Test name
Test status
Simulation time 161358123206 ps
CPU time 74.94 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:51:26 PM PST 23
Peak memory 200804 kb
Host smart-467e3e1d-019d-450d-9196-d7f18e3aba85
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214843199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.214843199
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.29243706
Short name T593
Test name
Test status
Simulation time 33086412336 ps
CPU time 21.13 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:50:32 PM PST 23
Peak memory 200764 kb
Host smart-54399c5e-29ca-43f2-a4c7-ccde76ee0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29243706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.29243706
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3376377571
Short name T585
Test name
Test status
Simulation time 3315445467 ps
CPU time 2.37 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:50:11 PM PST 23
Peak memory 200544 kb
Host smart-e35e5f56-dfae-4f0f-9dad-a1b7bd7d1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376377571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3376377571
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.399671001
Short name T580
Test name
Test status
Simulation time 5976070444 ps
CPU time 4.27 seconds
Started Dec 20 12:49:30 PM PST 23
Finished Dec 20 12:50:30 PM PST 23
Peak memory 200572 kb
Host smart-ddce1fcb-4c5f-493d-a9f9-190384e390c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399671001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.399671001
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.452697323
Short name T702
Test name
Test status
Simulation time 5408639835 ps
CPU time 3.93 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:50:33 PM PST 23
Peak memory 200756 kb
Host smart-e600e766-b533-4327-9981-140cf0b13f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452697323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
452697323
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3778398675
Short name T91
Test name
Test status
Simulation time 136265465806 ps
CPU time 162.35 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:52:50 PM PST 23
Peak memory 209388 kb
Host smart-6bace3f1-13ad-4cc5-bc8e-50edbec2092c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778398675 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3778398675
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4253719529
Short name T781
Test name
Test status
Simulation time 520628942 ps
CPU time 1.17 seconds
Started Dec 20 12:49:15 PM PST 23
Finished Dec 20 12:50:17 PM PST 23
Peak memory 200480 kb
Host smart-d669f319-4b8c-4b6f-b9b3-390f44491e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253719529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4253719529
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2844213090
Short name T808
Test name
Test status
Simulation time 333123278609 ps
CPU time 97.44 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:51:45 PM PST 23
Peak memory 200708 kb
Host smart-4b5c3945-e834-4290-8449-4e74b4c3ed6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844213090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2844213090
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3268533342
Short name T807
Test name
Test status
Simulation time 396977839194 ps
CPU time 249.16 seconds
Started Dec 20 12:49:21 PM PST 23
Finished Dec 20 12:54:30 PM PST 23
Peak memory 200808 kb
Host smart-b2e74993-e801-4564-8624-b0144d7bf190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268533342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3268533342
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.526905744
Short name T546
Test name
Test status
Simulation time 486068585194 ps
CPU time 313.36 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:55:20 PM PST 23
Peak memory 200796 kb
Host smart-4f9ee252-9da6-49d7-833e-f3d99dcfa3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526905744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.526905744
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2591182495
Short name T673
Test name
Test status
Simulation time 162316476797 ps
CPU time 105.31 seconds
Started Dec 20 12:48:56 PM PST 23
Finished Dec 20 12:51:42 PM PST 23
Peak memory 200924 kb
Host smart-8ece07ca-4470-4dae-a2a7-d32dc5507feb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591182495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2591182495
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3126693801
Short name T267
Test name
Test status
Simulation time 331163883636 ps
CPU time 728.38 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 01:02:17 PM PST 23
Peak memory 201004 kb
Host smart-a706d5a7-851f-4516-b4a8-003ce5e5fca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126693801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3126693801
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3335555139
Short name T710
Test name
Test status
Simulation time 161840649762 ps
CPU time 95.36 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:51:52 PM PST 23
Peak memory 200780 kb
Host smart-3850c5a6-4912-4592-99b4-a437d6aa1e7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335555139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3335555139
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3910762294
Short name T178
Test name
Test status
Simulation time 342196455920 ps
CPU time 179.17 seconds
Started Dec 20 12:49:12 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 200928 kb
Host smart-8412e346-3e9a-45f8-9382-401789afef18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910762294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3910762294
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3642481188
Short name T552
Test name
Test status
Simulation time 488456885351 ps
CPU time 332.59 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:55:41 PM PST 23
Peak memory 200876 kb
Host smart-9962a25d-6541-46e6-8bb8-86a8d9e92aab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642481188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3642481188
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2186002256
Short name T775
Test name
Test status
Simulation time 124186870692 ps
CPU time 404.73 seconds
Started Dec 20 12:49:26 PM PST 23
Finished Dec 20 12:57:08 PM PST 23
Peak memory 201316 kb
Host smart-c4b8c2d8-2950-49c5-9e3f-32ec6f47c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186002256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2186002256
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2609980821
Short name T816
Test name
Test status
Simulation time 40149701067 ps
CPU time 22.54 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:50:33 PM PST 23
Peak memory 200848 kb
Host smart-12394063-fdf3-4ae3-9948-d1dfe6f43efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609980821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2609980821
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1291054605
Short name T757
Test name
Test status
Simulation time 3968029258 ps
CPU time 10.12 seconds
Started Dec 20 12:49:31 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200620 kb
Host smart-9546db1d-e566-45e4-9b82-9d1aa144369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291054605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1291054605
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2626962753
Short name T795
Test name
Test status
Simulation time 5766922275 ps
CPU time 9.09 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:50:21 PM PST 23
Peak memory 200496 kb
Host smart-b6fdf126-2cd9-4c12-97b3-4f3203c84a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626962753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2626962753
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2688189307
Short name T19
Test name
Test status
Simulation time 361187993070 ps
CPU time 110.43 seconds
Started Dec 20 12:49:13 PM PST 23
Finished Dec 20 12:52:04 PM PST 23
Peak memory 200888 kb
Host smart-830f5fa3-e2c4-4334-8ac0-ae1a55a571ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688189307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2688189307
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3317863604
Short name T571
Test name
Test status
Simulation time 161582772981 ps
CPU time 94.16 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:51:44 PM PST 23
Peak memory 209240 kb
Host smart-92fbd50e-04ee-4e76-adb3-bf0ffc851531
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317863604 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3317863604
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2184840370
Short name T497
Test name
Test status
Simulation time 454662405 ps
CPU time 0.78 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:50:09 PM PST 23
Peak memory 200796 kb
Host smart-88facaea-337c-4b82-8782-0e1316f0425a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184840370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2184840370
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.776290362
Short name T117
Test name
Test status
Simulation time 496158196186 ps
CPU time 1052.44 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 01:07:41 PM PST 23
Peak memory 201008 kb
Host smart-4129eb2f-1116-4122-aacc-9cbb1d8f45b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776290362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.776290362
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2103921181
Short name T515
Test name
Test status
Simulation time 327608566872 ps
CPU time 193.18 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:53:25 PM PST 23
Peak memory 200884 kb
Host smart-7a1bb884-1fed-48f1-86b2-9016bc8ffea6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103921181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2103921181
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3433330323
Short name T565
Test name
Test status
Simulation time 160132708922 ps
CPU time 185.71 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:53:22 PM PST 23
Peak memory 200752 kb
Host smart-e1e04364-0a13-43bd-8c63-d1780bc0131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433330323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3433330323
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2178673926
Short name T548
Test name
Test status
Simulation time 164636743821 ps
CPU time 87.32 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:51:40 PM PST 23
Peak memory 200896 kb
Host smart-e3ab1283-2ef8-4ede-9e35-6a563d5168eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178673926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2178673926
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.440456049
Short name T461
Test name
Test status
Simulation time 321692762794 ps
CPU time 343.28 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:56:00 PM PST 23
Peak memory 200900 kb
Host smart-9e991a0b-d7c7-4b1e-b5e8-aa0c327c40dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440456049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.440456049
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3726190769
Short name T557
Test name
Test status
Simulation time 116898657516 ps
CPU time 606.21 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 01:00:15 PM PST 23
Peak memory 201080 kb
Host smart-b2b7a296-69c5-4a15-93a5-1d3276cc5e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726190769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3726190769
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4060793050
Short name T626
Test name
Test status
Simulation time 27177528832 ps
CPU time 11.35 seconds
Started Dec 20 12:48:59 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 200600 kb
Host smart-1421d81d-842b-49a8-b35a-4e2f1e628d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060793050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4060793050
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1368779594
Short name T435
Test name
Test status
Simulation time 4596144453 ps
CPU time 11.29 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 12:50:38 PM PST 23
Peak memory 200756 kb
Host smart-d6d1e7cd-1880-4d60-9ebb-af9f37050506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368779594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1368779594
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3247178999
Short name T462
Test name
Test status
Simulation time 5672654192 ps
CPU time 15.36 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:50:23 PM PST 23
Peak memory 200724 kb
Host smart-38a44ff8-06b9-4f3a-837e-d20f0ff26cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247178999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3247178999
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3715577076
Short name T249
Test name
Test status
Simulation time 361361237685 ps
CPU time 718.92 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 01:02:11 PM PST 23
Peak memory 200948 kb
Host smart-2fdaf038-ee4e-4651-b9f0-b9b2a4c2734b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715577076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3715577076
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3057075980
Short name T705
Test name
Test status
Simulation time 117077447521 ps
CPU time 292.88 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:55:03 PM PST 23
Peak memory 209608 kb
Host smart-f1252128-6e64-43a4-955c-6930478b1c3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057075980 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3057075980
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1244719477
Short name T640
Test name
Test status
Simulation time 358766273 ps
CPU time 0.82 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:50:12 PM PST 23
Peak memory 200612 kb
Host smart-119ca33b-5485-4489-9890-4d3f3c7d1f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244719477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1244719477
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.428406699
Short name T175
Test name
Test status
Simulation time 169424982270 ps
CPU time 80.27 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:51:29 PM PST 23
Peak memory 201024 kb
Host smart-5a445f05-933a-4bf5-9b64-7e4a37bb1622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428406699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.428406699
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4166279698
Short name T225
Test name
Test status
Simulation time 167831046430 ps
CPU time 108.55 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 200952 kb
Host smart-274dbf7b-11c0-4473-a078-c7e40542097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166279698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4166279698
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3723203175
Short name T758
Test name
Test status
Simulation time 161284278765 ps
CPU time 336.92 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:55:48 PM PST 23
Peak memory 200964 kb
Host smart-c66d48ee-5266-4122-a4b1-c87f0a551564
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723203175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3723203175
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3867051890
Short name T544
Test name
Test status
Simulation time 330409790396 ps
CPU time 710.09 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 01:02:11 PM PST 23
Peak memory 201008 kb
Host smart-648bf2af-76a7-4143-a305-8f2d350ff1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867051890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3867051890
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2827865181
Short name T532
Test name
Test status
Simulation time 494114426066 ps
CPU time 587.81 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:59:58 PM PST 23
Peak memory 200924 kb
Host smart-fce4e006-4294-4c3e-8cfb-6fecee87cd5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827865181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2827865181
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1375949155
Short name T216
Test name
Test status
Simulation time 617587020909 ps
CPU time 739.73 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 01:02:30 PM PST 23
Peak memory 200920 kb
Host smart-8dca8aac-30b6-4512-abdf-f2d0ce62a12c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375949155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1375949155
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.117162610
Short name T468
Test name
Test status
Simulation time 337162892028 ps
CPU time 193.17 seconds
Started Dec 20 12:49:31 PM PST 23
Finished Dec 20 12:53:39 PM PST 23
Peak memory 200844 kb
Host smart-d9684fb2-9857-4c00-8747-96c7b3a11e5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117162610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.117162610
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1692129863
Short name T811
Test name
Test status
Simulation time 117849035397 ps
CPU time 648.04 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 01:01:19 PM PST 23
Peak memory 201252 kb
Host smart-763a99a5-4816-4964-bd5c-478640144e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692129863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1692129863
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3031158141
Short name T664
Test name
Test status
Simulation time 25133325507 ps
CPU time 30.36 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:51:00 PM PST 23
Peak memory 200556 kb
Host smart-c092e5e7-11d9-4962-9c97-28c31063814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031158141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3031158141
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1251831987
Short name T829
Test name
Test status
Simulation time 3779619325 ps
CPU time 1.43 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 200652 kb
Host smart-253d6fbc-7d30-439f-b38e-d4dbe71ef7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251831987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1251831987
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.405531268
Short name T438
Test name
Test status
Simulation time 5895137339 ps
CPU time 7.2 seconds
Started Dec 20 12:49:05 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 200668 kb
Host smart-47acbbed-80ef-4467-bc33-8f4fde879538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405531268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.405531268
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.152835832
Short name T190
Test name
Test status
Simulation time 210932741237 ps
CPU time 131.27 seconds
Started Dec 20 12:49:06 PM PST 23
Finished Dec 20 12:52:20 PM PST 23
Peak memory 200692 kb
Host smart-5d536c5d-9468-4c6b-848f-1ecddef4a5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152835832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
152835832
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1927909086
Short name T813
Test name
Test status
Simulation time 424816259 ps
CPU time 1.59 seconds
Started Dec 20 12:49:17 PM PST 23
Finished Dec 20 12:50:19 PM PST 23
Peak memory 200700 kb
Host smart-e2a528cd-fff6-4870-9a42-11f3c0a0e918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927909086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1927909086
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3984571028
Short name T288
Test name
Test status
Simulation time 166028699924 ps
CPU time 209.77 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 200912 kb
Host smart-a3d57cf8-64a5-4c04-8bac-f4aad2cf528d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984571028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3984571028
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1697807312
Short name T776
Test name
Test status
Simulation time 498681444294 ps
CPU time 1002.65 seconds
Started Dec 20 12:49:13 PM PST 23
Finished Dec 20 01:07:00 PM PST 23
Peak memory 200808 kb
Host smart-c1860501-e811-4d93-b3c8-956a953fbc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697807312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1697807312
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2388271816
Short name T477
Test name
Test status
Simulation time 488380128854 ps
CPU time 1028.59 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 01:07:18 PM PST 23
Peak memory 200856 kb
Host smart-9d30421a-63b5-4e58-8c5f-70f7c2759bd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388271816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2388271816
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2201632720
Short name T111
Test name
Test status
Simulation time 329713958349 ps
CPU time 391.56 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 200708 kb
Host smart-a4d5ff34-1614-46a2-af31-18274591cc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201632720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2201632720
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3703498767
Short name T578
Test name
Test status
Simulation time 168540389844 ps
CPU time 58.7 seconds
Started Dec 20 12:49:08 PM PST 23
Finished Dec 20 12:51:09 PM PST 23
Peak memory 201048 kb
Host smart-904ab878-aed1-46a2-943c-7975eec75597
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703498767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3703498767
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3282908834
Short name T287
Test name
Test status
Simulation time 498268980706 ps
CPU time 998.62 seconds
Started Dec 20 12:49:10 PM PST 23
Finished Dec 20 01:06:51 PM PST 23
Peak memory 200892 kb
Host smart-7eb9fb80-44eb-4c7a-942e-9757aaab2c46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282908834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3282908834
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1725806039
Short name T761
Test name
Test status
Simulation time 327625260289 ps
CPU time 193.2 seconds
Started Dec 20 12:49:03 PM PST 23
Finished Dec 20 12:53:18 PM PST 23
Peak memory 200920 kb
Host smart-72516844-a461-46f2-a975-fa2e237d0492
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725806039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1725806039
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3315510760
Short name T661
Test name
Test status
Simulation time 23335797168 ps
CPU time 43.71 seconds
Started Dec 20 12:49:04 PM PST 23
Finished Dec 20 12:50:52 PM PST 23
Peak memory 200560 kb
Host smart-20ff3bda-3ac7-422a-9150-ff62dac4c8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315510760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3315510760
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3850197494
Short name T167
Test name
Test status
Simulation time 3452361548 ps
CPU time 8.84 seconds
Started Dec 20 12:49:07 PM PST 23
Finished Dec 20 12:50:18 PM PST 23
Peak memory 200756 kb
Host smart-bcabaff0-123f-4839-8fa4-0dbc6bfbd3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850197494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3850197494
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2836715524
Short name T18
Test name
Test status
Simulation time 5841997566 ps
CPU time 3.93 seconds
Started Dec 20 12:49:09 PM PST 23
Finished Dec 20 12:50:17 PM PST 23
Peak memory 200748 kb
Host smart-b773fedf-5c76-4574-8aed-b977709a505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836715524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2836715524
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1399791806
Short name T455
Test name
Test status
Simulation time 289154344 ps
CPU time 0.9 seconds
Started Dec 20 12:49:31 PM PST 23
Finished Dec 20 12:50:27 PM PST 23
Peak memory 200716 kb
Host smart-5029c833-5e82-4ca3-912e-14fbff48e83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399791806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1399791806
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.240109234
Short name T14
Test name
Test status
Simulation time 160575988750 ps
CPU time 377.01 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 12:56:49 PM PST 23
Peak memory 201012 kb
Host smart-a734febc-18e8-42d0-8cb2-1643b9765928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240109234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.240109234
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1076451674
Short name T172
Test name
Test status
Simulation time 164443586777 ps
CPU time 104.64 seconds
Started Dec 20 12:49:25 PM PST 23
Finished Dec 20 12:52:07 PM PST 23
Peak memory 200820 kb
Host smart-476a14f2-c4b2-41ee-a136-bb6c58195787
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076451674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1076451674
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2718483590
Short name T799
Test name
Test status
Simulation time 165504767633 ps
CPU time 354.78 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 200944 kb
Host smart-7aba5873-e97f-47b3-a8b1-a9fdf179a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718483590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2718483590
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2567604425
Short name T542
Test name
Test status
Simulation time 329531350521 ps
CPU time 789.22 seconds
Started Dec 20 12:49:23 PM PST 23
Finished Dec 20 01:03:31 PM PST 23
Peak memory 200928 kb
Host smart-5c54689a-ca3d-4eef-88d3-49dcdea25cd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567604425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2567604425
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2888195622
Short name T619
Test name
Test status
Simulation time 161584187675 ps
CPU time 92.07 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:51:54 PM PST 23
Peak memory 200948 kb
Host smart-537def6f-685b-4946-bf52-3356242520ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888195622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2888195622
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3624366352
Short name T353
Test name
Test status
Simulation time 73739893093 ps
CPU time 283.31 seconds
Started Dec 20 12:49:30 PM PST 23
Finished Dec 20 12:55:09 PM PST 23
Peak memory 201268 kb
Host smart-fb98d855-49ef-4960-88c2-354f9385af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624366352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3624366352
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2413068413
Short name T573
Test name
Test status
Simulation time 25541324462 ps
CPU time 28.65 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 12:50:55 PM PST 23
Peak memory 200904 kb
Host smart-b8ff4fa7-a1cd-4b73-bf3f-b8cc0ba34388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413068413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2413068413
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.686844301
Short name T690
Test name
Test status
Simulation time 4462238765 ps
CPU time 2.21 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:50:25 PM PST 23
Peak memory 200780 kb
Host smart-bdcc249e-3fb7-4a94-afd9-a322f11b9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686844301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.686844301
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2069478932
Short name T785
Test name
Test status
Simulation time 5703741259 ps
CPU time 8.42 seconds
Started Dec 20 12:49:22 PM PST 23
Finished Dec 20 12:50:30 PM PST 23
Peak memory 200792 kb
Host smart-706dea71-0c53-4f30-99bd-89d4ec6e9598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069478932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2069478932
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.425171524
Short name T572
Test name
Test status
Simulation time 173479064443 ps
CPU time 103.23 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 12:52:15 PM PST 23
Peak memory 200884 kb
Host smart-c3c019e9-4671-48f0-a028-cf27264a6f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425171524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
425171524
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3406560482
Short name T641
Test name
Test status
Simulation time 520930849 ps
CPU time 1.53 seconds
Started Dec 20 12:49:22 PM PST 23
Finished Dec 20 12:50:23 PM PST 23
Peak memory 200772 kb
Host smart-35eb4af5-971b-442b-a66b-69af2505c823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406560482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3406560482
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.4080561618
Short name T219
Test name
Test status
Simulation time 494147094780 ps
CPU time 207.87 seconds
Started Dec 20 12:49:20 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 201012 kb
Host smart-51ff125e-3115-4c4a-895a-8a77e8b1d6df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080561618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.4080561618
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2422513732
Short name T337
Test name
Test status
Simulation time 162985441069 ps
CPU time 43.58 seconds
Started Dec 20 12:49:28 PM PST 23
Finished Dec 20 12:51:09 PM PST 23
Peak memory 200952 kb
Host smart-0367c082-c56b-4dfb-b46b-40dbfee82d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422513732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2422513732
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1261461311
Short name T558
Test name
Test status
Simulation time 494183261469 ps
CPU time 300.66 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:55:23 PM PST 23
Peak memory 201032 kb
Host smart-135ca9f3-1a86-4208-bc92-e1319b18f07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261461311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1261461311
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2900264172
Short name T798
Test name
Test status
Simulation time 494393378883 ps
CPU time 834.78 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 01:04:22 PM PST 23
Peak memory 200912 kb
Host smart-f4855ceb-680a-41d1-802e-1767aa35ccf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900264172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2900264172
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2841367360
Short name T321
Test name
Test status
Simulation time 326782277695 ps
CPU time 355.13 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:56:27 PM PST 23
Peak memory 200928 kb
Host smart-23c4acda-5358-4e38-9a30-1fd017350603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841367360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2841367360
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2112162668
Short name T422
Test name
Test status
Simulation time 164650459757 ps
CPU time 30.15 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:51:02 PM PST 23
Peak memory 200840 kb
Host smart-1673a268-315f-4e2b-a6f2-c01b91d1ea05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112162668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2112162668
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1176989460
Short name T303
Test name
Test status
Simulation time 168566916147 ps
CPU time 324.65 seconds
Started Dec 20 12:49:31 PM PST 23
Finished Dec 20 12:55:51 PM PST 23
Peak memory 200940 kb
Host smart-5d30f9a8-f4b8-45ee-83e6-5529cb9eba7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176989460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1176989460
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1426838868
Short name T425
Test name
Test status
Simulation time 498161435750 ps
CPU time 310.52 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 200808 kb
Host smart-7c7073a8-c5b0-46b3-84ed-5e97f30256a7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426838868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1426838868
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.643595235
Short name T561
Test name
Test status
Simulation time 123582499262 ps
CPU time 646.26 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 01:01:14 PM PST 23
Peak memory 201396 kb
Host smart-43792906-6c77-481d-9f0f-601e15e5ccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643595235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.643595235
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3658554631
Short name T401
Test name
Test status
Simulation time 40533844562 ps
CPU time 43.72 seconds
Started Dec 20 12:49:26 PM PST 23
Finished Dec 20 12:51:07 PM PST 23
Peak memory 200564 kb
Host smart-7263ac55-d4e5-45fd-a5e6-b1001bdcd3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658554631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3658554631
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.655456466
Short name T832
Test name
Test status
Simulation time 3862162523 ps
CPU time 1.25 seconds
Started Dec 20 12:49:27 PM PST 23
Finished Dec 20 12:50:25 PM PST 23
Peak memory 200724 kb
Host smart-a9d90450-256e-4f67-905e-2e5d1f5bdbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655456466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.655456466
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2190123255
Short name T533
Test name
Test status
Simulation time 5672015517 ps
CPU time 4.21 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:50:34 PM PST 23
Peak memory 200808 kb
Host smart-3e271a9e-9e57-4886-aaa1-1a8358da7371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190123255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2190123255
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1168341292
Short name T102
Test name
Test status
Simulation time 180974333252 ps
CPU time 437.55 seconds
Started Dec 20 12:49:31 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 201092 kb
Host smart-63f47ad3-503a-4da6-8173-d890de332ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168341292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1168341292
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3137235681
Short name T503
Test name
Test status
Simulation time 103598219122 ps
CPU time 272.13 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:54:58 PM PST 23
Peak memory 209644 kb
Host smart-22e9d692-2e19-4fd8-8dda-ebf4d1a11141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137235681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3137235681
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3760146612
Short name T846
Test name
Test status
Simulation time 279489994 ps
CPU time 1.27 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:50:23 PM PST 23
Peak memory 200724 kb
Host smart-789016a4-7042-4896-bb8e-29955f7a2002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760146612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3760146612
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4022880742
Short name T726
Test name
Test status
Simulation time 500263206981 ps
CPU time 1099.66 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 01:08:49 PM PST 23
Peak memory 200784 kb
Host smart-eda5d2a3-73b4-4718-990b-2be65a96be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022880742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4022880742
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3392653478
Short name T124
Test name
Test status
Simulation time 327789217596 ps
CPU time 733.33 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 01:02:42 PM PST 23
Peak memory 200880 kb
Host smart-069ca4ff-6143-4a23-a424-480558b935aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392653478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3392653478
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.75835318
Short name T243
Test name
Test status
Simulation time 486614461453 ps
CPU time 1086.5 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:08:41 PM PST 23
Peak memory 200896 kb
Host smart-efe7ac8d-8819-4b2c-a871-e7a7b91cefc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=75835318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt
_fixed.75835318
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1245876067
Short name T143
Test name
Test status
Simulation time 338844435319 ps
CPU time 78.3 seconds
Started Dec 20 12:49:23 PM PST 23
Finished Dec 20 12:51:40 PM PST 23
Peak memory 200736 kb
Host smart-ff00f8fd-b252-4f55-841e-13d8dff3aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245876067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1245876067
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2690553948
Short name T611
Test name
Test status
Simulation time 164585811537 ps
CPU time 192.78 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 200920 kb
Host smart-c721ec6c-2bee-40f4-b89f-c260db3b5cbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690553948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2690553948
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1817111720
Short name T101
Test name
Test status
Simulation time 495844373922 ps
CPU time 278.3 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 200948 kb
Host smart-1d1a9710-3708-4ad2-99b2-2cc79e62e6e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817111720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1817111720
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2021337117
Short name T629
Test name
Test status
Simulation time 491298084600 ps
CPU time 535.51 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:59:21 PM PST 23
Peak memory 201040 kb
Host smart-e4d03665-e79a-49e5-b4f5-d0b4ca6fa598
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021337117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2021337117
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2751484311
Short name T350
Test name
Test status
Simulation time 103512354752 ps
CPU time 358.5 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:56:28 PM PST 23
Peak memory 201388 kb
Host smart-1f77d122-41bb-4530-9714-fe97432c29d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751484311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2751484311
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.317240804
Short name T431
Test name
Test status
Simulation time 22846525547 ps
CPU time 54.15 seconds
Started Dec 20 12:49:27 PM PST 23
Finished Dec 20 12:51:18 PM PST 23
Peak memory 200848 kb
Host smart-869b6054-fdbe-48aa-81c3-947ca855ef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317240804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.317240804
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2477979906
Short name T432
Test name
Test status
Simulation time 3247661738 ps
CPU time 2.46 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:50:28 PM PST 23
Peak memory 200488 kb
Host smart-531126c8-8bb7-48bf-89a4-fbb2b037e5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477979906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2477979906
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2183028623
Short name T421
Test name
Test status
Simulation time 5881981249 ps
CPU time 4.34 seconds
Started Dec 20 12:49:45 PM PST 23
Finished Dec 20 12:50:39 PM PST 23
Peak memory 200740 kb
Host smart-0ff71dd6-6cc7-44e6-a388-5bbc788c17ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183028623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2183028623
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.330250248
Short name T289
Test name
Test status
Simulation time 628348693855 ps
CPU time 820.91 seconds
Started Dec 20 12:49:28 PM PST 23
Finished Dec 20 01:04:06 PM PST 23
Peak memory 209616 kb
Host smart-97b7a86d-4744-4d4c-a59f-41e733faad78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330250248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
330250248
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.62403106
Short name T650
Test name
Test status
Simulation time 186411850093 ps
CPU time 93.87 seconds
Started Dec 20 12:49:26 PM PST 23
Finished Dec 20 12:51:57 PM PST 23
Peak memory 210652 kb
Host smart-2c4ed0fa-1411-46aa-9150-ed95aa9f7872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62403106 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.62403106
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4146318878
Short name T463
Test name
Test status
Simulation time 337791849 ps
CPU time 0.98 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:50:28 PM PST 23
Peak memory 200672 kb
Host smart-279e632d-2fa0-40f8-901a-b26d1c194aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146318878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4146318878
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2605200379
Short name T276
Test name
Test status
Simulation time 477969035691 ps
CPU time 96.61 seconds
Started Dec 20 12:49:32 PM PST 23
Finished Dec 20 12:52:03 PM PST 23
Peak memory 200700 kb
Host smart-38cf599b-7235-4ec7-80aa-8f3bde89023c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605200379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2605200379
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2425460914
Short name T290
Test name
Test status
Simulation time 166463554245 ps
CPU time 369.89 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:56:43 PM PST 23
Peak memory 200992 kb
Host smart-64213fdc-0046-459d-98a5-e1706f5a6dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425460914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2425460914
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3517828872
Short name T681
Test name
Test status
Simulation time 324353341856 ps
CPU time 191.24 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:53:41 PM PST 23
Peak memory 200980 kb
Host smart-c417e494-7c4b-4400-885a-f89d3114522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517828872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3517828872
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.498221646
Short name T752
Test name
Test status
Simulation time 160623859342 ps
CPU time 342.37 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:56:12 PM PST 23
Peak memory 200912 kb
Host smart-7771d25f-b5ea-481e-ba25-594b32bab142
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=498221646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.498221646
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1959005463
Short name T733
Test name
Test status
Simulation time 493412344534 ps
CPU time 165.82 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:53:08 PM PST 23
Peak memory 200952 kb
Host smart-4263815c-c8d8-41de-91ca-0dc4fd83b80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959005463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1959005463
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3623057998
Short name T184
Test name
Test status
Simulation time 490377901137 ps
CPU time 272.98 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:55:03 PM PST 23
Peak memory 200916 kb
Host smart-0a11dc2b-2b0e-41e1-9ba1-4fd64da8ceb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623057998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3623057998
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3504132393
Short name T499
Test name
Test status
Simulation time 497790440206 ps
CPU time 1241.16 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 01:11:07 PM PST 23
Peak memory 200956 kb
Host smart-0f18b886-b24e-4718-976d-90e192af3128
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504132393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3504132393
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1065253601
Short name T210
Test name
Test status
Simulation time 102683425879 ps
CPU time 347.53 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 12:56:16 PM PST 23
Peak memory 201432 kb
Host smart-0047ded7-914d-4344-a643-3cc724d21054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065253601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1065253601
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4197421126
Short name T492
Test name
Test status
Simulation time 32274753146 ps
CPU time 39.08 seconds
Started Dec 20 12:49:23 PM PST 23
Finished Dec 20 12:51:01 PM PST 23
Peak memory 200808 kb
Host smart-52dec442-9688-40ea-99a4-1431741e3b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197421126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4197421126
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3514655351
Short name T665
Test name
Test status
Simulation time 3716546527 ps
CPU time 5.01 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 12:50:41 PM PST 23
Peak memory 200780 kb
Host smart-10dcb604-46dd-4978-a530-bf03094cc804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514655351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3514655351
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1358827899
Short name T643
Test name
Test status
Simulation time 5609111389 ps
CPU time 5.92 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:50:34 PM PST 23
Peak memory 200700 kb
Host smart-358344ca-c8df-47cf-b008-e0d48f11cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358827899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1358827899
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.595120845
Short name T837
Test name
Test status
Simulation time 332499079164 ps
CPU time 238.4 seconds
Started Dec 20 12:49:24 PM PST 23
Finished Dec 20 12:54:21 PM PST 23
Peak memory 200948 kb
Host smart-49bcf83f-8487-48e0-86c9-0b28a620a77e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595120845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
595120845
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.577078062
Short name T688
Test name
Test status
Simulation time 430892521 ps
CPU time 0.66 seconds
Started Dec 20 12:47:35 PM PST 23
Finished Dec 20 12:48:55 PM PST 23
Peak memory 200680 kb
Host smart-82a610d6-6469-4417-956b-7fb73d62cb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577078062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.577078062
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2524506609
Short name T105
Test name
Test status
Simulation time 325512176222 ps
CPU time 378.28 seconds
Started Dec 20 12:47:22 PM PST 23
Finished Dec 20 12:54:45 PM PST 23
Peak memory 200972 kb
Host smart-72e19427-08d8-427a-80e0-324d03a75189
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524506609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2524506609
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.512372894
Short name T239
Test name
Test status
Simulation time 164753364940 ps
CPU time 181.92 seconds
Started Dec 20 12:47:10 PM PST 23
Finished Dec 20 12:51:00 PM PST 23
Peak memory 201024 kb
Host smart-f6211e4a-f029-4e83-acfa-3c624c2df867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512372894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.512372894
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.433798736
Short name T696
Test name
Test status
Simulation time 500140573504 ps
CPU time 68.97 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:49:24 PM PST 23
Peak memory 200836 kb
Host smart-552ff10c-47cc-45a6-b3ab-52d3f8cf3b8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=433798736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.433798736
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2314113641
Short name T645
Test name
Test status
Simulation time 327012020680 ps
CPU time 769.82 seconds
Started Dec 20 12:47:55 PM PST 23
Finished Dec 20 01:02:23 PM PST 23
Peak memory 201024 kb
Host smart-c0893fc8-cc30-4e4d-8c7d-7a6aedb4cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314113641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2314113641
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4275596830
Short name T556
Test name
Test status
Simulation time 327086391149 ps
CPU time 188.02 seconds
Started Dec 20 12:46:29 PM PST 23
Finished Dec 20 12:50:00 PM PST 23
Peak memory 200844 kb
Host smart-fa7d9faa-2099-4326-9222-578e168abeee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275596830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4275596830
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2834821243
Short name T162
Test name
Test status
Simulation time 498486564464 ps
CPU time 289.56 seconds
Started Dec 20 12:47:25 PM PST 23
Finished Dec 20 12:53:23 PM PST 23
Peak memory 200792 kb
Host smart-020355da-f918-4b46-99c0-bb6bcb218a03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834821243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2834821243
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2359683921
Short name T756
Test name
Test status
Simulation time 165246713065 ps
CPU time 400.53 seconds
Started Dec 20 12:47:58 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 200832 kb
Host smart-8477a86c-a8e1-4bfd-8920-d8facfa39a42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359683921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2359683921
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2151050431
Short name T345
Test name
Test status
Simulation time 108221826278 ps
CPU time 648 seconds
Started Dec 20 12:48:16 PM PST 23
Finished Dec 20 01:00:37 PM PST 23
Peak memory 201192 kb
Host smart-0d69932b-6ffb-4fe9-80b9-ef00e3d22294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151050431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2151050431
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.232719546
Short name T657
Test name
Test status
Simulation time 26518703485 ps
CPU time 62.7 seconds
Started Dec 20 12:47:53 PM PST 23
Finished Dec 20 12:50:14 PM PST 23
Peak memory 200860 kb
Host smart-cee05504-718e-4181-a5f4-5b52c8b041eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232719546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.232719546
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1552523377
Short name T760
Test name
Test status
Simulation time 4873717102 ps
CPU time 2.89 seconds
Started Dec 20 12:47:20 PM PST 23
Finished Dec 20 12:48:23 PM PST 23
Peak memory 200820 kb
Host smart-2660a780-3890-4f7d-8aff-b775bdd9343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552523377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1552523377
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.401941455
Short name T45
Test name
Test status
Simulation time 3898261329 ps
CPU time 3.47 seconds
Started Dec 20 12:47:50 PM PST 23
Finished Dec 20 12:49:09 PM PST 23
Peak memory 216160 kb
Host smart-fc6a56d6-9ec2-4916-9c30-1bb39029a41f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401941455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.401941455
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1466819852
Short name T559
Test name
Test status
Simulation time 10753144165 ps
CPU time 46.27 seconds
Started Dec 20 12:47:14 PM PST 23
Finished Dec 20 12:48:52 PM PST 23
Peak memory 209808 kb
Host smart-2f5bfc21-d7be-46ce-bdbd-58804f1873a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466819852 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1466819852
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2670764577
Short name T440
Test name
Test status
Simulation time 499073333 ps
CPU time 0.87 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:50:31 PM PST 23
Peak memory 200732 kb
Host smart-cc1c4acc-be59-4170-9d8c-b225d2e47357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670764577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2670764577
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2532320676
Short name T792
Test name
Test status
Simulation time 328634169588 ps
CPU time 778.22 seconds
Started Dec 20 12:49:55 PM PST 23
Finished Dec 20 01:03:40 PM PST 23
Peak memory 200740 kb
Host smart-9372d16c-578d-4711-9993-5d9f68773958
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532320676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2532320676
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4270192619
Short name T232
Test name
Test status
Simulation time 496609964545 ps
CPU time 188.09 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 201136 kb
Host smart-0f89decf-aee5-4ade-aa2b-f8fcb8306185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270192619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4270192619
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3619891133
Short name T129
Test name
Test status
Simulation time 164770323304 ps
CPU time 99.31 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:52:13 PM PST 23
Peak memory 201028 kb
Host smart-46da28cf-dd62-46fe-a7ca-4c9ef77bd451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619891133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3619891133
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3667755130
Short name T764
Test name
Test status
Simulation time 492131426412 ps
CPU time 553.64 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 12:59:49 PM PST 23
Peak memory 200872 kb
Host smart-96a75ddb-413b-411d-91d8-f1b14cda22c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667755130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3667755130
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3484519491
Short name T826
Test name
Test status
Simulation time 166875533587 ps
CPU time 362.27 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:56:32 PM PST 23
Peak memory 200816 kb
Host smart-e8f16a1e-57f2-4896-ae1a-189c32e01e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484519491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3484519491
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2224898706
Short name T541
Test name
Test status
Simulation time 493007935237 ps
CPU time 248.92 seconds
Started Dec 20 12:49:35 PM PST 23
Finished Dec 20 12:54:38 PM PST 23
Peak memory 200904 kb
Host smart-73692372-a295-4907-923f-5f0da759c65e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224898706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2224898706
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2783011772
Short name T666
Test name
Test status
Simulation time 162439417314 ps
CPU time 403.66 seconds
Started Dec 20 12:49:35 PM PST 23
Finished Dec 20 12:57:13 PM PST 23
Peak memory 201000 kb
Host smart-34e89318-78b5-4e8d-b104-2d770dee1aed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783011772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2783011772
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4032991034
Short name T748
Test name
Test status
Simulation time 72125873825 ps
CPU time 376.62 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 201308 kb
Host smart-0d449491-6a10-40a7-baa9-44dcb78c3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032991034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4032991034
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2773208998
Short name T820
Test name
Test status
Simulation time 40877171171 ps
CPU time 18.16 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:50:50 PM PST 23
Peak memory 200672 kb
Host smart-ed570ac2-9dbc-481d-9bc5-e52aa122c395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773208998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2773208998
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2498051194
Short name T642
Test name
Test status
Simulation time 3011453687 ps
CPU time 8.23 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:50:40 PM PST 23
Peak memory 200872 kb
Host smart-5d01df8f-30d7-4ddb-a0bd-a45ee5cfbfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498051194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2498051194
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1487037780
Short name T656
Test name
Test status
Simulation time 5719630794 ps
CPU time 4.06 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:50:31 PM PST 23
Peak memory 200828 kb
Host smart-75b69c3a-facf-4589-bfc2-767c59d30ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487037780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1487037780
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2467529045
Short name T274
Test name
Test status
Simulation time 333672713335 ps
CPU time 384.55 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:56:57 PM PST 23
Peak memory 201008 kb
Host smart-a889947a-a8e5-4ef2-9ddc-cf7e40e7e7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467529045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2467529045
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.586805204
Short name T433
Test name
Test status
Simulation time 436583784 ps
CPU time 0.73 seconds
Started Dec 20 12:49:28 PM PST 23
Finished Dec 20 12:50:26 PM PST 23
Peak memory 200736 kb
Host smart-f6f03e19-bcd1-4074-905d-2cf130dc2e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586805204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.586805204
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2420178359
Short name T762
Test name
Test status
Simulation time 334334537094 ps
CPU time 203.02 seconds
Started Dec 20 12:49:50 PM PST 23
Finished Dec 20 12:54:01 PM PST 23
Peak memory 200896 kb
Host smart-d5817172-83c0-4687-8847-13d148b1adc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420178359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2420178359
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2537946496
Short name T112
Test name
Test status
Simulation time 327525691809 ps
CPU time 211.72 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:54:04 PM PST 23
Peak memory 200876 kb
Host smart-b7cdb4cf-46be-41e9-85c8-3630bf230b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537946496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2537946496
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.140362305
Short name T637
Test name
Test status
Simulation time 498626596002 ps
CPU time 1126.28 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 01:09:20 PM PST 23
Peak memory 201020 kb
Host smart-aaeaf8b8-ec2e-4d79-bebf-ccf5bcddb60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140362305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.140362305
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2946100028
Short name T772
Test name
Test status
Simulation time 489562633816 ps
CPU time 1123.83 seconds
Started Dec 20 12:49:57 PM PST 23
Finished Dec 20 01:09:26 PM PST 23
Peak memory 201072 kb
Host smart-1f7001f2-f711-4c84-83c9-5c27959c6077
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946100028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2946100028
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2301513688
Short name T109
Test name
Test status
Simulation time 488977164928 ps
CPU time 304.03 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 12:55:40 PM PST 23
Peak memory 200708 kb
Host smart-eab2e7eb-cea4-43b1-a23a-59990c985c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301513688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2301513688
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2900699074
Short name T106
Test name
Test status
Simulation time 166742455163 ps
CPU time 53.62 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:51:27 PM PST 23
Peak memory 200948 kb
Host smart-28ad5366-445a-4bab-8ed7-54cd448c69df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900699074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2900699074
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1285743549
Short name T652
Test name
Test status
Simulation time 491896339576 ps
CPU time 1216.97 seconds
Started Dec 20 12:49:50 PM PST 23
Finished Dec 20 01:10:55 PM PST 23
Peak memory 200968 kb
Host smart-aec3127e-3639-4316-8b69-5dbea1797a92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285743549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1285743549
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1118982943
Short name T718
Test name
Test status
Simulation time 135237118405 ps
CPU time 671.58 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:01:46 PM PST 23
Peak memory 200480 kb
Host smart-34d98d31-b41e-4c50-b85e-56fa85ff2fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118982943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1118982943
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3254265693
Short name T466
Test name
Test status
Simulation time 38350699874 ps
CPU time 75.23 seconds
Started Dec 20 12:49:49 PM PST 23
Finished Dec 20 12:51:52 PM PST 23
Peak memory 200796 kb
Host smart-08da6c84-310e-4aba-9870-d721ecdbe771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254265693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3254265693
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1295012990
Short name T58
Test name
Test status
Simulation time 3110001470 ps
CPU time 3.79 seconds
Started Dec 20 12:49:49 PM PST 23
Finished Dec 20 12:50:41 PM PST 23
Peak memory 200884 kb
Host smart-d33bbba6-9091-4fc8-b9e3-437458fbb639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295012990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1295012990
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1160814721
Short name T699
Test name
Test status
Simulation time 5801547779 ps
CPU time 8.09 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:50:38 PM PST 23
Peak memory 200568 kb
Host smart-0646ac63-19ea-4220-9559-142b6ab51bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160814721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1160814721
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2403369147
Short name T226
Test name
Test status
Simulation time 58277047491 ps
CPU time 124.07 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:52:30 PM PST 23
Peak memory 200844 kb
Host smart-03d24f42-9331-4c3d-8a93-f58990bdcdf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403369147 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2403369147
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1663141117
Short name T663
Test name
Test status
Simulation time 463988934 ps
CPU time 1.61 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:50:29 PM PST 23
Peak memory 200716 kb
Host smart-c5c8c235-87a7-4bb7-8134-492d569e197e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663141117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1663141117
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3946767198
Short name T743
Test name
Test status
Simulation time 329821533981 ps
CPU time 196.99 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 12:53:48 PM PST 23
Peak memory 200956 kb
Host smart-3383d122-4c79-4fad-b188-09fad030ae31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946767198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3946767198
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1171962041
Short name T336
Test name
Test status
Simulation time 165186429466 ps
CPU time 391.75 seconds
Started Dec 20 12:49:21 PM PST 23
Finished Dec 20 12:56:52 PM PST 23
Peak memory 200776 kb
Host smart-cd1c0c61-3434-45a0-b44f-4347625bcaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171962041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1171962041
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1805619185
Short name T473
Test name
Test status
Simulation time 328715902253 ps
CPU time 177.96 seconds
Started Dec 20 12:49:17 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 200968 kb
Host smart-0a0552f2-bbe7-4c61-83dc-ff2260f12b5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805619185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1805619185
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2458835508
Short name T471
Test name
Test status
Simulation time 162409229716 ps
CPU time 381.03 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 200916 kb
Host smart-7c3c032c-aa95-4a1e-bad8-cf22c771b4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458835508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2458835508
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2845798259
Short name T409
Test name
Test status
Simulation time 329740315353 ps
CPU time 761.1 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 01:03:07 PM PST 23
Peak memory 200768 kb
Host smart-9439c660-83f1-4830-9e06-5b2307ba1c48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845798259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2845798259
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2103632573
Short name T720
Test name
Test status
Simulation time 165962092978 ps
CPU time 103.02 seconds
Started Dec 20 12:49:28 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 200832 kb
Host smart-aeb0660f-c732-4672-84ab-8e742e0bb313
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103632573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2103632573
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1631903217
Short name T234
Test name
Test status
Simulation time 330417792205 ps
CPU time 719.21 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 01:02:25 PM PST 23
Peak memory 200888 kb
Host smart-6eba4f90-7f42-455d-9988-1bdb01bff4cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631903217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1631903217
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.706358507
Short name T346
Test name
Test status
Simulation time 86689052782 ps
CPU time 446.61 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:57:52 PM PST 23
Peak memory 201400 kb
Host smart-02f5f8c4-05c2-4826-b637-0eb9abcc9c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706358507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.706358507
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1696021339
Short name T780
Test name
Test status
Simulation time 46973611972 ps
CPU time 16.71 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:50:42 PM PST 23
Peak memory 200760 kb
Host smart-083fa37c-47fc-4e5c-9b5d-9ecc9b5b6f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696021339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1696021339
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1473184468
Short name T597
Test name
Test status
Simulation time 5056008711 ps
CPU time 3.82 seconds
Started Dec 20 12:49:29 PM PST 23
Finished Dec 20 12:50:29 PM PST 23
Peak memory 200812 kb
Host smart-3df84fd9-7966-4c3b-bb40-3cff5491ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473184468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1473184468
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3791211554
Short name T678
Test name
Test status
Simulation time 5606050194 ps
CPU time 8.45 seconds
Started Dec 20 12:49:27 PM PST 23
Finished Dec 20 12:50:32 PM PST 23
Peak memory 200688 kb
Host smart-0b2fb166-5c96-4a6e-a99d-38947178f489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791211554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3791211554
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.749453316
Short name T130
Test name
Test status
Simulation time 570518798128 ps
CPU time 1014.34 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:07:29 PM PST 23
Peak memory 200960 kb
Host smart-b27a2f71-47e8-4899-82a9-280c1af4361b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749453316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
749453316
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2720189877
Short name T306
Test name
Test status
Simulation time 274931506987 ps
CPU time 275.74 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 12:55:05 PM PST 23
Peak memory 209644 kb
Host smart-07864eaf-0ce4-46c5-b3da-ceec8e2ef9b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720189877 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2720189877
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3883421753
Short name T579
Test name
Test status
Simulation time 358037147 ps
CPU time 1.37 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200776 kb
Host smart-2a294065-6a25-4aa6-9bfe-9f2748b15efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883421753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3883421753
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1806599797
Short name T300
Test name
Test status
Simulation time 163187765596 ps
CPU time 376.21 seconds
Started Dec 20 12:49:35 PM PST 23
Finished Dec 20 12:56:45 PM PST 23
Peak memory 200692 kb
Host smart-baea6b09-c6e5-4b2b-bf17-07155c609c7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806599797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1806599797
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2803269275
Short name T508
Test name
Test status
Simulation time 495563499914 ps
CPU time 1082.94 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 01:08:36 PM PST 23
Peak memory 200720 kb
Host smart-1f177a34-0d81-41a6-88b1-0718440f169f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803269275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2803269275
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3724755195
Short name T135
Test name
Test status
Simulation time 165725948735 ps
CPU time 380.95 seconds
Started Dec 20 12:49:31 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 200920 kb
Host smart-f34c9875-4b79-4a57-b831-e6710e05e235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724755195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3724755195
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2522689154
Short name T429
Test name
Test status
Simulation time 493654074282 ps
CPU time 1180.88 seconds
Started Dec 20 12:49:25 PM PST 23
Finished Dec 20 01:10:04 PM PST 23
Peak memory 201048 kb
Host smart-ce3db90c-3154-4078-9ebf-216ffb52bb61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522689154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2522689154
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3714916669
Short name T98
Test name
Test status
Simulation time 336710638988 ps
CPU time 809.08 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:04:03 PM PST 23
Peak memory 200960 kb
Host smart-07705bc5-4692-4e97-ab8f-9870fefbd893
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714916669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3714916669
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2370538510
Short name T612
Test name
Test status
Simulation time 164216901374 ps
CPU time 376.94 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 200996 kb
Host smart-d4b8067b-d0ca-4af9-b57a-2e751d157044
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370538510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2370538510
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3793848569
Short name T734
Test name
Test status
Simulation time 133845789462 ps
CPU time 560.21 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:59:51 PM PST 23
Peak memory 201404 kb
Host smart-69d0d4d4-29b8-4c38-90e6-cf8969b65e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793848569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3793848569
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2245201200
Short name T854
Test name
Test status
Simulation time 30292023852 ps
CPU time 71.45 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:51:44 PM PST 23
Peak memory 200600 kb
Host smart-95909913-d678-4e65-b58e-1a29e6426301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245201200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2245201200
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.725887168
Short name T92
Test name
Test status
Simulation time 3364856040 ps
CPU time 3.01 seconds
Started Dec 20 12:49:45 PM PST 23
Finished Dec 20 12:50:38 PM PST 23
Peak memory 200848 kb
Host smart-a2e5bf22-a0f2-47b0-94a9-727c2f1cd193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725887168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.725887168
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2072484342
Short name T670
Test name
Test status
Simulation time 5638508841 ps
CPU time 7.12 seconds
Started Dec 20 12:49:27 PM PST 23
Finished Dec 20 12:50:31 PM PST 23
Peak memory 200760 kb
Host smart-8737d3e5-0ddc-4c11-9379-99b6db7a0b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072484342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2072484342
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2279469280
Short name T494
Test name
Test status
Simulation time 1018140647 ps
CPU time 2.89 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200464 kb
Host smart-8eb7e05b-a7dd-432b-a375-dd39b3740f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279469280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2279469280
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.4207334657
Short name T608
Test name
Test status
Simulation time 494457868 ps
CPU time 0.85 seconds
Started Dec 20 12:49:46 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200488 kb
Host smart-87d47a60-7c06-4980-a2ac-4c630b0741be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207334657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4207334657
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2087353564
Short name T182
Test name
Test status
Simulation time 497838448547 ps
CPU time 748.49 seconds
Started Dec 20 12:49:54 PM PST 23
Finished Dec 20 01:03:08 PM PST 23
Peak memory 200640 kb
Host smart-fa308e91-14b9-454f-9553-8d602f51eac2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087353564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2087353564
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.337831467
Short name T800
Test name
Test status
Simulation time 181048118324 ps
CPU time 40.84 seconds
Started Dec 20 12:49:53 PM PST 23
Finished Dec 20 12:51:20 PM PST 23
Peak memory 200896 kb
Host smart-50c48ab9-7851-4a66-b05b-fe1ac28c3394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337831467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.337831467
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2007255113
Short name T754
Test name
Test status
Simulation time 492518008263 ps
CPU time 538.31 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:59:26 PM PST 23
Peak memory 200940 kb
Host smart-54c7fbdd-9157-40fa-bda2-3bd3a7f40af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007255113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2007255113
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.99905496
Short name T535
Test name
Test status
Simulation time 164368507069 ps
CPU time 86.55 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:51:59 PM PST 23
Peak memory 200868 kb
Host smart-5bb46633-1fb0-424a-8a13-01b952cbc9c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=99905496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt
_fixed.99905496
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3419523570
Short name T286
Test name
Test status
Simulation time 335349772094 ps
CPU time 808.31 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 01:04:00 PM PST 23
Peak memory 201048 kb
Host smart-50655fea-e40d-40e1-b8f8-1566ec4467f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419523570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3419523570
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1436286717
Short name T454
Test name
Test status
Simulation time 163736076132 ps
CPU time 93.21 seconds
Started Dec 20 12:49:46 PM PST 23
Finished Dec 20 12:52:08 PM PST 23
Peak memory 201116 kb
Host smart-617251a5-6cd9-45f3-bdd3-36e0e24634f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436286717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1436286717
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.679454451
Short name T252
Test name
Test status
Simulation time 166179106233 ps
CPU time 91.25 seconds
Started Dec 20 12:49:50 PM PST 23
Finished Dec 20 12:52:09 PM PST 23
Peak memory 200840 kb
Host smart-5a325564-f3ab-4888-8d77-49dc8c89e19d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679454451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.679454451
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.892972024
Short name T474
Test name
Test status
Simulation time 492688342738 ps
CPU time 1062.34 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 01:08:15 PM PST 23
Peak memory 200808 kb
Host smart-bfea9be9-f614-431d-8f1a-063c797c5ab7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892972024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.892972024
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.347406801
Short name T707
Test name
Test status
Simulation time 90623182407 ps
CPU time 365.35 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 201396 kb
Host smart-8c1f7519-605b-47ca-995e-f411964817b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347406801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.347406801
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2545990055
Short name T653
Test name
Test status
Simulation time 34984892772 ps
CPU time 78.26 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:51:53 PM PST 23
Peak memory 200092 kb
Host smart-8383f916-5f36-4580-ad34-5d92cb7ebf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545990055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2545990055
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3213067766
Short name T404
Test name
Test status
Simulation time 3160129854 ps
CPU time 4.36 seconds
Started Dec 20 12:49:45 PM PST 23
Finished Dec 20 12:50:39 PM PST 23
Peak memory 200692 kb
Host smart-33ef5605-1973-4516-95cc-8ea8f6149423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213067766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3213067766
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1830171893
Short name T599
Test name
Test status
Simulation time 5916292135 ps
CPU time 3.03 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:50:34 PM PST 23
Peak memory 200564 kb
Host smart-6468abe3-22b8-43c8-ade4-f4bb0485e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830171893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1830171893
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4148200002
Short name T317
Test name
Test status
Simulation time 407995858269 ps
CPU time 227.02 seconds
Started Dec 20 12:49:34 PM PST 23
Finished Dec 20 12:54:15 PM PST 23
Peak memory 201060 kb
Host smart-240aea5e-89d3-4fa2-91f6-3b730c28e1e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148200002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4148200002
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.738187365
Short name T323
Test name
Test status
Simulation time 26985519555 ps
CPU time 30.94 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 12:51:02 PM PST 23
Peak memory 200980 kb
Host smart-ea06ed97-20e5-4035-8f17-820efdcf7e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738187365 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.738187365
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3100471751
Short name T447
Test name
Test status
Simulation time 366157850 ps
CPU time 0.91 seconds
Started Dec 20 12:49:50 PM PST 23
Finished Dec 20 12:50:39 PM PST 23
Peak memory 200628 kb
Host smart-4ff707ea-b931-4fef-82d5-8a863da627cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100471751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3100471751
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2859308087
Short name T103
Test name
Test status
Simulation time 163509093882 ps
CPU time 103.9 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:52:12 PM PST 23
Peak memory 200920 kb
Host smart-f18c94b2-585e-4103-9600-36a96cfb6f74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859308087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2859308087
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.120524742
Short name T160
Test name
Test status
Simulation time 164210551002 ps
CPU time 360.61 seconds
Started Dec 20 12:49:48 PM PST 23
Finished Dec 20 12:56:37 PM PST 23
Peak memory 200780 kb
Host smart-dca679dc-8d08-4ad1-9ec8-bd2580f1c29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120524742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.120524742
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.30143028
Short name T310
Test name
Test status
Simulation time 500848386703 ps
CPU time 1139.19 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 01:09:32 PM PST 23
Peak memory 200816 kb
Host smart-bf8642c5-b919-42d9-a76f-870c4884fce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30143028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.30143028
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3728544325
Short name T555
Test name
Test status
Simulation time 167562094342 ps
CPU time 322.07 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:55:54 PM PST 23
Peak memory 200896 kb
Host smart-228edb89-ca27-4e92-8cdd-68f9d97f975d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728544325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3728544325
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4041780321
Short name T587
Test name
Test status
Simulation time 164607028771 ps
CPU time 379.89 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:56:52 PM PST 23
Peak memory 200920 kb
Host smart-1efd8c95-0756-4821-8dad-87734f160876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041780321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4041780321
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.510151728
Short name T630
Test name
Test status
Simulation time 162124599255 ps
CPU time 71.36 seconds
Started Dec 20 12:49:46 PM PST 23
Finished Dec 20 12:51:47 PM PST 23
Peak memory 200972 kb
Host smart-cae70277-48a5-47a6-9642-4d9d35059c7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=510151728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.510151728
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1107245552
Short name T534
Test name
Test status
Simulation time 167944158809 ps
CPU time 367.8 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 12:56:39 PM PST 23
Peak memory 200904 kb
Host smart-1955aef0-a873-4025-abec-e0e49eabd4ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107245552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1107245552
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.942353129
Short name T139
Test name
Test status
Simulation time 329882760276 ps
CPU time 134.27 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:52:48 PM PST 23
Peak memory 200756 kb
Host smart-c2e89021-fef2-4a28-9ff4-e44369a91f37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942353129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.942353129
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4021809650
Short name T202
Test name
Test status
Simulation time 106856684102 ps
CPU time 512.88 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:59:03 PM PST 23
Peak memory 201452 kb
Host smart-12108e08-845a-4d47-a9d1-268538bc7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021809650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4021809650
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1985752712
Short name T715
Test name
Test status
Simulation time 30068617520 ps
CPU time 71 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:51:44 PM PST 23
Peak memory 200564 kb
Host smart-8bf8c494-631e-4e4f-b566-ff0086cde770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985752712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1985752712
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2030203398
Short name T842
Test name
Test status
Simulation time 5393801698 ps
CPU time 3.8 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:50:37 PM PST 23
Peak memory 200804 kb
Host smart-aed4a29a-034e-4b5b-86de-5dc15ec2af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030203398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2030203398
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.5808900
Short name T635
Test name
Test status
Simulation time 5887697655 ps
CPU time 7.74 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 12:50:39 PM PST 23
Peak memory 200700 kb
Host smart-7d778504-4328-4532-b584-4b98eb638e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5808900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.5808900
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4131861652
Short name T36
Test name
Test status
Simulation time 239535297194 ps
CPU time 197.66 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:53:52 PM PST 23
Peak memory 209612 kb
Host smart-29a875e0-ba92-40dd-8e3a-182743bc8a79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131861652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.4131861652
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1896079058
Short name T415
Test name
Test status
Simulation time 497659892 ps
CPU time 1.16 seconds
Started Dec 20 12:49:51 PM PST 23
Finished Dec 20 12:50:40 PM PST 23
Peak memory 200800 kb
Host smart-0f298630-dc2e-4013-a773-d13dbc00f731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896079058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1896079058
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1427743633
Short name T818
Test name
Test status
Simulation time 165017418615 ps
CPU time 100.61 seconds
Started Dec 20 12:49:51 PM PST 23
Finished Dec 20 12:52:19 PM PST 23
Peak memory 201024 kb
Host smart-a6d8830f-9618-40fd-bf54-7ee15e904eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427743633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1427743633
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4012421890
Short name T518
Test name
Test status
Simulation time 162030499419 ps
CPU time 171.95 seconds
Started Dec 20 12:49:49 PM PST 23
Finished Dec 20 12:53:29 PM PST 23
Peak memory 200944 kb
Host smart-e71cfc30-c5da-4da4-86ca-571e5045efc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012421890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4012421890
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1677221958
Short name T457
Test name
Test status
Simulation time 498184904947 ps
CPU time 335.44 seconds
Started Dec 20 12:49:42 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 200900 kb
Host smart-3f4836c3-d833-41a7-a058-89a71323e6f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677221958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1677221958
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3608802552
Short name T695
Test name
Test status
Simulation time 162732024613 ps
CPU time 246.4 seconds
Started Dec 20 12:49:51 PM PST 23
Finished Dec 20 12:54:45 PM PST 23
Peak memory 201096 kb
Host smart-a93812ce-921e-4d02-80f2-a6f21dd5570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608802552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3608802552
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.332729858
Short name T550
Test name
Test status
Simulation time 164581561732 ps
CPU time 104.01 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 12:52:20 PM PST 23
Peak memory 200948 kb
Host smart-dba84953-0652-4702-8d49-90842a16d412
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=332729858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.332729858
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4218927838
Short name T416
Test name
Test status
Simulation time 161318516135 ps
CPU time 95.69 seconds
Started Dec 20 12:49:36 PM PST 23
Finished Dec 20 12:52:05 PM PST 23
Peak memory 200960 kb
Host smart-4a443c29-d204-45f7-8595-083a20b3b713
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218927838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4218927838
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.586875455
Short name T483
Test name
Test status
Simulation time 64321782829 ps
CPU time 347.76 seconds
Started Dec 20 12:49:49 PM PST 23
Finished Dec 20 12:56:25 PM PST 23
Peak memory 201144 kb
Host smart-ff101af1-ed8e-4fed-ba47-4c9569dd324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586875455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.586875455
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.750994226
Short name T801
Test name
Test status
Simulation time 30589110904 ps
CPU time 71.95 seconds
Started Dec 20 12:49:52 PM PST 23
Finished Dec 20 12:51:51 PM PST 23
Peak memory 200768 kb
Host smart-0163615e-da66-4363-86a6-13ce577e014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750994226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.750994226
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.4061054848
Short name T852
Test name
Test status
Simulation time 3813217084 ps
CPU time 1.18 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:50:34 PM PST 23
Peak memory 200928 kb
Host smart-ced74c35-5abf-4f17-b4b5-5a00dee42022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061054848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.4061054848
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3579572480
Short name T495
Test name
Test status
Simulation time 6226602169 ps
CPU time 6.17 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:50:40 PM PST 23
Peak memory 200768 kb
Host smart-e91f2171-17bb-42a8-8e95-938b9ed74ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579572480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3579572480
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1124164436
Short name T115
Test name
Test status
Simulation time 347451934067 ps
CPU time 809.96 seconds
Started Dec 20 12:49:47 PM PST 23
Finished Dec 20 01:04:06 PM PST 23
Peak memory 200936 kb
Host smart-cdf0e0a5-a0e9-40fe-9311-c1f4c2bcda26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124164436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1124164436
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1644269733
Short name T783
Test name
Test status
Simulation time 30808573500 ps
CPU time 74.25 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:51:46 PM PST 23
Peak memory 209260 kb
Host smart-15ca7e77-d6f1-4bdb-bdd5-9cdb672c1c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644269733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1644269733
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.185527924
Short name T839
Test name
Test status
Simulation time 403970494 ps
CPU time 0.89 seconds
Started Dec 20 12:50:08 PM PST 23
Finished Dec 20 12:50:50 PM PST 23
Peak memory 200668 kb
Host smart-3b7aa4ba-359a-41cc-96a9-be902125fac6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185527924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.185527924
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.27084452
Short name T327
Test name
Test status
Simulation time 327186211932 ps
CPU time 754.42 seconds
Started Dec 20 12:49:48 PM PST 23
Finished Dec 20 01:03:11 PM PST 23
Peak memory 200916 kb
Host smart-17604ac9-941f-416d-a26c-fcaa98347b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27084452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.27084452
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.282810530
Short name T694
Test name
Test status
Simulation time 321476305239 ps
CPU time 764.44 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 01:03:18 PM PST 23
Peak memory 200952 kb
Host smart-26b0b4d9-e8ac-468f-b8ed-4e13b1bd9182
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=282810530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.282810530
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2906123917
Short name T623
Test name
Test status
Simulation time 323562529526 ps
CPU time 389.97 seconds
Started Dec 20 12:49:55 PM PST 23
Finished Dec 20 12:57:11 PM PST 23
Peak memory 200956 kb
Host smart-49a0fe0f-f839-4b48-82e3-97704b5e0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906123917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2906123917
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.914040977
Short name T607
Test name
Test status
Simulation time 484958997835 ps
CPU time 283.07 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 200984 kb
Host smart-449a6449-f7b1-4d32-b5e8-253389a1e599
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=914040977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.914040977
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2591002047
Short name T152
Test name
Test status
Simulation time 489813148970 ps
CPU time 1075.8 seconds
Started Dec 20 12:50:01 PM PST 23
Finished Dec 20 01:08:41 PM PST 23
Peak memory 200760 kb
Host smart-2d1f5797-2604-4114-98e7-c4cc663f81c5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591002047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2591002047
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2718019278
Short name T822
Test name
Test status
Simulation time 118096255809 ps
CPU time 593.94 seconds
Started Dec 20 12:49:56 PM PST 23
Finished Dec 20 01:00:36 PM PST 23
Peak memory 201392 kb
Host smart-031c4be6-f546-455b-829d-23fa1938c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718019278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2718019278
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3627608100
Short name T719
Test name
Test status
Simulation time 29065571716 ps
CPU time 60 seconds
Started Dec 20 12:49:56 PM PST 23
Finished Dec 20 12:51:41 PM PST 23
Peak memory 200716 kb
Host smart-36022583-554d-462f-b09e-930d432fde16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627608100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3627608100
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2864926551
Short name T732
Test name
Test status
Simulation time 4346095269 ps
CPU time 2.43 seconds
Started Dec 20 12:49:54 PM PST 23
Finished Dec 20 12:50:43 PM PST 23
Peak memory 200492 kb
Host smart-a90b4f1c-2423-4bca-8a94-31ec3ca5afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864926551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2864926551
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1236386728
Short name T774
Test name
Test status
Simulation time 5925075534 ps
CPU time 2.01 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:50:35 PM PST 23
Peak memory 200768 kb
Host smart-9479d08d-dea3-4d82-8411-c1d29ea3d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236386728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1236386728
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.136454431
Short name T786
Test name
Test status
Simulation time 340652333546 ps
CPU time 146.34 seconds
Started Dec 20 12:50:07 PM PST 23
Finished Dec 20 12:53:15 PM PST 23
Peak memory 201032 kb
Host smart-208e4989-1bd6-4b02-8948-f37dd704519a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136454431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
136454431
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.271955562
Short name T575
Test name
Test status
Simulation time 431209463 ps
CPU time 1.14 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:50:32 PM PST 23
Peak memory 200696 kb
Host smart-604f16e2-cb47-496c-a31f-648aac9cb15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271955562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.271955562
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2197557414
Short name T246
Test name
Test status
Simulation time 497964345411 ps
CPU time 192.14 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:53:42 PM PST 23
Peak memory 201056 kb
Host smart-66509292-b1ae-4e09-8529-91c1a22e3372
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197557414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2197557414
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1893358979
Short name T158
Test name
Test status
Simulation time 497623054861 ps
CPU time 310.11 seconds
Started Dec 20 12:49:33 PM PST 23
Finished Dec 20 12:55:37 PM PST 23
Peak memory 201052 kb
Host smart-3933357a-3bdc-45fc-a4a1-2995ef4bf005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893358979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1893358979
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.39888775
Short name T589
Test name
Test status
Simulation time 492388955422 ps
CPU time 667.49 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 01:01:39 PM PST 23
Peak memory 200880 kb
Host smart-372f79d0-4a2e-4528-8d04-6afced5b8b59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=39888775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.39888775
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1464027686
Short name T99
Test name
Test status
Simulation time 494207530320 ps
CPU time 230.66 seconds
Started Dec 20 12:49:59 PM PST 23
Finished Dec 20 12:54:35 PM PST 23
Peak memory 201044 kb
Host smart-07c2e274-5655-46f6-ac19-044ebbeab8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464027686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1464027686
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2031696121
Short name T465
Test name
Test status
Simulation time 163702569632 ps
CPU time 205.35 seconds
Started Dec 20 12:50:07 PM PST 23
Finished Dec 20 12:54:14 PM PST 23
Peak memory 200920 kb
Host smart-67fa9577-ca59-4e3a-bdf6-81b1df62ad84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031696121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2031696121
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1747114122
Short name T128
Test name
Test status
Simulation time 166654309682 ps
CPU time 411.86 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 12:57:24 PM PST 23
Peak memory 200732 kb
Host smart-80551e9b-1e24-46e8-aca9-fe4b93d20f52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747114122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1747114122
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4269280492
Short name T15
Test name
Test status
Simulation time 163430226500 ps
CPU time 88.95 seconds
Started Dec 20 12:49:40 PM PST 23
Finished Dec 20 12:52:01 PM PST 23
Peak memory 200988 kb
Host smart-f701fed3-471f-48bf-9ed0-62d87539dd09
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269280492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4269280492
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3983285502
Short name T211
Test name
Test status
Simulation time 81697441500 ps
CPU time 399.59 seconds
Started Dec 20 12:49:46 PM PST 23
Finished Dec 20 12:57:15 PM PST 23
Peak memory 201376 kb
Host smart-17288327-5493-4348-8803-22c9cb9674cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983285502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3983285502
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2009483471
Short name T616
Test name
Test status
Simulation time 46386066101 ps
CPU time 29.92 seconds
Started Dec 20 12:49:41 PM PST 23
Finished Dec 20 12:51:02 PM PST 23
Peak memory 200816 kb
Host smart-34ef9ccf-ede3-403d-95df-efd686ba3b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009483471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2009483471
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.613393928
Short name T93
Test name
Test status
Simulation time 3664616475 ps
CPU time 4.73 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:50:38 PM PST 23
Peak memory 200620 kb
Host smart-3d1eeea8-9cb6-4f38-9cac-885303f69c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613393928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.613393928
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3990857125
Short name T525
Test name
Test status
Simulation time 5952475842 ps
CPU time 2.54 seconds
Started Dec 20 12:50:02 PM PST 23
Finished Dec 20 12:50:49 PM PST 23
Peak memory 200620 kb
Host smart-d3a98518-ad26-4e12-a011-3adf73c65f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990857125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3990857125
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1081188808
Short name T512
Test name
Test status
Simulation time 28745241235 ps
CPU time 104.02 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:52:15 PM PST 23
Peak memory 201500 kb
Host smart-91adb649-01c1-4fff-8b06-6eb5d59e5e06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081188808 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1081188808
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3399334602
Short name T423
Test name
Test status
Simulation time 314004522 ps
CPU time 0.93 seconds
Started Dec 20 12:49:39 PM PST 23
Finished Dec 20 12:50:32 PM PST 23
Peak memory 200568 kb
Host smart-2c8614eb-967e-4efe-9b08-839fc65abc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399334602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3399334602
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3716476354
Short name T749
Test name
Test status
Simulation time 495368449278 ps
CPU time 1123.8 seconds
Started Dec 20 12:49:52 PM PST 23
Finished Dec 20 01:09:23 PM PST 23
Peak memory 200948 kb
Host smart-cab4e923-d200-45d6-8c29-b210360fb597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716476354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3716476354
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.533022154
Short name T622
Test name
Test status
Simulation time 166448482023 ps
CPU time 412.7 seconds
Started Dec 20 12:49:45 PM PST 23
Finished Dec 20 12:57:28 PM PST 23
Peak memory 200952 kb
Host smart-5244565e-55b8-4baa-aaa0-a18ad5888a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533022154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.533022154
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1631392227
Short name T514
Test name
Test status
Simulation time 327006857146 ps
CPU time 363.58 seconds
Started Dec 20 12:49:52 PM PST 23
Finished Dec 20 12:56:42 PM PST 23
Peak memory 201016 kb
Host smart-a6bc85cf-59c9-470a-9647-1a4510210324
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631392227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1631392227
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.404136600
Short name T723
Test name
Test status
Simulation time 168295786870 ps
CPU time 386.22 seconds
Started Dec 20 12:49:51 PM PST 23
Finished Dec 20 12:57:05 PM PST 23
Peak memory 200712 kb
Host smart-6283d8f0-9cd1-4206-9d6e-c7afd469f3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404136600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.404136600
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1778342703
Short name T484
Test name
Test status
Simulation time 165405686757 ps
CPU time 184.2 seconds
Started Dec 20 12:49:38 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 200896 kb
Host smart-21a39a60-4031-49a0-892a-de91baecd03a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778342703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1778342703
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.393560686
Short name T414
Test name
Test status
Simulation time 165822358450 ps
CPU time 82.05 seconds
Started Dec 20 12:49:48 PM PST 23
Finished Dec 20 12:51:59 PM PST 23
Peak memory 200820 kb
Host smart-3c054c51-7862-4c21-ab8e-ad111ed7e936
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393560686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.393560686
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1768754119
Short name T806
Test name
Test status
Simulation time 122386548467 ps
CPU time 524.68 seconds
Started Dec 20 12:49:46 PM PST 23
Finished Dec 20 12:59:20 PM PST 23
Peak memory 201436 kb
Host smart-4639a6c9-225c-4492-bcd3-a9e23aee9eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768754119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1768754119
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3632832882
Short name T493
Test name
Test status
Simulation time 23170828369 ps
CPU time 22.73 seconds
Started Dec 20 12:49:44 PM PST 23
Finished Dec 20 12:50:56 PM PST 23
Peak memory 200676 kb
Host smart-ba260340-53ed-4e3d-84c6-04c5e08918a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632832882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3632832882
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.285691209
Short name T742
Test name
Test status
Simulation time 5155193476 ps
CPU time 3.01 seconds
Started Dec 20 12:49:43 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200692 kb
Host smart-009b97bb-aba3-46f7-923b-321765b46a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285691209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.285691209
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.925304714
Short name T405
Test name
Test status
Simulation time 5601814665 ps
CPU time 12.69 seconds
Started Dec 20 12:49:50 PM PST 23
Finished Dec 20 12:50:50 PM PST 23
Peak memory 200708 kb
Host smart-64638e72-e8bc-4b72-a8bc-ad23a1bfcd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925304714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.925304714
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1794412079
Short name T543
Test name
Test status
Simulation time 182949744020 ps
CPU time 441.73 seconds
Started Dec 20 12:49:37 PM PST 23
Finished Dec 20 12:57:52 PM PST 23
Peak memory 200976 kb
Host smart-e4e5b89b-6c50-43e9-876d-80df575f2307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794412079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1794412079
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1468700984
Short name T834
Test name
Test status
Simulation time 26570116055 ps
CPU time 63.63 seconds
Started Dec 20 12:49:52 PM PST 23
Finished Dec 20 12:51:42 PM PST 23
Peak memory 217012 kb
Host smart-d83bb3b9-c87e-4e6b-8e99-c37439051373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468700984 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1468700984
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.755361337
Short name T745
Test name
Test status
Simulation time 518779785 ps
CPU time 1.22 seconds
Started Dec 20 12:48:04 PM PST 23
Finished Dec 20 12:49:17 PM PST 23
Peak memory 200624 kb
Host smart-3f27766f-dbcb-4ff9-9c24-26825d79f0aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755361337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.755361337
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.193402671
Short name T576
Test name
Test status
Simulation time 333135782952 ps
CPU time 194.19 seconds
Started Dec 20 12:47:28 PM PST 23
Finished Dec 20 12:51:57 PM PST 23
Peak memory 201016 kb
Host smart-c3c7f823-0779-4986-a03f-d36dc3661b18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193402671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.193402671
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1413904734
Short name T709
Test name
Test status
Simulation time 334986593860 ps
CPU time 197.79 seconds
Started Dec 20 12:48:10 PM PST 23
Finished Dec 20 12:52:53 PM PST 23
Peak memory 200988 kb
Host smart-a8b85cb3-9bb7-4a6c-884d-731bbf967c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413904734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1413904734
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2201453761
Short name T679
Test name
Test status
Simulation time 494728560031 ps
CPU time 298.1 seconds
Started Dec 20 12:48:01 PM PST 23
Finished Dec 20 12:54:14 PM PST 23
Peak memory 200940 kb
Host smart-b3f8e56e-43c8-459b-ab49-3009da9e5a93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201453761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2201453761
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1778622868
Short name T549
Test name
Test status
Simulation time 491338013181 ps
CPU time 261.57 seconds
Started Dec 20 12:47:42 PM PST 23
Finished Dec 20 12:53:30 PM PST 23
Peak memory 200972 kb
Host smart-e265c29b-62a3-42ad-9c75-e14768ca1754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778622868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1778622868
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.534664437
Short name T22
Test name
Test status
Simulation time 171616409765 ps
CPU time 238.39 seconds
Started Dec 20 12:47:40 PM PST 23
Finished Dec 20 12:52:55 PM PST 23
Peak memory 200760 kb
Host smart-e097dcb5-a0cf-42e5-a331-920adb10e607
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=534664437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.534664437
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4221946449
Short name T406
Test name
Test status
Simulation time 162050571910 ps
CPU time 393.25 seconds
Started Dec 20 12:47:52 PM PST 23
Finished Dec 20 12:55:50 PM PST 23
Peak memory 200948 kb
Host smart-4ba60f1b-09ca-4d0b-a4af-0d73097cc68f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221946449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4221946449
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4166681288
Short name T475
Test name
Test status
Simulation time 143457984232 ps
CPU time 481.94 seconds
Started Dec 20 12:48:08 PM PST 23
Finished Dec 20 12:57:42 PM PST 23
Peak memory 201436 kb
Host smart-97bca0f6-946d-4870-b30a-7af832baf034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166681288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4166681288
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1528496919
Short name T739
Test name
Test status
Simulation time 43577842872 ps
CPU time 16.82 seconds
Started Dec 20 12:48:00 PM PST 23
Finished Dec 20 12:49:38 PM PST 23
Peak memory 200824 kb
Host smart-0d4bab10-2e2a-47f3-92b1-94eadd29a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528496919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1528496919
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1215464229
Short name T634
Test name
Test status
Simulation time 3564192608 ps
CPU time 5.1 seconds
Started Dec 20 12:48:06 PM PST 23
Finished Dec 20 12:49:37 PM PST 23
Peak memory 200860 kb
Host smart-b2c76cb5-8dd3-4cdd-8d5e-de9f75f55c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215464229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1215464229
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3180240179
Short name T448
Test name
Test status
Simulation time 6054350679 ps
CPU time 11.94 seconds
Started Dec 20 12:47:53 PM PST 23
Finished Dec 20 12:49:23 PM PST 23
Peak memory 200696 kb
Host smart-ff75aae0-f87e-4fdb-8404-10f1fcd42333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180240179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3180240179
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3377811773
Short name T247
Test name
Test status
Simulation time 43854980904 ps
CPU time 108.74 seconds
Started Dec 20 12:48:30 PM PST 23
Finished Dec 20 12:51:37 PM PST 23
Peak memory 209164 kb
Host smart-233ab702-5630-49a6-89b8-c55e9482114b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377811773 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3377811773
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.364395700
Short name T441
Test name
Test status
Simulation time 567397532 ps
CPU time 0.78 seconds
Started Dec 20 12:49:21 PM PST 23
Finished Dec 20 12:50:20 PM PST 23
Peak memory 200732 kb
Host smart-3a8bf1dc-3f00-4ae9-a82c-587d894ad50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364395700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.364395700
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.824308227
Short name T615
Test name
Test status
Simulation time 165720880676 ps
CPU time 181.72 seconds
Started Dec 20 12:48:02 PM PST 23
Finished Dec 20 12:52:50 PM PST 23
Peak memory 200920 kb
Host smart-b620cdac-62d2-4650-a589-3bb481ace34d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824308227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.824308227
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1004711255
Short name T187
Test name
Test status
Simulation time 324955607618 ps
CPU time 191.56 seconds
Started Dec 20 12:48:02 PM PST 23
Finished Dec 20 12:52:34 PM PST 23
Peak memory 200984 kb
Host smart-36de699d-fdbd-486d-9f79-b9b81b10ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004711255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1004711255
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3296953123
Short name T523
Test name
Test status
Simulation time 327404215154 ps
CPU time 82.95 seconds
Started Dec 20 12:48:11 PM PST 23
Finished Dec 20 12:50:58 PM PST 23
Peak memory 200896 kb
Host smart-cd971ded-d790-4336-a600-4f05892d954e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296953123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3296953123
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.826695393
Short name T831
Test name
Test status
Simulation time 168900242981 ps
CPU time 235.47 seconds
Started Dec 20 12:48:07 PM PST 23
Finished Dec 20 12:53:13 PM PST 23
Peak memory 200924 kb
Host smart-1d813223-fdef-442a-afd6-3f41d1138657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826695393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.826695393
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3617785915
Short name T605
Test name
Test status
Simulation time 485158431278 ps
CPU time 568.55 seconds
Started Dec 20 12:48:21 PM PST 23
Finished Dec 20 12:58:57 PM PST 23
Peak memory 200908 kb
Host smart-9dec1a62-da67-4eb2-bf22-2c2b4956c6b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617785915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3617785915
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.275079299
Short name T116
Test name
Test status
Simulation time 329312291489 ps
CPU time 361.34 seconds
Started Dec 20 12:48:03 PM PST 23
Finished Dec 20 12:55:16 PM PST 23
Peak memory 200952 kb
Host smart-6d02a221-ee33-40e8-aa34-b8bd6066f34c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275079299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.275079299
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2465584534
Short name T452
Test name
Test status
Simulation time 332484178062 ps
CPU time 645.12 seconds
Started Dec 20 12:48:16 PM PST 23
Finished Dec 20 01:00:30 PM PST 23
Peak memory 200840 kb
Host smart-ba4fb61a-c76b-468c-9519-11de6fec7dec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465584534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2465584534
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3093464153
Short name T55
Test name
Test status
Simulation time 98487146893 ps
CPU time 366.79 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:55:52 PM PST 23
Peak memory 201364 kb
Host smart-5d16a883-e4bd-431b-9bc5-783bca177644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093464153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3093464153
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1128183944
Short name T687
Test name
Test status
Simulation time 43904289170 ps
CPU time 51.38 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:50:37 PM PST 23
Peak memory 200812 kb
Host smart-00178a28-d2cc-4be7-8021-da5bf37ca1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128183944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1128183944
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1908781045
Short name T439
Test name
Test status
Simulation time 3824361863 ps
CPU time 1.39 seconds
Started Dec 20 12:48:02 PM PST 23
Finished Dec 20 12:49:53 PM PST 23
Peak memory 200784 kb
Host smart-3942b275-0c44-4529-abae-e063f8b06034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908781045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1908781045
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3692921450
Short name T794
Test name
Test status
Simulation time 5719557389 ps
CPU time 14.19 seconds
Started Dec 20 12:48:09 PM PST 23
Finished Dec 20 12:49:38 PM PST 23
Peak memory 200764 kb
Host smart-5d915273-8e99-4a15-9858-de55cac8d380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692921450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3692921450
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2051210276
Short name T442
Test name
Test status
Simulation time 1210855445 ps
CPU time 1.32 seconds
Started Dec 20 12:48:16 PM PST 23
Finished Dec 20 12:49:33 PM PST 23
Peak memory 200564 kb
Host smart-9126b9a4-c8cb-4615-b19b-10716a1930b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051210276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2051210276
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2636639471
Short name T146
Test name
Test status
Simulation time 76808823129 ps
CPU time 82.22 seconds
Started Dec 20 12:48:05 PM PST 23
Finished Dec 20 12:50:55 PM PST 23
Peak memory 209704 kb
Host smart-2ca13a4d-2044-4947-93a2-ac64ea93a717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636639471 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2636639471
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3699869825
Short name T591
Test name
Test status
Simulation time 370278955 ps
CPU time 1.44 seconds
Started Dec 20 12:48:09 PM PST 23
Finished Dec 20 12:49:23 PM PST 23
Peak memory 200700 kb
Host smart-1b19d355-f48c-4358-b707-0bcacf5467d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699869825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3699869825
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2817805800
Short name T295
Test name
Test status
Simulation time 334339820311 ps
CPU time 108.47 seconds
Started Dec 20 12:48:08 PM PST 23
Finished Dec 20 12:51:14 PM PST 23
Peak memory 200976 kb
Host smart-bdcc6a5b-5b3b-466b-8ad1-862707b101ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817805800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2817805800
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3038130112
Short name T181
Test name
Test status
Simulation time 165835780987 ps
CPU time 307.87 seconds
Started Dec 20 12:48:09 PM PST 23
Finished Dec 20 12:54:32 PM PST 23
Peak memory 201036 kb
Host smart-ab3277cb-97fd-4778-bbd9-b0c6442cd336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038130112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3038130112
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.641442476
Short name T292
Test name
Test status
Simulation time 329142968051 ps
CPU time 61.63 seconds
Started Dec 20 12:48:11 PM PST 23
Finished Dec 20 12:50:36 PM PST 23
Peak memory 200796 kb
Host smart-43ef7bf0-ee4a-425c-ae8e-95df0e4dcf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641442476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.641442476
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.758607460
Short name T590
Test name
Test status
Simulation time 332825860077 ps
CPU time 782.98 seconds
Started Dec 20 12:48:02 PM PST 23
Finished Dec 20 01:02:19 PM PST 23
Peak memory 200944 kb
Host smart-116cd713-cccf-4e32-8faf-ec2ba849b5ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=758607460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.758607460
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3528166796
Short name T270
Test name
Test status
Simulation time 160199313916 ps
CPU time 352.17 seconds
Started Dec 20 12:48:05 PM PST 23
Finished Dec 20 12:55:14 PM PST 23
Peak memory 200992 kb
Host smart-1b5f35ee-1934-4de3-8669-9fe6e46e04a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528166796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3528166796
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.19335624
Short name T767
Test name
Test status
Simulation time 164696598178 ps
CPU time 89.39 seconds
Started Dec 20 12:48:05 PM PST 23
Finished Dec 20 12:51:02 PM PST 23
Peak memory 200900 kb
Host smart-c3418c37-26a1-443c-bde2-9c71aa21a087
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=19335624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.19335624
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2538892133
Short name T138
Test name
Test status
Simulation time 338085017644 ps
CPU time 117.23 seconds
Started Dec 20 12:48:03 PM PST 23
Finished Dec 20 12:51:20 PM PST 23
Peak memory 200916 kb
Host smart-018b20d2-0f8e-438c-9fb0-89f8d8e771d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538892133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2538892133
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1651282854
Short name T509
Test name
Test status
Simulation time 487323612193 ps
CPU time 307.43 seconds
Started Dec 20 12:48:04 PM PST 23
Finished Dec 20 12:54:31 PM PST 23
Peak memory 200936 kb
Host smart-e6c46e53-4609-49bb-87f6-caf7c2f295e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651282854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1651282854
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.686580021
Short name T208
Test name
Test status
Simulation time 77078276874 ps
CPU time 436.17 seconds
Started Dec 20 12:48:06 PM PST 23
Finished Dec 20 12:57:01 PM PST 23
Peak memory 201388 kb
Host smart-b1466534-29de-491f-a533-2b5e2d03512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686580021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.686580021
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4280906485
Short name T118
Test name
Test status
Simulation time 41340605515 ps
CPU time 9.7 seconds
Started Dec 20 12:48:16 PM PST 23
Finished Dec 20 12:49:45 PM PST 23
Peak memory 200760 kb
Host smart-bd1b95b7-7ce4-4100-b672-80968d33dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280906485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4280906485
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2835924024
Short name T426
Test name
Test status
Simulation time 4290925166 ps
CPU time 8.96 seconds
Started Dec 20 12:48:03 PM PST 23
Finished Dec 20 12:49:49 PM PST 23
Peak memory 200732 kb
Host smart-dc7af999-2c7a-4af7-aa0a-d5dcb19d3020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835924024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2835924024
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3533857434
Short name T411
Test name
Test status
Simulation time 6181981742 ps
CPU time 4.6 seconds
Started Dec 20 12:48:35 PM PST 23
Finished Dec 20 12:49:44 PM PST 23
Peak memory 200764 kb
Host smart-e67a90b9-97c6-47f5-82e5-f0884cb88a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533857434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3533857434
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1782671889
Short name T594
Test name
Test status
Simulation time 349756361279 ps
CPU time 803.08 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 01:02:58 PM PST 23
Peak memory 200904 kb
Host smart-6f0493c3-2104-4a3f-b990-0dca29e3457e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782671889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1782671889
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2161317580
Short name T214
Test name
Test status
Simulation time 107779283460 ps
CPU time 226.03 seconds
Started Dec 20 12:48:29 PM PST 23
Finished Dec 20 12:53:35 PM PST 23
Peak memory 200996 kb
Host smart-9f78038e-0b2d-4d35-9ebd-e047b80915c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161317580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2161317580
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3230610554
Short name T819
Test name
Test status
Simulation time 296453542 ps
CPU time 0.94 seconds
Started Dec 20 12:48:15 PM PST 23
Finished Dec 20 12:49:24 PM PST 23
Peak memory 200624 kb
Host smart-9201d640-a1ba-453b-b3f9-6cf478097f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230610554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3230610554
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.341180929
Short name T334
Test name
Test status
Simulation time 484560476581 ps
CPU time 296.12 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:54:43 PM PST 23
Peak memory 201020 kb
Host smart-5c7a61b8-013d-4bcd-9d74-9781995a3bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341180929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.341180929
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2760331275
Short name T802
Test name
Test status
Simulation time 161393844001 ps
CPU time 98.35 seconds
Started Dec 20 12:48:09 PM PST 23
Finished Dec 20 12:51:16 PM PST 23
Peak memory 200944 kb
Host smart-0b2a67c7-1e32-454e-a8b2-f48cdbd5ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760331275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2760331275
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1856246613
Short name T708
Test name
Test status
Simulation time 325249702279 ps
CPU time 149.08 seconds
Started Dec 20 12:48:43 PM PST 23
Finished Dec 20 12:52:18 PM PST 23
Peak memory 200916 kb
Host smart-b7b4767b-9e52-49b3-94c2-9228412c710f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856246613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1856246613
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.153358186
Short name T157
Test name
Test status
Simulation time 490676990346 ps
CPU time 318.78 seconds
Started Dec 20 12:48:10 PM PST 23
Finished Dec 20 12:54:56 PM PST 23
Peak memory 200936 kb
Host smart-d3146e9d-21d8-4707-b496-7030a87724e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153358186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.153358186
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2127138449
Short name T120
Test name
Test status
Simulation time 159171296826 ps
CPU time 374.18 seconds
Started Dec 20 12:48:11 PM PST 23
Finished Dec 20 12:55:49 PM PST 23
Peak memory 200872 kb
Host smart-55e494b4-98ec-4037-8e8f-4c5f5d636c5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127138449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2127138449
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.993979104
Short name T516
Test name
Test status
Simulation time 163983332900 ps
CPU time 61.21 seconds
Started Dec 20 12:48:05 PM PST 23
Finished Dec 20 12:50:23 PM PST 23
Peak memory 200980 kb
Host smart-baf2b4f5-816f-4ebf-9315-243981a824e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993979104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.993979104
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3057106089
Short name T738
Test name
Test status
Simulation time 485973235908 ps
CPU time 122.13 seconds
Started Dec 20 12:48:22 PM PST 23
Finished Dec 20 12:51:48 PM PST 23
Peak memory 200904 kb
Host smart-a679fa5c-ea14-4794-a4c8-e9ee3f46fca5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057106089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3057106089
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1298644187
Short name T725
Test name
Test status
Simulation time 77132257564 ps
CPU time 463.93 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:57:39 PM PST 23
Peak memory 201392 kb
Host smart-8c19d01f-9836-4c74-ac2d-8fa533537606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298644187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1298644187
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3134497167
Short name T522
Test name
Test status
Simulation time 43064971869 ps
CPU time 25.64 seconds
Started Dec 20 12:48:15 PM PST 23
Finished Dec 20 12:50:05 PM PST 23
Peak memory 200652 kb
Host smart-b4760c90-a474-411b-be5f-c689e5c6950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134497167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3134497167
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1834182085
Short name T667
Test name
Test status
Simulation time 5025724170 ps
CPU time 13.42 seconds
Started Dec 20 12:48:12 PM PST 23
Finished Dec 20 12:49:37 PM PST 23
Peak memory 200688 kb
Host smart-2a43665a-6e6e-4294-8923-9d2ed29d57f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834182085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1834182085
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.709723021
Short name T507
Test name
Test status
Simulation time 6004517810 ps
CPU time 14.45 seconds
Started Dec 20 12:48:12 PM PST 23
Finished Dec 20 12:49:51 PM PST 23
Peak memory 200780 kb
Host smart-fa38cc4d-3741-4a95-8441-6f7a190dbf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709723021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.709723021
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1418026678
Short name T850
Test name
Test status
Simulation time 198612634307 ps
CPU time 473.73 seconds
Started Dec 20 12:48:40 PM PST 23
Finished Dec 20 12:57:39 PM PST 23
Peak memory 200940 kb
Host smart-4233e779-e478-45e1-b497-2c6f41ec373e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418026678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1418026678
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1946295932
Short name T443
Test name
Test status
Simulation time 46329063279 ps
CPU time 29.56 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 12:50:15 PM PST 23
Peak memory 201016 kb
Host smart-98cb5e8c-5670-47d0-971e-4d1c81fc4900
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946295932 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1946295932
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.21895201
Short name T649
Test name
Test status
Simulation time 307674185 ps
CPU time 0.79 seconds
Started Dec 20 12:48:19 PM PST 23
Finished Dec 20 12:49:54 PM PST 23
Peak memory 200704 kb
Host smart-6d92aa0f-0445-4a00-9d72-9a5c8d5503a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21895201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.21895201
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2688010487
Short name T711
Test name
Test status
Simulation time 163980674895 ps
CPU time 99.7 seconds
Started Dec 20 12:48:51 PM PST 23
Finished Dec 20 12:51:35 PM PST 23
Peak memory 201076 kb
Host smart-88ed63e8-aae8-45f9-bdcd-3f30b432a387
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688010487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2688010487
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3003725613
Short name T257
Test name
Test status
Simulation time 330750303312 ps
CPU time 218.03 seconds
Started Dec 20 12:48:22 PM PST 23
Finished Dec 20 12:53:27 PM PST 23
Peak memory 201064 kb
Host smart-ceda8fcb-4d09-488e-855e-949335e18548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003725613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3003725613
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3846308930
Short name T186
Test name
Test status
Simulation time 487541129654 ps
CPU time 287.62 seconds
Started Dec 20 12:48:43 PM PST 23
Finished Dec 20 12:54:34 PM PST 23
Peak memory 201028 kb
Host smart-008a2be4-8737-4266-9285-5c0799ae094e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846308930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3846308930
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.569225870
Short name T592
Test name
Test status
Simulation time 162862500757 ps
CPU time 32.98 seconds
Started Dec 20 12:48:12 PM PST 23
Finished Dec 20 12:49:57 PM PST 23
Peak memory 200888 kb
Host smart-9137d149-a7c9-4b8e-bec0-54cec539f657
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=569225870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.569225870
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2720267725
Short name T746
Test name
Test status
Simulation time 160481053767 ps
CPU time 97.59 seconds
Started Dec 20 12:48:13 PM PST 23
Finished Dec 20 12:51:26 PM PST 23
Peak memory 201016 kb
Host smart-7594d718-472f-4453-bc9c-02fd47c40085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720267725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2720267725
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2321032387
Short name T644
Test name
Test status
Simulation time 164693653074 ps
CPU time 412.82 seconds
Started Dec 20 12:48:12 PM PST 23
Finished Dec 20 12:56:23 PM PST 23
Peak memory 200992 kb
Host smart-ceae2600-978b-4e93-953f-d0bfde4892d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321032387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2321032387
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2891589116
Short name T603
Test name
Test status
Simulation time 324152910983 ps
CPU time 377.65 seconds
Started Dec 20 12:48:51 PM PST 23
Finished Dec 20 12:56:13 PM PST 23
Peak memory 200932 kb
Host smart-be5efae3-18ba-4b04-8596-bcc8d49118ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891589116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2891589116
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2418516434
Short name T581
Test name
Test status
Simulation time 99842488679 ps
CPU time 385.31 seconds
Started Dec 20 12:48:33 PM PST 23
Finished Dec 20 12:56:14 PM PST 23
Peak memory 201236 kb
Host smart-f5b4bc6b-40b8-4c40-a0ff-7ef5db5ea322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418516434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2418516434
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3046505117
Short name T491
Test name
Test status
Simulation time 46477006745 ps
CPU time 106.17 seconds
Started Dec 20 12:48:50 PM PST 23
Finished Dec 20 12:51:42 PM PST 23
Peak memory 200800 kb
Host smart-f4aa13c0-4748-47e8-9965-b72215914f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046505117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3046505117
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4142640143
Short name T20
Test name
Test status
Simulation time 5095840972 ps
CPU time 7.06 seconds
Started Dec 20 12:48:17 PM PST 23
Finished Dec 20 12:49:33 PM PST 23
Peak memory 200728 kb
Host smart-b3d9f457-3418-43b7-9f9a-f88de89b69e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142640143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4142640143
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3713171871
Short name T418
Test name
Test status
Simulation time 5896391998 ps
CPU time 3.96 seconds
Started Dec 20 12:48:16 PM PST 23
Finished Dec 20 12:49:38 PM PST 23
Peak memory 200776 kb
Host smart-3e3970c2-c07c-4a86-af7b-ec87da8a6054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713171871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3713171871
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1803029999
Short name T583
Test name
Test status
Simulation time 329203538802 ps
CPU time 681.4 seconds
Started Dec 20 12:48:32 PM PST 23
Finished Dec 20 01:00:58 PM PST 23
Peak memory 209572 kb
Host smart-f477ea7c-640b-4f27-aa71-8dc3436b9d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803029999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1803029999
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1818729603
Short name T332
Test name
Test status
Simulation time 267734003491 ps
CPU time 324.38 seconds
Started Dec 20 12:48:44 PM PST 23
Finished Dec 20 12:55:21 PM PST 23
Peak memory 209724 kb
Host smart-c4600bbd-9c4a-4bbc-8057-9cb757b5ae90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818729603 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1818729603
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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