Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6822	1			T18	25		T19	38		T21	155
testmodes[AdcCtrlTestmodeNormal]	5633	1			T14	3		T15	3		T16	3
testmodes[AdcCtrlTestmodeLowpower]	5783	1			T13	2		T17	1		T18	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3618	1			T18	20		T19	16		T21	60
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1739	1			T18	4		T19	10		T21	46
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1358	1			T18	1		T19	12		T21	49
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1785	1			T18	4		T19	9		T21	49
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2067	1			T14	2		T15	2		T16	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1443	1			T19	11		T21	35		T34	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1301	1			T19	12		T21	46		T34	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1487	1			T18	1		T19	11		T21	37
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2744	1			T13	1		T18	19		T19	44