Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22230

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3597

1

T14

3

T19

26

T20

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20445

1

T5

1

T23

1

T24

1

auto[1]

5382

1

T13

15

T14

1

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31	1			T184	12		T124	5		T185	14
values[1]	630	1			T21	15		T35	27		T107	1
values[2]	728	1			T14	1		T19	19		T98	9
values[3]	622	1			T14	1		T21	2		T186	2
values[4]	785	1			T18	18		T94	10		T117	3
values[5]	585	1			T14	1		T105	5		T32	21
values[6]	676	1			T127	1		T186	8		T187	1
values[7]	828	1			T19	7		T34	7		T127	1
values[8]	673	1			T117	13		T105	1		T100	30
values[9]	2925	1			T13	15		T15	23		T16	24
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	872	1			T14	1		T19	19		T21	15
values[1]	657	1			T14	1		T32	1		T186	2
values[2]	738	1			T18	18		T21	2		T94	10
values[3]	691	1			T14	1		T117	3		T140	9
values[4]	547	1			T105	5		T127	1		T186	6
values[5]	695	1			T186	2		T187	1		T101	1
values[6]	2637	1			T13	15		T15	23		T16	24
values[7]	750	1			T20	15		T117	13		T46	8
values[8]	695	1			T21	11		T105	6		T187	1
values[9]	196	1			T140	2		T52	1		T157	18
minimum	17349	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T98	5		T101	6		T188	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T14	1		T19	9		T21	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T186	1		T141	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	1		T32	1		T108	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	1		T94	7		T118	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T21	2		T127	1		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T140	7		T107	1		T103	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T117	3		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T105	5		T186	2		T108	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T127	1		T102	1		T109	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T187	1		T101	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T186	2		T109	7		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T13	15		T15	3		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T19	4		T34	4		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	3		T48	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T20	15		T117	13		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T21	3		T105	6		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T21	5		T187	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T157	9		T112	1		T190	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T140	2		T52	1		T152	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17203	1			T18	50		T19	131		T21	423
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T98	4		T101	1		T188	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T19	10		T21	7		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T186	1		T191	2		T192	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T147	13		T193	12		T194	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T18	17		T94	3		T118	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T46	10		T195	9		T147	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T140	2		T103	4		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T32	9		T33	2		T102	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T186	4		T108	2		T118	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T102	15		T109	10		T196	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T102	5		T118	10		T197	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T109	6		T198	4		T199	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T15	20		T16	21		T53	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T19	3		T34	3		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	5		T189	7		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T108	2		T200	17		T199	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T158	8		T201	7		T180	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T21	3		T202	11		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T157	9		T203	3		T204	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T205	13		T194	10		T206	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	1		T23	1		T24	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum , values[0]]	*	--	--	4

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T124	5		T185	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T184	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T101	6		T188	1		T207	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	8		T35	14		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T98	5		T141	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T14	1		T19	9		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T186	1		T118	1		T208	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	1		T21	2		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T18	1		T94	7		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T117	3		T127	1		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T105	5		T108	3		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T32	12		T33	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T186	2		T187	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	1		T186	2		T109	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T127	1		T102	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T19	4		T34	4		T138	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T100	15		T163	11		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T117	13		T105	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T13	15		T15	3		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	15		T21	5		T140	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T101	1		T188	2		T210	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	7		T35	13		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T98	4		T211	10		T212	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T19	10		T147	13		T121	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T186	1		T118	7		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	10		T195	9		T147	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T18	17		T94	3		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T102	13		T213	3		T212	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T108	2		T50	2		T118	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T32	9		T33	2		T102	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T186	4		T118	10		T197	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T109	6		T199	14		T214	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T102	5		T215	2		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T19	3		T34	3		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T100	15		T163	3		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	2		T198	7		T200	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T15	20		T16	21		T53	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T21	3		T108	2		T202	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T98	6		T101	5		T188	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T14	1		T19	13		T21	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T186	2		T141	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T14	1		T32	1		T108	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	18		T94	8		T118	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T21	1		T127	1		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	7		T107	1		T103	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T14	1		T117	1		T32	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T105	1		T186	5		T108	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T127	1		T102	16		T109	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T187	1		T101	1		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T186	1		T109	7		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T13	2		T15	23		T16	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T19	7		T34	7		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T46	6		T48	1		T189	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T20	1		T117	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T21	1		T105	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T21	5		T187	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T157	10		T112	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T140	2		T52	1		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17349	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T98	3		T101	2		T211	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T19	6		T21	6		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T208	6		T217	11		T191	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T108	1		T147	12		T193	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T94	2		T181	4		T217	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	1		T46	10		T195	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	2		T103	1		T195	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T117	2		T32	8		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T105	4		T186	1		T108	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T196	16		T218	2		T190	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T118	3		T216	8		T219	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T186	1		T109	6		T199	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T13	13		T17	10		T22	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	13		T163	2		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	2		T164	1		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	14		T117	12		T221	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T21	2		T105	5		T158	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T21	3		T202	6		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T157	8		T190	16		T222	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T152	8		T194	8		T206	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T124	1		T185	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T184	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T101	5		T188	3		T207	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	9		T35	14		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T98	6		T141	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T14	1		T19	13		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T186	2		T118	8		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	1		T21	1		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T18	18		T94	8		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T117	1		T127	1		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T105	1		T108	4		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	1		T32	13		T33	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T186	5		T187	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T127	1		T186	1		T109	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T127	1		T102	6		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T19	7		T34	7		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T100	16		T163	4		T46	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T117	1		T105	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T13	2		T15	23		T16	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T20	1		T21	5		T140	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T124	4		T185	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T184	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T101	2		T207	13		T210	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	6		T35	13		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T98	3		T211	11		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	6		T147	12		T121	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T208	6		T223	10		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	1		T46	10		T108	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T94	2		T140	2		T103	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T117	2		T212	1		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T105	4		T108	1		T118	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T32	8		T33	1		T196	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T186	1		T118	3		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T186	1		T109	6		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T215	2		T216	8		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T138	13		T163	2		T211	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T100	14		T163	10		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T117	12		T147	2		T221	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T13	13		T17	10		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T20	14		T21	3		T202	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22154

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T14

2

T18

18

T19

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20003

1

T5

1

T23

1

T24

1

auto[1]

5824

1

T13

15

T14

3

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	55	1			T196	33		T224	1		T225	1
values[1]	671	1			T94	3		T127	1		T33	6
values[2]	699	1			T21	2		T105	5		T140	9
values[3]	545	1			T18	18		T20	15		T21	8
values[4]	781	1			T19	19		T117	13		T138	14
values[5]	450	1			T14	1		T34	7		T94	5
values[6]	549	1			T21	18		T48	1		T195	18
values[7]	740	1			T32	21		T102	22		T109	13
values[8]	2491	1			T13	15		T15	23		T16	24
values[9]	1502	1			T14	2		T19	7		T94	2
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	869	1			T94	3		T127	1		T33	5
values[1]	664	1			T18	18		T20	15		T21	2
values[2]	658	1			T21	8		T138	14		T32	1
values[3]	632	1			T19	19		T34	7		T98	9
values[4]	468	1			T94	5		T117	13		T186	2
values[5]	729	1			T14	1		T21	15		T32	21
values[6]	2482	1			T13	15		T15	23		T16	24
values[7]	726	1			T14	1		T35	27		T94	2
values[8]	1070	1			T14	1		T19	7		T105	6
values[9]	152	1			T200	1		T113	29		T194	2
minimum	17377	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T33	3		T163	3		T101	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T94	2		T127	1		T187	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T20	15		T21	2		T105	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	1		T163	11		T195	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T208	7		T200	1		T199	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T21	5		T138	14		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T127	1		T140	2		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T19	9		T34	4		T98	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T94	3		T107	1		T195	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T117	13		T186	1		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T21	8		T48	1		T226	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	1		T32	12		T186	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T13	15		T15	3		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T102	1		T109	7		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T35	14		T94	2		T117	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T100	15		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T14	1		T46	3		T108	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T19	4		T105	6		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T200	1		T113	14		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T123	1		T161	1		T133	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17219	1			T18	50		T19	131		T21	423
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	2		T163	14		T101	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T94	1		T109	10		T118	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T140	2		T102	13		T164	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T18	17		T163	3		T195	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T200	17		T199	12		T121	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T21	3		T195	8		T211	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	10		T227	4		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T19	10		T34	3		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T94	2		T195	9		T50	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T186	1		T216	9		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	7		T147	14		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T32	9		T186	4		T201	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T15	20		T16	21		T53	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T102	15		T109	6		T118	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	13		T197	15		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T100	15		T189	7		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T46	5		T108	2		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T19	3		T108	2		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T113	15		T194	1		T232	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T123	6		T161	2		T133	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T23	1		T24	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T225	1		T233	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T196	17		T224	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T33	4		T101	6		T103	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T94	2		T127	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	2		T105	5		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T163	11		T187	2		T195	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T20	15		T208	7		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	1		T21	5		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T46	11		T200	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T19	9		T117	13		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T94	3		T127	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	1		T34	4		T98	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T21	11		T48	1		T195	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T201	1		T234	14		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T102	1		T104	1		T226	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T32	12		T102	1		T109	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T13	15		T15	3		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T100	15		T111	16		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T14	1		T94	2		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	447	1			T14	1		T19	4		T105	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T233	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T196	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	2		T101	1		T103	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T94	1		T109	10		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	2		T163	14		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T163	3		T195	2		T50	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T199	12		T121	10		T235	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T18	17		T21	3		T195	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T46	10		T200	17		T227	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T19	10		T211	16		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T94	2		T50	3		T118	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	3		T98	4		T186	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T21	7		T195	9		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T201	7		T227	9		T237	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T102	5		T147	14		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T32	9		T102	15		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T15	20		T16	21		T53	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T100	15		T214	4		T180	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T46	5		T108	2		T188	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	422	1			T19	3		T108	2		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1