Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22678

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3149

1

T14

1

T19

19

T20

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20146

1

T5

1

T23

1

T24

1

auto[1]

5681

1

T13

15

T14

1

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	209	1			T127	1		T141	1		T147	33
values[0]	24	1			T285	1		T194	19		T295	4
values[1]	718	1			T20	15		T105	1		T127	1
values[2]	758	1			T21	15		T34	7		T94	3
values[3]	657	1			T14	1		T19	26		T94	5
values[4]	517	1			T14	1		T127	1		T138	14
values[5]	2578	1			T13	15		T14	1		T15	23
values[6]	696	1			T21	2		T98	9		T117	13
values[7]	812	1			T18	18		T35	27		T117	3
values[8]	489	1			T105	5		T163	17		T46	29
values[9]	1025	1			T21	3		T32	1		T107	1
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	676	1			T20	15		T105	1		T127	1
values[1]	799	1			T14	1		T21	15		T34	7
values[2]	595	1			T14	1		T19	26		T94	5
values[3]	2479	1			T13	15		T14	1		T15	23
values[4]	618	1			T21	8		T94	2		T100	30
values[5]	802	1			T21	2		T98	9		T117	16
values[6]	753	1			T18	18		T35	27		T187	1
values[7]	378	1			T105	5		T163	17		T101	1
values[8]	1033	1			T21	3		T127	1		T107	1
values[9]	124	1			T32	1		T286	12		T269	13
minimum	17570	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T33	1		T102	1		T236	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	15		T105	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T108	3		T195	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	8		T34	4		T94	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T19	4		T94	3		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T19	9		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T13	15		T14	1		T15	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T127	1		T32	12		T103	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T94	2		T209	1		T118	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	5		T100	15		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T107	1		T102	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T21	2		T98	5		T117	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T18	1		T187	1		T101	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	14		T46	3		T152	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T105	5		T163	3		T46	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T101	1		T157	3		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T163	11		T102	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T21	3		T127	1		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T32	1		T286	12		T269	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T291	7		T315	5		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17243	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T164	5		T284	1		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T102	15		T236	13		T210	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T288	6		T206	11		T316	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T195	2		T157	12		T199	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	7		T34	3		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T19	3		T94	2		T195	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T19	10		T140	2		T108	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T15	20		T16	21		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T32	9		T103	4		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T118	10		T198	4		T113	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T21	3		T100	15		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T102	13		T195	8		T180	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T98	4		T147	13		T201	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T18	17		T101	1		T109	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T35	13		T46	5		T131	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T163	14		T46	10		T188	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T157	2		T205	8		T251	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T163	3		T102	5		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T50	3		T189	7		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T142	10		T289	12		T290	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T291	10		T315	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T164	4		T287	2		T122	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T141	1		T147	19		T200	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T127	1		T161	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T194	9		T295	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T33	1		T102	1		T242	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T20	15		T105	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T108	3		T195	10		T236	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T21	8		T34	4		T94	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	1		T19	4		T94	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T19	9		T105	6		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	14		T187	1		T108	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T127	1		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T13	15		T14	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T21	5		T100	15		T186	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T107	1		T102	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T21	2		T98	5		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T18	1		T187	1		T101	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	14		T117	3		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T105	5		T163	3		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T46	3		T157	3		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T32	1		T163	11		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T21	3		T107	1		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T147	14		T200	17		T288	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T161	2		T203	3		T293	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T194	10		T295	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T102	15		T210	3		T131	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T164	4		T287	2		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T195	2		T236	13		T113	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	7		T34	3		T94	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	3		T94	2		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T19	10		T140	2		T33	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T108	2		T195	9		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T32	9		T103	4		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T15	20		T16	21		T53	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T21	3		T100	15		T186	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T102	13		T195	8		T118	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T98	4		T147	13		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	17		T101	1		T109	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	13		T201	7		T246	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T163	14		T46	10		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T46	5		T157	2		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T163	3		T102	5		T50	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T50	3		T189	7		T211	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T33	1		T102	16		T236	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	1		T105	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T14	1		T108	2		T195	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T21	9		T34	7		T94	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T19	7		T94	4		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	1		T19	13		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T13	2		T14	1		T15	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T127	1		T32	13		T103	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T94	2		T209	1		T118	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	5		T100	16		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T107	1		T102	14		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T21	1		T98	6		T117	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T18	18		T187	1		T101	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	14		T46	6		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T105	1		T163	15		T46	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T101	1		T157	3		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T163	4		T102	6		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T21	1		T127	1		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T32	1		T286	1		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T291	11		T315	9		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17418	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T164	8		T284	1		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T236	14		T210	4		T113	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T20	14		T186	1		T124	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T108	1		T195	9		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T21	6		T94	1		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T94	1		T195	8		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	6		T105	5		T140	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T13	13		T17	10		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T32	8		T103	1		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T118	3		T113	13		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T21	3		T100	14		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T195	8		T180	1		T317	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T21	1		T98	3		T117	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T101	2		T109	6		T226	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	13		T46	2		T152	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T105	4		T163	2		T46	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T157	2		T217	11		T298	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T163	10		T220	11		T211	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T21	2		T211	11		T197	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T286	11		T269	12		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T291	6		T315	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T235	4		T318	1		T319	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T164	1		T287	1		T122	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T141	1		T147	15		T200	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T127	1		T161	3		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T194	11		T295	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T33	1		T102	16		T242	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	1		T105	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T108	2		T195	3		T236	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	9		T34	7		T94	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	1		T19	7		T94	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T19	13		T105	1		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T138	1		T187	1		T108	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T127	1		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T13	2		T14	1		T15	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	5		T100	16		T186	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T107	1		T102	14		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	1		T98	6		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T18	18		T187	1		T101	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	14		T117	1		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T105	1		T163	15		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	6		T157	3		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T32	1		T163	4		T102	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T21	1		T107	1		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T147	18		T286	11		T320	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T321	10		T293	13		T322	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T194	8		T295	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T210	4		T235	4		T318	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T20	14		T186	1		T164	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T108	1		T195	9		T236	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T21	6		T94	1		T211	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T94	1		T157	11		T199	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T19	6		T105	5		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T138	13		T195	8		T111	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T32	8		T103	1		T158	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T13	13		T17	10		T22	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T21	3		T100	14		T186	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T195	8		T118	3		T239	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T21	1		T98	3		T117	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T101	2		T109	6		T196	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T35	13		T117	2		T152	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T105	4		T163	2		T46	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T46	2		T157	2		T298	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T163	10		T220	11		T211	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T21	2		T211	11		T197	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6