Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22108

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3719

1

T14

2

T18

18

T19

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19949

1

T5

1

T23

1

T24

1

auto[1]

5878

1

T13

15

T14

3

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	328	1			T110	1		T199	20		T191	11
values[0]	21	1			T323	1		T233	20		-	-
values[1]	722	1			T94	3		T33	5		T187	1
values[2]	680	1			T21	2		T105	5		T127	1
values[3]	589	1			T18	18		T20	15		T21	8
values[4]	795	1			T19	19		T117	13		T138	14
values[5]	443	1			T14	1		T34	7		T98	9
values[6]	529	1			T21	15		T94	5		T186	6
values[7]	722	1			T21	3		T32	21		T102	22
values[8]	2477	1			T13	15		T14	1		T15	23
values[9]	1177	1			T14	1		T19	7		T94	2
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	695	1			T94	3		T33	5		T163	17
values[1]	689	1			T18	18		T20	15		T21	2
values[2]	612	1			T21	8		T138	14		T32	1
values[3]	655	1			T19	19		T98	9		T117	13
values[4]	480	1			T14	1		T34	7		T186	2
values[5]	631	1			T21	15		T94	5		T32	21
values[6]	2530	1			T13	15		T15	23		T16	24
values[7]	813	1			T14	1		T35	27		T94	2
values[8]	1042	1			T14	1		T19	7		T105	6
values[9]	112	1			T200	1		T113	29		T248	12
minimum	17568	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	3		T163	3		T101	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T94	2		T187	2		T109	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T20	15		T21	2		T105	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T18	1		T127	1		T163	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T138	14		T208	7		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T21	5		T32	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T127	1		T140	2		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T19	9		T98	5		T117	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T107	1		T195	9		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	1		T34	4		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T21	8		T94	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T32	12		T186	2		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T13	15		T15	3		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T102	1		T109	7		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	14		T94	2		T117	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T100	15		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T14	1		T46	3		T108	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T19	4		T105	6		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T200	1		T113	14		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T248	3		T123	1		T133	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17233	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T141	1		T196	17		T224	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	2		T163	14		T101	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T94	1		T109	10		T118	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T140	2		T164	4		T202	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T18	17		T163	3		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T200	17		T121	10		T235	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T21	3		T195	8		T211	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T46	10		T227	4		T228	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T19	10		T98	4		T147	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T195	9		T50	3		T118	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T34	3		T186	1		T216	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	7		T94	2		T147	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T32	9		T186	4		T201	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T15	20		T16	21		T53	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T102	15		T109	6		T118	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	13		T197	15		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T100	15		T231	11		T275	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T46	5		T108	2		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T19	3		T108	2		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T113	15		T194	1		T232	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T248	9		T123	6		T133	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T196	16		T303	4		T205	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T110	1		T199	6		T194	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T191	5		T243	1		T192	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T233	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T33	3		T101	6		T103	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T94	2		T187	1		T109	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T21	2		T105	5		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T127	1		T163	11		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T20	15		T208	7		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	1		T21	5		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T138	14		T140	2		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T19	9		T117	13		T211	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T127	1		T107	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T34	4		T98	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T21	8		T94	3		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T186	2		T201	1		T234	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T21	3		T102	1		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T32	12		T102	1		T109	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T13	15		T15	3		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T100	15		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T14	1		T94	2		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T19	4		T105	6		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T199	14		T194	1		T252	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T191	6		T192	10		T248	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T233	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	2		T101	1		T103	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T94	1		T109	10		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T140	2		T163	14		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T163	3		T102	13		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T200	17		T199	12		T121	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	17		T21	3		T195	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	10		T227	4		T239	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T19	10		T211	16		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T50	3		T118	2		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T34	3		T98	4		T186	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T21	7		T94	2		T195	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T186	4		T201	7		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T102	5		T198	7		T275	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T32	9		T102	15		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T15	20		T16	21		T53	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T100	15		T214	4		T180	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	5		T108	2		T188	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T19	3		T108	2		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	4		T163	15		T101	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T94	2		T187	2		T109	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T20	1		T21	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T18	18		T127	1		T163	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	1		T208	1		T200	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T21	5		T32	1		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T127	1		T140	2		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	13		T98	6		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T107	1		T195	10		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T34	7		T186	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	9		T94	4		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T32	13		T186	5		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T13	2		T15	23		T16	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T102	16		T109	7		T118	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T35	14		T94	2		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	1		T100	16		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	1		T46	6		T108	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T19	7		T105	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T200	1		T113	16		T194	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T248	10		T123	7		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17378	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T141	1		T196	17		T224	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T33	1		T163	2		T101	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T94	1		T118	3		T211	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T20	14		T21	1		T105	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T163	10		T195	9		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T138	13		T208	6		T121	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T21	3		T195	8		T211	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T46	10		T240	5		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	6		T98	3		T117	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T195	8		T118	1		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T220	11		T216	8		T192	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T21	6		T94	1		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T32	8		T186	1		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	851	1			T13	13		T17	10		T21	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T109	6		T111	15		T113	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	13		T117	2		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T100	14		T221	4		T231	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T46	2		T217	11		T199	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T105	5		T108	1		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T113	13		T232	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T248	2		T133	10		T142	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T157	8		T160	2		T324	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T196	16		T266	10		T222	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T110	1		T199	15		T194	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T191	7		T243	1		T192	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T233	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	4		T101	5		T103	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T94	2		T187	1		T109	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T21	1		T105	1		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T127	1		T163	4		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	1		T208	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T18	18		T21	5		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T138	1		T140	2		T46	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	13		T117	1		T211	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T127	1		T107	1		T50	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	1		T34	7		T98	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T21	9		T94	4		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T186	5		T201	8		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T21	1		T102	6		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T32	13		T102	16		T109	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T13	2		T15	23		T16	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	1		T100	16		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T14	1		T94	2		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T19	7		T105	1		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T199	5		T252	11		T161	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T191	4		T192	12		T248	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T233	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T33	1		T101	2		T103	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T94	1		T211	12		T196	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	1		T105	4		T140	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T163	10		T195	9		T118	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T20	14		T208	6		T199	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T21	3		T195	8		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T138	13		T46	10		T239	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T19	6		T117	12		T211	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T118	1		T157	2		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T98	3		T220	11		T217	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	6		T94	1		T195	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T186	1		T234	13		T237	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T21	2		T226	9		T111	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T32	8		T109	6		T111	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	881	1			T13	13		T17	10		T22	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T100	14		T221	4		T217	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T46	2		T217	11		T113	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T105	5		T108	1		T130	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6