Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20570

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

5257

1

T13

15

T14

2

T15

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20638

1

T5

1

T23

1

T24

1

auto[1]

5189

1

T13

15

T14

3

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	365	1			T33	1		T101	7		T211	30
values[0]	10	1			T114	2		T247	6		T325	2
values[1]	520	1			T14	1		T34	7		T187	1
values[2]	601	1			T14	1		T21	15		T117	3
values[3]	882	1			T18	18		T20	15		T21	3
values[4]	657	1			T94	3		T127	2		T187	1
values[5]	635	1			T94	5		T100	30		T140	9
values[6]	576	1			T14	1		T19	19		T21	8
values[7]	723	1			T105	6		T138	14		T186	2
values[8]	846	1			T19	7		T105	1		T32	21
values[9]	2668	1			T13	15		T15	23		T16	24
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	459	1			T186	6		T104	1		T195	12
values[1]	2599	1			T13	15		T14	1		T15	23
values[2]	830	1			T18	18		T20	15		T117	13
values[3]	649	1			T94	3		T127	2		T140	9
values[4]	665	1			T19	19		T94	5		T100	30
values[5]	605	1			T14	1		T21	8		T35	27
values[6]	793	1			T105	6		T186	4		T107	2
values[7]	635	1			T19	7		T105	1		T32	21
values[8]	915	1			T21	2		T98	9		T33	1
values[9]	182	1			T195	17		T211	30		T112	1
minimum	17495	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T104	1		T130	12		T199	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T186	2		T195	10		T118	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	3		T117	3		T105	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1250	1			T13	15		T14	1		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T20	15		T117	13		T108	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T18	1		T187	1		T216	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T127	1		T140	7		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T94	2		T127	1		T108	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T19	9		T100	15		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T94	3		T163	3		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T21	5		T94	2		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	1		T35	14		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T105	6		T186	1		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T186	2		T107	1		T102	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	12		T107	1		T163	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T19	4		T105	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T21	2		T98	5		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T102	1		T48	1		T195	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T195	9		T112	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T211	14		T131	1		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17224	1			T14	1		T18	50		T19	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T34	4		T48	1		T157	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T130	11		T199	14		T180	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T186	4		T195	2		T118	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	2		T103	4		T109	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	952	1			T15	20		T16	21		T21	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T108	2		T118	10		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T18	17		T216	9		T180	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T140	2		T50	3		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T94	1		T108	2		T118	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T19	10		T100	15		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T94	2		T163	14		T102	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T21	3		T46	5		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T35	13		T46	10		T246	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T186	1		T158	8		T253	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T102	5		T109	10		T147	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T32	9		T163	3		T189	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	3		T211	10		T239	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T98	4		T101	1		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T102	15		T195	9		T147	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T195	8		T328	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T211	16		T131	10		T254	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T34	3		T157	12		T197	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T33	1		T101	6		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T211	14		T224	1		T147	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T114	1		T325	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T14	1		T104	1		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T34	4		T187	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T117	3		T105	5		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T21	8		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T20	15		T21	3		T117	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T18	1		T119	1		T216	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T127	1		T50	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T94	2		T127	1		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T100	15		T140	7		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T94	3		T163	3		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T19	9		T21	5		T94	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T35	14		T242	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T105	6		T107	1		T46	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	14		T186	2		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	12		T186	1		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T19	4		T105	1		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T21	2		T98	5		T108	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1281	1			T13	15		T15	3		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T101	1		T228	11		T298	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T211	16		T147	13		T254	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T114	1		T325	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T247	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T147	2		T130	11		T199	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	3		T195	2		T157	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T33	2		T103	4		T231	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T21	7		T186	4		T118	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T109	6		T108	2		T118	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	17		T216	9		T180	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T50	3		T131	12		T244	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T94	1		T108	2		T118	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T100	15		T140	2		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T94	2		T163	14		T102	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T19	10		T21	3		T181	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	13		T50	2		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	5		T253	3		T210	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T102	5		T46	10		T235	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T32	9		T186	1		T163	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T19	3		T109	10		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T98	4		T195	8		T188	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T15	20		T16	21		T53	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T104	1		T130	12		T199	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T186	5		T195	3		T118	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T21	1		T117	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1273	1			T13	2		T14	1		T15	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T20	1		T117	1		T108	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T18	18		T187	1		T216	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T127	1		T140	7		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T94	2		T127	1		T108	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T19	13		T100	16		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T94	4		T163	15		T102	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	5		T94	2		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	1		T35	14		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T105	1		T186	2		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T186	1		T107	1		T102	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T32	13		T107	1		T163	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T19	7		T105	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T21	1		T98	6		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T102	16		T48	1		T195	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T195	9		T112	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T211	17		T131	11		T327	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17369	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T34	7		T48	1		T157	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T130	11		T199	5		T148	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T186	1		T195	9		T118	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	2		T117	2		T105	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	929	1			T13	13		T17	10		T21	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T20	14		T117	12		T108	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T216	8		T180	1		T191	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T140	2		T208	6		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T94	1		T220	11		T111	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T19	6		T100	14		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T94	1		T163	2		T309	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T21	3		T46	2		T152	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	13		T138	13		T46	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T105	5		T158	6		T253	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T186	1		T147	18		T235	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T32	8		T163	10		T202	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T211	11		T217	3		T239	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T21	1		T98	3		T101	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T195	8		T147	12		T199	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T195	8		T270	1		T328	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T211	13		T254	13		T302	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T147	2		T329	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T157	11		T197	10		T237	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T33	1		T101	5		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T211	17		T224	1		T147	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T114	2		T325	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T247	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T104	1		T147	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	7		T187	1		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T117	1		T105	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T21	9		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T20	1		T21	1		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T18	18		T119	1		T216	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T127	1		T50	4		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T94	2		T127	1		T187	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T100	16		T140	7		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T94	4		T163	15		T102	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	13		T21	5		T94	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T35	14		T242	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T105	1		T107	1		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T138	1		T186	1		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T32	13		T186	2		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T19	7		T105	1		T109	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T21	1		T98	6		T108	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T13	2		T15	23		T16	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T101	2		T190	16		T298	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T211	13		T147	12		T254	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T147	2		T130	11		T199	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T195	9		T157	11		T197	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T117	2		T105	4		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	6		T186	1		T118	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T20	14		T21	2		T117	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T216	8		T180	1		T191	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T244	11		T170	1		T184	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T94	1		T220	11		T111	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T100	14		T140	2		T164	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T94	1		T163	2		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T19	6		T21	3		T181	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	13		T207	13		T246	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T105	5		T46	2		T253	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T138	13		T186	1		T46	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	8		T163	10		T202	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T211	11		T147	18		T217	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T21	1		T98	3		T108	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	950	1			T13	13		T17	10		T22	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6