Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20529

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

5298

1

T13

15

T14

2

T15

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20609

1

T5

1

T23

1

T24

1

auto[1]

5218

1

T13

15

T14

3

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	57	1			T101	7		T141	1		T190	17
values[0]	23	1			T34	7		T247	6		T325	2
values[1]	492	1			T14	1		T187	1		T48	1
values[2]	651	1			T14	1		T21	15		T117	3
values[3]	882	1			T18	18		T20	15		T21	3
values[4]	698	1			T94	3		T127	1		T163	17
values[5]	588	1			T94	5		T100	30		T127	1
values[6]	539	1			T14	1		T19	19		T35	27
values[7]	721	1			T21	8		T94	2		T105	6
values[8]	894	1			T19	7		T105	1		T32	21
values[9]	2938	1			T13	15		T15	23		T16	24
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	558	1			T34	7		T186	6		T48	1
values[1]	2670	1			T13	15		T14	1		T15	23
values[2]	765	1			T18	18		T20	15		T187	1
values[3]	617	1			T117	13		T127	2		T140	9
values[4]	695	1			T19	19		T94	8		T100	30
values[5]	597	1			T14	1		T21	8		T35	27
values[6]	730	1			T105	6		T186	4		T107	2
values[7]	744	1			T19	7		T105	1		T32	21
values[8]	778	1			T21	2		T98	9		T33	1
values[9]	289	1			T108	3		T211	30		T147	26
minimum	17384	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T195	10		T147	3		T130	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T34	4		T186	2		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T21	3		T117	3		T105	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1265	1			T13	15		T14	1		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T20	15		T118	4		T211	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	1		T187	1		T108	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T117	13		T127	1		T140	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T127	1		T52	1		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T19	9		T100	15		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T94	5		T163	3		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T21	5		T94	2		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	1		T35	14		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T105	6		T186	1		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T186	2		T107	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	12		T107	1		T163	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T19	4		T105	1		T109	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T21	2		T98	5		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T102	1		T48	1		T195	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T108	3		T112	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T211	14		T147	13		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17203	1			T14	1		T18	50		T19	131
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T197	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T195	2		T147	2		T130	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T34	3		T186	4		T118	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T33	2		T103	4		T109	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	984	1			T15	20		T16	21		T21	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T118	10		T211	11		T263	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T18	17		T108	2		T118	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T140	2		T50	3		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T236	13		T231	11		T200	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T19	10		T100	15		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T94	3		T163	14		T102	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T21	3		T46	5		T198	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T35	13		T46	10		T246	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T186	1		T158	8		T253	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T102	5		T235	3		T245	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T32	9		T163	3		T189	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T19	3		T109	10		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T98	4		T101	1		T195	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T102	15		T195	9		T197	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T330	15		T331	4		T328	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T211	16		T147	13		T131	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T197	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T101	6		T190	17		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T141	1		T332	10		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T325	1		T322	3		T333	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T34	4		T247	2		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	1		T104	1		T195	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T187	1		T48	1		T157	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T117	3		T105	5		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T21	8		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T20	15		T21	3		T117	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	1		T119	1		T284	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T50	1		T110	1		T164	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T94	2		T127	1		T163	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T100	15		T127	1		T140	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T94	3		T102	1		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T19	9		T46	3		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T35	14		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T21	5		T94	2		T105	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	14		T186	2		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T32	12		T186	1		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T19	4		T105	1		T109	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T21	2		T98	5		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1377	1			T13	15		T15	3		T16	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T101	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T332	10		T334	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T325	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T34	3		T247	4		T150	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T195	2		T147	2		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T157	12		T197	14		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	2		T103	4		T113	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T21	7		T186	4		T118	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T109	6		T108	2		T118	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T18	17		T216	9		T180	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T50	3		T164	4		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T94	1		T163	14		T108	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T100	15		T140	2		T196	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T94	2		T102	13		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	10		T46	5		T181	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T35	13		T50	2		T246	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T21	3		T157	2		T253	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T102	5		T46	10		T235	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	9		T186	1		T163	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	3		T109	10		T211	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T98	4		T195	8		T188	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1137	1			T15	20		T16	21		T53	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T195	3		T147	3		T130	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	7		T186	5		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T21	1		T117	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T13	2		T14	1		T15	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T20	1		T118	11		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T18	18		T187	1		T108	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T117	1		T127	1		T140	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T127	1		T52	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T19	13		T100	16		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T94	6		T163	15		T102	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	5		T94	2		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	1		T35	14		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T105	1		T186	2		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T186	1		T107	1		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T32	13		T107	1		T163	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T19	7		T105	1		T109	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T21	1		T98	6		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T102	16		T48	1		T195	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T108	2		T112	1		T326	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T211	17		T147	14		T131	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17359	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T197	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T195	9		T147	2		T130	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T186	1		T118	1		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T21	2		T117	2		T105	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	938	1			T13	13		T17	10		T21	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	14		T118	3		T211	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T216	8		T180	1		T191	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T117	12		T140	2		T208	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T220	11		T158	13		T111	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T19	6		T100	14		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T94	2		T163	2		T309	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T21	3		T46	2		T210	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	13		T138	13		T46	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T105	5		T158	6		T152	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T186	1		T235	4		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	8		T163	10		T202	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T211	11		T147	18		T217	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T21	1		T98	3		T101	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T195	8		T199	14		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T108	1		T330	15		T270	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T211	13		T147	12		T254	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T197	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T101	5		T190	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T141	1		T332	11		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T325	2		T322	1		T333	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T34	7		T247	6		T150	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	1		T104	1		T195	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T187	1		T48	1		T157	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T117	1		T105	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	1		T21	9		T140	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T20	1		T21	1		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	18		T119	1		T284	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	4		T110	1		T164	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T94	2		T127	1		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T100	16		T127	1		T140	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T94	4		T102	14		T189	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	13		T46	6		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T35	14		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T21	5		T94	2		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T138	1		T186	1		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T32	13		T186	2		T107	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T19	7		T105	1		T109	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T21	1		T98	6		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1482	1			T13	2		T15	23		T16	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T101	2		T190	16		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T332	9		T334	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T322	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T195	9		T147	2		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T157	11		T197	10		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T117	2		T105	4		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	6		T186	1		T118	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T20	14		T21	2		T117	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T216	8		T180	1		T240	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T164	1		T244	11		T170	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T94	1		T163	2		T220	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T100	14		T140	2		T196	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T94	1		T158	13		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T19	6		T46	2		T181	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T35	13		T207	13		T246	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	3		T105	5		T157	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	13		T186	1		T46	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	8		T163	10		T202	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T211	11		T147	18		T217	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T21	1		T98	3		T108	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1032	1			T13	13		T17	10		T22	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6