Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22449

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3378

1

T14

1

T19

19

T20

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19966

1

T5

1

T23

1

T24

1

auto[1]

5861

1

T13

15

T14

2

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	751	1			T19	10		T21	21		T34	3
values[0]	31	1			T19	7		T206	15		T126	1
values[1]	510	1			T19	19		T21	18		T102	20
values[2]	2582	1			T13	15		T14	1		T15	23
values[3]	547	1			T94	3		T138	14		T32	1
values[4]	536	1			T14	2		T140	2		T186	6
values[5]	666	1			T21	8		T107	1		T109	12
values[6]	857	1			T20	15		T127	1		T186	2
values[7]	577	1			T105	6		T127	1		T140	9
values[8]	733	1			T21	2		T34	7		T94	7
values[9]	1144	1			T18	18		T100	30		T33	5
minimum	16893	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	583	1			T19	19		T35	27		T33	1
values[1]	2462	1			T13	15		T14	1		T15	23
values[2]	635	1			T14	1		T94	3		T138	14
values[3]	585	1			T14	1		T140	2		T186	6
values[4]	737	1			T21	8		T109	12		T108	5
values[5]	614	1			T20	15		T127	1		T186	2
values[6]	721	1			T105	6		T127	1		T140	9
values[7]	729	1			T21	2		T34	7		T94	7
values[8]	1057	1			T18	18		T100	30		T33	5
values[9]	177	1			T196	33		T224	1		T119	1
minimum	17527	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T33	1		T102	1		T157	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	9		T35	14		T46	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T13	15		T15	3		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T117	3		T105	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	1		T94	2		T101	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T138	14		T104	1		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	1		T140	2		T163	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T186	2		T107	2		T46	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	5		T108	3		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T109	2		T211	14		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T127	1		T48	1		T242	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T20	15		T186	2		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	1		T102	1		T226	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T105	6		T140	7		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T34	4		T94	2		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T21	2		T94	3		T98	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T18	1		T100	15		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T187	1		T258	1		T231	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T224	1		T261	1		T281	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T196	17		T119	1		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17271	1			T18	50		T19	135		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T21	11		T102	1		T118	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T102	5		T157	11		T181	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	10		T35	13		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T15	20		T16	21		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T202	11		T147	2		T212	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T94	1		T101	1		T103	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T189	7		T253	3		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T163	14		T195	9		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T186	4		T46	5		T147	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T21	3		T108	2		T50	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T109	10		T211	16		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T200	17		T193	18		T161	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T197	14		T263	12		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T102	15		T246	8		T131	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T140	2		T32	9		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T34	3		T109	6		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T94	2		T98	4		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T18	17		T100	15		T33	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T231	10		T131	12		T244	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T261	2		T341	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T196	16		T131	12		T125	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T21	7		T102	13		T118	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	572	1			T19	10		T21	21		T34	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T119	1		T131	1		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T19	4		T272	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T206	9		T126	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T102	1		T157	3		T181	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T19	9		T21	11		T102	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T13	15		T15	3		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T35	14		T117	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T94	2		T101	7		T103	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	14		T32	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	2		T140	2		T163	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T186	2		T107	1		T46	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T21	5		T108	3		T195	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T107	1		T109	2		T211	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T127	1		T48	1		T242	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T20	15		T186	2		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T127	1		T102	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T105	6		T140	7		T32	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	4		T94	2		T117	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T21	2		T94	3		T98	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T18	1		T100	15		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T187	2		T188	1		T211	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16750	1			T18	50		T19	121		T21	402
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T118	2		T211	10		T212	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T131	12		T123	6		T125	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T19	3		T272	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T206	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T102	5		T157	2		T181	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T19	10		T21	7		T102	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T15	20		T16	21		T53	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	13		T202	11		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T94	1		T101	1		T103	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T189	7		T253	3		T180	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T163	14		T199	14		T288	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T186	4		T46	5		T147	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T21	3		T108	2		T195	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T109	10		T211	16		T230	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T236	13		T200	17		T121	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T197	14		T263	12		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T102	15		T131	10		T275	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	2		T32	9		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	3		T109	6		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T94	2		T98	4		T121	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T18	17		T100	15		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T188	2		T211	11		T196	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T33	1		T102	6		T157	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	13		T35	14		T46	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T13	2		T15	23		T16	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	1		T117	1		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	1		T94	2		T101	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T138	1		T104	1		T189	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	1		T140	2		T163	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T186	5		T107	2		T46	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T21	5		T108	4		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T109	12		T211	17		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T127	1		T48	1		T242	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T20	1		T186	1		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T127	1		T102	16		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T105	2		T140	7		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T34	7		T94	2		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	1		T94	4		T98	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T18	18		T100	16		T33	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T187	1		T258	1		T231	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T224	1		T261	3		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T196	17		T119	1		T131	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17399	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T21	10		T102	14		T118	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T157	10		T181	4		T158	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T19	6		T35	13		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T13	13		T17	10		T22	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T117	2		T105	5		T202	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T94	1		T101	2		T103	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	13		T111	15		T253	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T163	2		T195	8		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T186	1		T46	2		T147	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T21	3		T108	1		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T211	13		T262	13		T240	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T152	8		T190	13		T193	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T20	14		T186	1		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T226	9		T246	7		T317	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T105	4		T140	2		T32	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T117	12		T109	6		T111	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T21	1		T94	1		T98	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T100	14		T33	1		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T231	9		T246	10		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T281	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T196	16		T125	13		T342	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T221	1		T231	8		T245	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T21	8		T343	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	550	1			T19	10		T21	21		T34	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T119	1		T131	13		T123	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T19	7		T272	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T206	8		T126	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T102	6		T157	3		T181	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	13		T21	10		T102	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T13	2		T15	23		T16	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T35	14		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T94	2		T101	6		T103	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T138	1		T32	1		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	2		T140	2		T163	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T186	5		T107	1		T46	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T21	5		T108	4		T195	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T107	1		T109	12		T211	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T127	1		T48	1		T242	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T20	1		T186	1		T197	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T127	1		T102	16		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T105	2		T140	7		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T34	7		T94	2		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T21	1		T94	4		T98	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T18	18		T100	16		T33	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T187	2		T188	3		T211	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16893	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T118	1		T211	11		T212	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T125	13		T342	10		T313	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T272	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T206	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T157	2		T181	4		T221	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T19	6		T21	8		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T13	13		T17	10		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T35	13		T117	2		T105	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T94	1		T101	2		T103	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T138	13		T111	15		T253	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T163	2		T208	6		T199	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T186	1		T46	2		T147	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T21	3		T108	1		T195	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T211	13		T262	13		T317	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T236	14		T152	8		T121	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T20	14		T186	1		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T317	8		T286	17		T342	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T105	4		T140	2		T32	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T117	12		T109	6		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T21	1		T94	1		T98	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T100	14		T33	1		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T211	12		T196	16		T221	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6