Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22254

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3573

1

T14

1

T18

18

T19

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20195

1

T5

1

T23

1

T24

1

auto[1]

5632

1

T13

15

T14

2

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	247	1			T19	7		T208	7		T147	33
values[0]	44	1			T33	1		T205	9		T241	17
values[1]	646	1			T14	1		T20	15		T35	27
values[2]	2634	1			T13	15		T15	23		T16	24
values[3]	611	1			T105	5		T100	30		T163	17
values[4]	782	1			T19	19		T127	1		T109	1
values[5]	458	1			T107	1		T187	1		T46	8
values[6]	819	1			T21	2		T34	7		T94	2
values[7]	616	1			T14	2		T94	5		T127	1
values[8]	778	1			T105	1		T140	9		T186	2
values[9]	848	1			T18	18		T21	15		T140	2
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	683	1			T14	1		T20	15		T35	27
values[1]	2590	1			T13	15		T15	23		T16	24
values[2]	699	1			T105	5		T100	30		T187	1
values[3]	703	1			T19	19		T127	1		T109	1
values[4]	523	1			T117	13		T107	1		T187	1
values[5]	777	1			T14	1		T21	2		T34	7
values[6]	693	1			T14	1		T94	5		T127	1
values[7]	670	1			T105	1		T140	2		T187	1
values[8]	856	1			T18	18		T19	7		T21	15
values[9]	115	1			T119	1		T147	26		T237	19
minimum	17518	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	14		T94	2		T163	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	1		T20	15		T117	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T13	15		T15	3		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	8		T105	6		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T105	5		T187	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T100	15		T50	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T127	1		T109	1		T242	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	9		T195	10		T226	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T187	1		T46	3		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T117	13		T107	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	1		T98	5		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T21	2		T34	4		T94	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T109	7		T108	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T94	3		T127	1		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T140	2		T108	2		T195	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T105	1		T187	1		T118	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T19	4		T21	8		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T18	1		T32	12		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T119	1		T159	1		T302	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T147	13		T237	17		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17233	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T107	1		T110	1		T190	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	13		T94	1		T163	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T46	10		T236	13		T199	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T15	20		T16	21		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T21	3		T163	14		T189	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	2		T118	7		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T100	15		T50	3		T147	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T216	9		T245	3		T303	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T19	10		T195	2		T246	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	5		T211	11		T253	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T157	2		T197	15		T229	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T98	4		T33	2		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	3		T109	10		T188	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T109	6		T157	12		T197	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T94	2		T140	2		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	2		T195	9		T202	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T118	2		T199	12		T216	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	3		T21	7		T101	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T18	17		T32	9		T195	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T302	16		T255	13		T297	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T147	13		T237	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T241	7		T206	17		T344	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T19	4		T170	3		T251	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T208	7		T147	19		T221	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T33	1		T205	1		T153	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T241	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T35	14		T94	2		T163	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	1		T20	15		T117	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T13	15		T15	3		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	8		T105	6		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T105	5		T187	1		T102	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T100	15		T163	3		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T127	1		T109	1		T242	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T19	9		T195	10		T226	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T187	1		T46	3		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T107	1		T104	1		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T98	5		T33	3		T186	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T21	2		T34	4		T94	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	2		T109	7		T157	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T94	3		T127	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T108	3		T195	9		T202	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T105	1		T140	7		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	8		T140	2		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T18	1		T32	12		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T19	3		T170	2		T251	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T147	14		T278	13		T150	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T205	8		T153	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T241	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	13		T94	1		T163	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T199	7		T251	9		T252	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T15	20		T16	21		T53	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	3		T46	10		T189	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T102	5		T118	7		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T100	15		T163	14		T50	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	2		T216	9		T244	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	10		T195	2		T246	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T46	5		T211	11		T253	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T197	15		T229	12		T114	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T98	4		T33	2		T186	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T34	3		T109	10		T211	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T109	6		T157	12		T197	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T94	2		T188	2		T118	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T195	9		T202	11		T263	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T140	2		T186	1		T108	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	7		T101	1		T102	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T18	17		T32	9		T195	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	14		T94	2		T163	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T20	1		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T13	2		T15	23		T16	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T21	6		T105	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T105	1		T187	1		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T100	16		T50	4		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T127	1		T109	1		T242	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T19	13		T195	3		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T187	1		T46	6		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T117	1		T107	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T14	1		T98	6		T33	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T21	1		T34	7		T94	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	1		T109	7		T108	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T94	4		T127	1		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T140	2		T108	4		T195	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T105	1		T187	1		T118	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T19	7		T21	9		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T18	18		T32	13		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T119	1		T159	1		T302	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T147	14		T237	3		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17392	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T107	1		T110	1		T190	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	13		T94	1		T163	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	14		T117	2		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	878	1			T13	13		T17	10		T22	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	5		T105	5		T138	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T105	4		T130	11		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T100	14		T147	2		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T216	8		T234	13		T245	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	6		T195	9		T226	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T46	2		T211	12		T253	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T117	12		T157	2		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T98	3		T33	1		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	1		T211	13		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T109	6		T108	1		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T94	1		T140	2		T108	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T195	8		T202	6		T199	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T118	1		T199	14		T216	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T21	6		T101	2		T103	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T32	8		T195	8		T196	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T302	11		T255	5		T345	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T147	12		T237	16		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T222	2		T346	2		T153	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T190	16		T241	6		T206	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T19	7		T170	4		T251	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T208	1		T147	15		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T33	1		T205	9		T153	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T241	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	14		T94	2		T163	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	1		T20	1		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T13	2		T15	23		T16	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T21	6		T105	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T105	1		T187	1		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T100	16		T163	15		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T127	1		T109	1		T242	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T19	13		T195	3		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T187	1		T46	6		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T107	1		T104	1		T197	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T98	6		T33	4		T186	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	1		T34	7		T94	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	2		T109	7		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T94	4		T127	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T108	2		T195	10		T202	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T105	1		T140	7		T186	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T21	9		T140	2		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T18	18		T32	13		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T170	1		T133	12		T267	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T208	6		T147	18		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T153	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T241	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T35	13		T94	1		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T20	14		T117	2		T158	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T13	13		T17	10		T22	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T21	5		T105	5		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T105	4		T158	6		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T100	14		T163	2		T147	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T216	8		T234	13		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	6		T195	9		T226	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T46	2		T211	12		T253	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T229	9		T190	13		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T98	3		T33	1		T186	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	1		T117	12		T211	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T109	6		T157	11		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T94	1		T118	3		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T108	1		T195	8		T202	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	2		T108	1		T118	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T21	6		T101	2		T103	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T32	8		T195	8		T196	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6