Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T33	4		T163	15		T101	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T94	2		T127	1		T187	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T21	1		T105	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T18	18		T163	4		T195	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T208	1		T200	18		T199	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	5		T138	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T127	1		T140	2		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	13		T34	7		T98	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T94	4		T107	1		T195	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T117	1		T186	2		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T21	9		T48	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T14	1		T32	13		T186	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T13	2		T15	23		T16	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T102	16		T109	7		T118	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T35	14		T94	2		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	1		T100	16		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	1		T46	6		T108	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T19	7		T105	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T200	1		T113	16		T194	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T123	7		T161	3		T133	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17360	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T33	1		T163	2		T101	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T94	1		T118	3		T211	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T20	14		T21	1		T105	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T163	10		T195	9		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T208	6		T199	14		T121	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	3		T138	13		T195	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T46	10		T235	4		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	6		T98	3		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T94	1		T195	8		T118	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T117	12		T220	11		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	6		T226	9		T147	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T32	8		T186	1		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	857	1			T13	13		T17	10		T21	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T109	6		T111	15		T113	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	13		T117	2		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T100	14		T221	4		T231	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T46	2		T217	11		T199	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T105	5		T108	1		T130	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T113	13		T222	2		T232	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T133	10		T142	8		T225	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T238	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T225	1		T233	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T196	17		T224	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T33	5		T101	5		T103	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T94	2		T127	1		T109	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	1		T105	1		T140	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T163	4		T187	2		T195	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T20	1		T208	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	18		T21	5		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T46	11		T200	18		T227	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	13		T117	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T94	4		T127	1		T140	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T34	7		T98	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	10		T48	1		T195	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T201	8		T234	1		T227	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T102	6		T104	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T32	13		T102	16		T109	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T13	2		T15	23		T16	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T100	16		T111	1		T214	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T14	1		T94	2		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	507	1			T14	1		T19	7		T105	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T233	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T196	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T33	1		T101	2		T103	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T94	1		T211	12		T147	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	1		T105	4		T140	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T163	10		T195	9		T118	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T20	14		T208	6		T199	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T21	3		T195	8		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T46	10		T239	14		T240	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T19	6		T117	12		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T94	1		T118	1		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T98	3		T186	1		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T21	8		T195	8		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T234	13		T237	2		T148	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T226	9		T147	18		T111	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T32	8		T109	6		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	895	1			T13	13		T17	10		T22	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T100	14		T111	15		T240	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T46	2		T217	11		T199	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T105	5		T108	1		T130	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6