Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22505

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3322

1

T14

1

T18

18

T19

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20201

1

T5

1

T23

1

T24

1

auto[1]

5626

1

T13

15

T14

2

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37	1			T255	19		T256	4		T257	13
values[1]	659	1			T14	1		T138	14		T140	2
values[2]	772	1			T21	3		T98	9		T117	3
values[3]	813	1			T21	15		T35	27		T100	30
values[4]	2414	1			T13	15		T15	23		T16	24
values[5]	718	1			T18	18		T108	4		T50	3
values[6]	646	1			T19	19		T127	1		T107	1
values[7]	613	1			T14	1		T19	7		T20	15
values[8]	809	1			T21	10		T94	2		T105	5
values[9]	1002	1			T14	1		T94	5		T32	21
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	829	1			T14	1		T21	3		T117	3
values[1]	910	1			T98	9		T127	1		T140	2
values[2]	645	1			T21	15		T35	27		T100	30
values[3]	2487	1			T13	15		T15	23		T16	24
values[4]	736	1			T18	18		T107	1		T108	4
values[5]	584	1			T19	19		T20	15		T127	1
values[6]	699	1			T14	1		T19	7		T117	13
values[7]	682	1			T21	2		T94	7		T127	1
values[8]	768	1			T14	1		T21	8		T105	5
values[9]	132	1			T101	1		T141	1		T111	13
minimum	17355	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T102	1		T104	1		T242	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	1		T21	3		T117	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T101	6		T195	9		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T98	5		T127	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T21	8		T107	2		T103	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	14		T100	15		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T13	15		T15	3		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T105	1		T186	2		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T107	1		T50	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	1		T108	2		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T19	9		T220	12		T245	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T20	15		T127	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T14	1		T117	13		T105	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T19	4		T187	1		T46	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T94	5		T118	2		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T21	2		T127	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T14	1		T105	5		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T21	5		T32	12		T163	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T111	13		T258	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T101	1		T141	1		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17205	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T259	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T102	5		T211	10		T202	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T188	2		T211	16		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T101	1		T195	9		T189	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T98	4		T186	4		T163	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T21	7		T103	4		T210	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T35	13		T100	15		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T15	20		T16	21		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T230	5		T260	13		T261	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T50	2		T158	8		T199	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	17		T108	2		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	10		T245	3		T262	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T50	3		T181	10		T147	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T118	10		T263	12		T113	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T19	3		T46	5		T109	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T94	2		T118	2		T213	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T140	2		T33	2		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T186	1		T46	10		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T21	3		T32	9		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T131	12		T240	11		T205	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T259	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T256	1		T257	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T255	6		T264	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T102	1		T104	1		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	1		T138	14		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T242	2		T189	1		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T21	3		T98	5		T117	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T21	8		T107	1		T101	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	14		T100	15		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T13	15		T15	3		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T105	1		T186	2		T230	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T50	1		T110	1		T196	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	1		T108	2		T211	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T19	9		T107	1		T121	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T127	1		T109	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	1		T117	13		T105	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T19	4		T20	15		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T94	2		T105	5		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T21	7		T140	7		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T14	1		T94	3		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T32	12		T163	3		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T256	3		T257	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T255	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T102	5		T211	10		T202	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T191	6		T266	10		T267	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T189	7		T198	4		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T98	4		T163	3		T102	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T21	7		T101	1		T103	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	13		T100	15		T186	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T15	20		T16	21		T53	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T230	5		T227	4		T268	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T50	2		T196	16		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T18	17		T108	2		T211	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	10		T121	10		T245	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T50	3		T181	10		T147	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T118	10		T263	12		T113	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T19	3		T33	2		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T118	2		T213	3		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	3		T140	2		T102	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T94	2		T186	1		T46	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T32	9		T163	14		T199	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T102	6		T104	1		T242	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T14	1		T21	1		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T101	5		T195	10		T189	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T98	6		T127	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T21	9		T107	2		T103	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	14		T100	16		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T13	2		T15	23		T16	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T105	1		T186	1		T230	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T107	1		T50	3		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T18	18		T108	4		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T19	13		T220	1		T245	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	1		T127	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	1		T117	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T19	7		T187	1		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T94	6		T118	3		T213	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T21	1		T127	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T14	1		T105	1		T186	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T21	5		T32	13		T163	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T111	1		T258	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T101	1		T141	1		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17346	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T259	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T211	11		T202	6		T157	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	2		T117	2		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T101	2		T195	8		T199	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T98	3		T186	1		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T21	6		T103	1		T210	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	13		T100	14		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T13	13		T17	10		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T186	1		T269	12		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T208	6		T158	6		T199	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T211	12		T217	11		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T19	6		T220	11		T245	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T20	14		T181	4		T147	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T117	12		T105	5		T118	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	2		T109	6		T195	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T94	1		T118	1		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T21	1		T140	2		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T105	4		T46	10		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T21	3		T32	8		T163	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T111	12		T124	14		T270	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T271	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T272	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T259	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T256	4		T257	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T255	14		T264	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T102	6		T104	1		T211	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T138	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T242	2		T189	8		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T21	1		T98	6		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	9		T107	1		T101	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T35	14		T100	16		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T13	2		T15	23		T16	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T105	1		T186	1		T230	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T50	3		T110	1		T196	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T18	18		T108	4		T211	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T19	13		T107	1		T121	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T127	1		T109	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	1		T117	1		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T19	7		T20	1		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T94	2		T105	1		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T21	6		T140	7		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T14	1		T94	4		T186	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T32	13		T163	15		T101	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T255	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T211	11		T202	6		T157	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T138	13		T108	1		T207	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T199	14		T219	7		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T21	2		T98	3		T117	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	6		T101	2		T103	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	13		T100	14		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	880	1			T13	13		T17	10		T22	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T186	1		T269	12		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T196	16		T208	6		T158	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T211	12		T217	11		T239	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T19	6		T121	9		T245	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T181	4		T147	18		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T117	12		T105	5		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T20	14		T33	1		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T105	4		T118	1		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T21	4		T140	2		T195	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T94	1		T46	10		T195	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T32	8		T163	2		T158	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6