Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22208

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3619

1

T14

2

T19

19

T21

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20424

1

T5

1

T23

1

T24

1

auto[1]

5403

1

T13

15

T14

1

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T257	13		-	-		-	-
values[0]	23	1			T48	1		T201	1		T273	1
values[1]	588	1			T14	1		T19	7		T21	2
values[2]	806	1			T14	1		T94	3		T127	1
values[3]	725	1			T19	19		T186	6		T103	7
values[4]	780	1			T14	1		T187	1		T164	9
values[5]	2492	1			T13	15		T15	23		T16	24
values[6]	648	1			T18	18		T21	15		T35	27
values[7]	608	1			T195	18		T220	12		T119	1
values[8]	588	1			T21	11		T98	9		T186	2
values[9]	1212	1			T34	7		T94	5		T105	12
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	821	1			T14	1		T19	7		T21	2
values[1]	709	1			T14	1		T94	3		T186	6
values[2]	793	1			T19	19		T104	1		T50	4
values[3]	2670	1			T13	15		T14	1		T15	23
values[4]	539	1			T18	18		T20	15		T21	15
values[5]	617	1			T117	13		T33	1		T102	6
values[6]	620	1			T48	1		T109	24		T195	18
values[7]	580	1			T21	3		T98	9		T105	1
values[8]	852	1			T21	8		T94	5		T105	6
values[9]	231	1			T34	7		T105	5		T33	5
minimum	17395	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	1		T19	4		T21	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T94	2		T127	1		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T94	2		T103	3		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T14	1		T186	2		T46	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T104	1		T181	5		T199	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T19	9		T50	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T13	15		T15	3		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	1		T100	15		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T18	1		T20	15		T117	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T21	8		T35	14		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T117	13		T209	1		T118	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T33	1		T102	1		T118	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T109	8		T195	9		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	1		T130	12		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T98	5		T107	1		T163	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	3		T105	1		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T105	6		T127	1		T211	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T21	5		T94	3		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T34	4		T46	11		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T105	5		T33	3		T186	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17214	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T274	1		T185	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T19	3		T157	12		T231	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T163	3		T108	2		T195	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T94	1		T103	4		T215	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T186	4		T46	5		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T181	10		T199	7		T113	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T19	10		T50	3		T118	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T15	20		T16	21		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T100	15		T32	9		T164	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T18	17		T101	1		T108	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	7		T35	13		T170	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T118	7		T189	7		T228	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T102	5		T118	10		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T109	16		T195	9		T263	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T130	11		T200	17		T199	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T98	4		T163	14		T102	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T186	1		T195	8		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T211	11		T196	16		T244	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	3		T94	2		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T34	3		T46	10		T147	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T33	2		T246	8		T275	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T274	2		T185	4		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T257	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T48	1		T201	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	1		T19	4		T21	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T94	2		T107	1		T108	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T94	2		T109	1		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	1		T127	1		T163	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T103	3		T104	1		T113	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	9		T186	2		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T181	5		T197	1		T199	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T187	1		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T13	15		T15	3		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T100	15		T127	1		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	1		T117	13		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	8		T35	14		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T195	9		T220	12		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	12		T265	1		T200	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T98	5		T102	1		T109	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T21	8		T186	1		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T34	4		T105	6		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T94	3		T105	6		T140	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T257	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T276	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T19	3		T157	12		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T108	2		T195	2		T147	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T94	1		T277	8		T278	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T163	3		T46	5		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T103	4		T113	15		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	10		T186	4		T50	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T181	10		T197	15		T199	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T164	4		T213	3		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	926	1			T15	20		T16	21		T53	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T100	15		T32	9		T147	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T18	17		T101	1		T118	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	7		T35	13		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T195	9		T263	12		T262	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T130	11		T200	17		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T98	4		T102	13		T109	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T21	3		T186	1		T102	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T34	3		T163	14		T46	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T94	2		T140	2		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	1		T19	7		T21	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T94	2		T127	1		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T94	2		T103	6		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	1		T186	5		T46	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T104	1		T181	11		T199	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T19	13		T50	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T13	2		T15	23		T16	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T14	1		T100	16		T32	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	18		T20	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T21	9		T35	14		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T117	1		T209	1		T118	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T33	1		T102	6		T118	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T109	18		T195	10		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T48	1		T130	12		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T98	6		T107	1		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T21	1		T105	1		T186	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T105	1		T127	1		T211	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T21	5		T94	4		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T34	7		T46	11		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T105	1		T33	4		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17364	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T274	3		T185	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T21	1		T157	11		T111	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T163	10		T195	9		T158	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T94	1		T103	1		T207	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T186	1		T46	2		T211	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T181	4		T199	7		T113	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	6		T118	1		T211	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	913	1			T13	13		T17	10		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T100	14		T32	8		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T20	14		T117	2		T101	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T21	6		T35	13		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T117	12		T262	13		T160	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T118	3		T236	14		T247	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T109	6		T195	8		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T130	11		T199	5		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T98	3		T163	2		T202	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T21	2		T195	8		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T105	5		T211	12		T196	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T21	3		T94	1		T140	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T46	10		T147	2		T279	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T105	4		T33	1		T186	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T268	9		T280	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T185	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T257	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T48	1		T201	1		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	1		T19	7		T21	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T94	2		T107	1		T108	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T94	2		T109	1		T51	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	1		T127	1		T163	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T103	6		T104	1		T113	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	13		T186	5		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T181	11		T197	16		T199	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	1		T187	1		T164	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T13	2		T15	23		T16	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T100	16		T127	1		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T18	18		T117	1		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	9		T35	14		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T195	10		T220	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T130	12		T265	1		T200	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T98	6		T102	14		T109	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T21	6		T186	2		T102	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T34	7		T105	1		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T94	4		T105	2		T140	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T281	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T21	1		T157	11		T111	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T195	9		T147	18		T253	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T94	1		T207	13		T277	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T163	10		T46	2		T211	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T103	1		T113	13		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	6		T186	1		T118	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T181	4		T199	7		T212	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T164	1		T221	4		T152	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	863	1			T13	13		T17	10		T20	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T100	14		T32	8		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T117	12		T101	2		T157	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T21	6		T35	13		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T195	8		T220	11		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T130	11		T199	5		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T98	3		T109	6		T202	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T21	5		T195	8		T199	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T105	5		T163	2		T46	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T94	1		T105	4		T140	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6