Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22565

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3262

1

T14

2

T18

18

T19

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20018

1

T5

1

T23

1

T24

1

auto[1]

5809

1

T13

15

T14

1

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T282	9		T283	10		-	-
values[0]	46	1			T127	1		T284	1		T285	1
values[1]	753	1			T20	15		T105	1		T33	1
values[2]	702	1			T34	7		T94	3		T195	12
values[3]	644	1			T14	1		T19	26		T21	15
values[4]	453	1			T14	1		T138	14		T187	1
values[5]	2648	1			T13	15		T14	1		T15	23
values[6]	713	1			T21	2		T117	13		T140	2
values[7]	822	1			T18	18		T35	27		T98	9
values[8]	430	1			T105	5		T163	17		T46	29
values[9]	1253	1			T21	3		T127	1		T32	1
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	887	1			T20	15		T105	1		T127	1
values[1]	817	1			T14	1		T21	15		T34	7
values[2]	586	1			T14	1		T19	26		T94	5
values[3]	2513	1			T13	15		T14	1		T15	23
values[4]	602	1			T21	8		T94	2		T100	30
values[5]	820	1			T21	2		T98	9		T117	16
values[6]	626	1			T18	18		T35	27		T187	1
values[7]	425	1			T105	5		T163	17		T101	1
values[8]	989	1			T127	1		T107	1		T163	14
values[9]	197	1			T21	3		T32	1		T286	12
minimum	17365	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T33	1		T186	2		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T20	15		T105	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T14	1		T108	3		T195	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T21	8		T34	4		T94	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T94	3		T108	2		T195	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T19	13		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T13	15		T15	3		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	1		T32	12		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T140	2		T186	2		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	5		T94	2		T100	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T117	3		T107	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T21	2		T98	5		T117	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T187	1		T101	6		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	1		T35	14		T46	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T105	5		T163	3		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T101	1		T157	3		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T163	11		T46	11		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T127	1		T107	1		T102	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T32	1		T269	13		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T21	3		T286	12		T148	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17207	1			T18	50		T19	131		T21	423
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T102	15		T236	13		T210	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T164	4		T287	2		T288	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T195	2		T157	12		T199	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	7		T34	3		T94	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T94	2		T108	2		T195	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T19	13		T140	2		T108	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T15	20		T16	21		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T32	9		T186	1		T103	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T186	4		T118	10		T198	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T21	3		T100	15		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T102	13		T277	8		T180	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T98	4		T195	8		T118	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T101	1		T109	10		T118	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T18	17		T35	13		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T163	14		T188	2		T191	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T157	2		T199	12		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T163	3		T46	10		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T102	5		T50	3		T189	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T142	10		T289	12		T290	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T291	10		T292	12		T293	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T23	1		T24	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T194	9		T294	3		T295	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T127	1		T284	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T33	1		T186	2		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	15		T105	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T195	10		T208	7		T236	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	4		T94	2		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	1		T94	3		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T19	13		T21	8		T105	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T138	14		T108	2		T195	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T187	1		T103	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T13	15		T15	3		T16	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	1		T21	5		T94	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T140	2		T107	1		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T21	2		T117	13		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T117	3		T187	1		T101	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T18	1		T35	14		T98	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T105	5		T163	3		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T46	3		T48	1		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T32	1		T163	11		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T21	3		T127	1		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T282	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T283	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T194	10		T294	3		T295	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T296	10		T297	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T102	15		T210	3		T113	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T164	4		T287	2		T122	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T195	2		T236	13		T245	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	3		T94	1		T211	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T94	2		T157	12		T213	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T19	13		T21	7		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T108	2		T195	9		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T103	4		T158	8		T263	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	992	1			T15	20		T16	21		T53	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	3		T100	15		T32	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T102	13		T118	10		T198	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T195	8		T147	13		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T101	1		T109	10		T118	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	17		T35	13		T98	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T163	14		T46	10		T188	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	5		T157	2		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T163	3		T50	2		T211	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T102	5		T50	3		T189	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T33	1		T186	1		T102	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T20	1		T105	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T14	1		T108	2		T195	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T21	9		T34	7		T94	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T94	4		T108	4		T195	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T19	20		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T13	2		T15	23		T16	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T32	13		T186	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T140	2		T186	5		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T21	5		T94	2		T100	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T117	1		T107	1		T102	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T21	1		T98	6		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T187	1		T101	5		T109	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	18		T35	14		T46	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T105	1		T163	15		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T101	1		T157	3		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T163	4		T46	11		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T127	1		T107	1		T102	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T32	1		T269	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T21	1		T286	1		T148	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17363	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T186	1		T236	14		T210	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	14		T164	1		T287	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T108	1		T195	9		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T21	6		T94	1		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T94	1		T195	8		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T19	6		T105	5		T140	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T13	13		T17	10		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T32	8		T103	1		T181	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T186	1		T118	3		T239	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T21	3		T100	14		T147	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T117	2		T277	11		T180	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T21	1		T98	3		T117	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T101	2		T226	9		T196	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	13		T46	2		T109	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T105	4		T163	2		T191	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T157	2		T217	11		T199	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T163	10		T46	10		T220	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T211	11		T197	10		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T269	12		T142	11		T289	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T21	2		T286	11		T148	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T270	1		T295	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T282	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T283	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T194	11		T294	4		T295	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T127	1		T284	1		T285	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T33	1		T186	1		T102	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	1		T105	1		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T195	3		T208	1		T236	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T34	7		T94	2		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	1		T94	4		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T19	20		T21	9		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T138	1		T108	4		T195	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	1		T187	1		T103	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T13	2		T15	23		T16	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T14	1		T21	5		T94	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T140	2		T107	1		T102	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T21	1		T117	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T117	1		T187	1		T101	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T18	18		T35	14		T98	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T105	1		T163	15		T46	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T46	6		T48	1		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T32	1		T163	4		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T21	1		T127	1		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T194	8		T294	2		T295	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T186	1		T108	1		T210	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T20	14		T164	1		T287	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T195	9		T208	6		T236	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T94	1		T211	13		T158	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T94	1		T157	11		T199	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T19	6		T21	6		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T138	13		T195	8		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T103	1		T158	6		T111	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T13	13		T17	10		T22	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T21	3		T100	14		T32	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T118	3		T277	11		T239	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T21	1		T117	12		T195	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T117	2		T101	2		T196	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T35	13		T98	3		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T105	4		T163	2		T46	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T46	2		T157	2		T298	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T163	10		T220	11		T211	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T21	2		T211	11		T197	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6