Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22505

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3322

1

T14

1

T18

18

T19

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20201

1

T5

1

T23

1

T24

1

auto[1]

5626

1

T13

15

T14

2

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	173	1			T101	1		T48	1		T195	12
values[0]	4	1			T14	1		T299	3		-	-
values[1]	684	1			T21	3		T138	14		T187	1
values[2]	778	1			T98	9		T117	3		T127	1
values[3]	825	1			T21	15		T35	27		T100	30
values[4]	2446	1			T13	15		T15	23		T16	24
values[5]	693	1			T18	18		T108	4		T50	3
values[6]	670	1			T19	19		T20	15		T127	1
values[7]	534	1			T14	1		T19	7		T117	13
values[8]	853	1			T21	2		T94	7		T140	9
values[9]	823	1			T14	1		T21	8		T105	5
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T21	3		T117	3		T138	14
values[1]	811	1			T98	9		T127	1		T140	2
values[2]	661	1			T21	15		T35	27		T100	30
values[3]	2496	1			T13	15		T15	23		T16	24
values[4]	728	1			T18	18		T107	1		T108	4
values[5]	549	1			T19	19		T20	15		T127	1
values[6]	778	1			T14	1		T19	7		T94	2
values[7]	653	1			T21	2		T94	5		T127	1
values[8]	815	1			T14	1		T21	8		T105	5
values[9]	62	1			T101	1		T258	1		T216	1
minimum	17551	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T102	1		T104	1		T242	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T21	3		T117	3		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T101	6		T189	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T98	5		T127	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T21	8		T107	1		T103	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T35	14		T100	15		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T13	15		T15	3		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T105	1		T186	2		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T107	1		T50	1		T208	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	1		T108	2		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	9		T245	4		T262	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T20	15		T127	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	1		T94	2		T117	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T19	4		T33	3		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T94	3		T118	2		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	2		T127	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	1		T105	5		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T21	5		T32	12		T163	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T258	1		T205	1		T124	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T101	1		T216	1		T271	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17240	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T14	1		T267	15		T300	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T102	5		T211	10		T157	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T188	2		T211	16		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T101	1		T189	7		T198	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T98	4		T186	4		T163	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T21	7		T103	4		T195	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	13		T100	15		T109	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T15	20		T16	21		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T230	5		T260	13		T261	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T50	2		T121	10		T275	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	17		T108	2		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	10		T245	3		T262	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T50	3		T181	10		T147	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T118	10		T263	12		T113	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T19	3		T33	2		T46	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T94	2		T118	2		T213	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T140	2		T102	13		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T186	1		T46	10		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T21	3		T32	9		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T205	10		T301	7		T204	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T267	6		T300	1		T250	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T48	1		T195	10		T119	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T101	1		T110	1		T199	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T14	1		T299	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T102	1		T104	1		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T21	3		T138	14		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T242	2		T189	1		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T98	5		T117	3		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T21	8		T107	1		T101	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T35	14		T100	15		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T13	15		T15	3		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T105	1		T186	2		T230	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	1		T110	1		T208	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T18	1		T108	2		T211	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	9		T107	1		T121	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T20	15		T127	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	1		T117	13		T105	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T19	4		T127	1		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T94	5		T32	1		T118	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T21	2		T140	7		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T14	1		T105	5		T186	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T21	5		T32	12		T163	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T195	2		T147	2		T240	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T199	7		T254	14		T302	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T299	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T102	5		T211	10		T202	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T191	6		T266	10		T267	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T189	7		T198	4		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T98	4		T163	3		T102	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T21	7		T101	1		T103	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T35	13		T100	15		T186	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T15	20		T16	21		T53	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T230	5		T227	4		T268	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	2		T275	9		T303	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T18	17		T108	2		T211	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	10		T121	10		T245	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	3		T181	10		T147	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T118	10		T263	12		T113	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T19	3		T33	2		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T94	2		T118	2		T213	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T140	2		T102	13		T109	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T186	1		T46	10		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	3		T32	9		T163	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T102	6		T104	1		T242	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T21	1		T117	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T101	5		T189	8		T198	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T98	6		T127	1		T140	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T21	9		T107	1		T103	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T35	14		T100	16		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T13	2		T15	23		T16	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T105	1		T186	1		T230	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T107	1		T50	3		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T18	18		T108	4		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T19	13		T245	6		T262	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T20	1		T127	1		T109	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	1		T94	2		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T19	7		T33	4		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T94	4		T118	3		T213	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T21	1		T127	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T14	1		T105	1		T186	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T21	5		T32	13		T163	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T258	1		T205	11		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T101	1		T216	1		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17413	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T14	1		T267	7		T300	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T211	11		T157	8		T147	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T21	2		T117	2		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T101	2		T199	14		T215	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T98	3		T186	1		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T21	6		T103	1		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T35	13		T100	14		T164	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	897	1			T13	13		T17	10		T22	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T186	1		T269	12		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T208	6		T121	9		T192	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T211	12		T217	11		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T19	6		T245	1		T262	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T20	14		T181	4		T147	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T117	12		T105	5		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T33	1		T46	2		T195	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T94	1		T118	1		T236	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T21	1		T140	2		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T105	4		T46	10		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T21	3		T32	8		T163	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T124	14		T270	1		T204	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T271	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T202	6		T268	11		T161	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T267	14		T300	3		T250	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T48	1		T195	3		T119	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T101	1		T110	1		T199	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T14	1		T299	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T102	6		T104	1		T211	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T21	1		T138	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T242	2		T189	8		T265	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T98	6		T117	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T21	9		T107	1		T101	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T35	14		T100	16		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T13	2		T15	23		T16	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T105	1		T186	1		T230	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T50	3		T110	1		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T18	18		T108	4		T211	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T19	13		T107	1		T121	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	1		T127	1		T109	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	1		T117	1		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T19	7		T127	1		T33	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T94	6		T32	1		T118	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T21	1		T140	7		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T14	1		T105	1		T186	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T21	5		T32	13		T163	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T195	9		T147	2		T272	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T199	7		T254	13		T271	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T211	11		T202	6		T157	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	2		T138	13		T108	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T199	14		T219	7		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T98	3		T117	2		T163	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T21	6		T101	2		T103	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	13		T100	14		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T13	13		T17	10		T22	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T186	1		T269	12		T268	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T208	6		T286	8		T192	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T211	12		T217	11		T216	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T19	6		T121	9		T245	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T20	14		T181	4		T147	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T117	12		T105	5		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T33	1		T46	2		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T94	1		T118	1		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T21	1		T140	2		T109	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T105	4		T46	10		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T21	3		T32	8		T163	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6