Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22217

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3610

1

T14

3

T19

26

T20

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20151

1

T5

1

T23

1

T24

1

auto[1]

5676

1

T13

15

T14

1

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T157	5		T115	1		T190	17
values[0]	19	1			T124	5		T185	14		-	-
values[1]	661	1			T21	15		T35	27		T98	9
values[2]	734	1			T14	1		T19	19		T32	1
values[3]	644	1			T14	1		T18	18		T21	2
values[4]	761	1			T94	5		T117	3		T127	1
values[5]	500	1			T14	1		T105	5		T32	21
values[6]	675	1			T127	1		T186	8		T187	1
values[7]	885	1			T19	7		T34	7		T127	1
values[8]	617	1			T117	13		T105	1		T100	30
values[9]	2769	1			T13	15		T15	23		T16	24
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	633	1			T14	1		T19	19		T21	15
values[1]	661	1			T14	1		T32	1		T186	2
values[2]	732	1			T18	18		T21	2		T94	10
values[3]	707	1			T117	3		T140	9		T33	5
values[4]	543	1			T14	1		T105	5		T127	1
values[5]	707	1			T186	2		T187	1		T101	1
values[6]	2624	1			T13	15		T15	23		T16	24
values[7]	795	1			T20	15		T117	13		T46	8
values[8]	757	1			T21	11		T105	6		T187	1
values[9]	108	1			T140	2		T52	1		T157	18
minimum	17560	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T98	5		T188	1		T158	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T19	9		T21	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T186	1		T141	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	1		T32	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	1		T94	7		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T21	2		T127	1		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T140	7		T107	1		T103	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T117	3		T33	3		T187	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T105	5		T186	2		T108	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T127	1		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T187	1		T101	1		T102	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T186	2		T109	8		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T13	15		T15	3		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T19	4		T34	4		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T46	3		T48	1		T164	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T20	15		T117	13		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T21	3		T105	6		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T21	5		T187	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T157	9		T190	17		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T140	2		T52	1		T205	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17257	1			T18	50		T19	131		T21	423
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T107	1		T195	9		T111	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T98	4		T188	2		T210	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T19	10		T21	7		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T186	1		T192	4		T251	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T147	13		T193	12		T194	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	17		T94	3		T46	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T195	9		T147	14		T170	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T140	2		T103	4		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T33	2		T102	13		T213	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T186	4		T108	2		T113	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T32	9		T102	15		T118	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T102	5		T118	10		T197	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T109	16		T198	4		T199	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T15	20		T16	21		T53	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	3		T34	3		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	5		T164	4		T211	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T108	2		T200	17		T199	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T189	7		T158	8		T201	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T21	3		T202	11		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T157	9		T203	3		T304	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T205	13		T194	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	1		T23	1		T24	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T195	8		T130	11		T305	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T115	1		T190	17		T306	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T157	3		T249	11		T307	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T124	5		T185	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T98	5		T101	6		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T21	8		T35	14		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T141	1		T110	1		T158	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	1		T19	9		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	1		T94	3		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T21	2		T108	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T94	4		T140	7		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T117	3		T127	1		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T105	5		T108	3		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	1		T32	12		T102	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T186	2		T187	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T127	1		T186	2		T109	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T127	1		T209	1		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T19	4		T34	4		T138	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T100	15		T163	11		T46	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T117	13		T105	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T13	15		T15	3		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T20	15		T21	5		T140	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T203	3		T291	10		T250	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T157	2		T249	10		T308	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T98	4		T101	1		T188	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T21	7		T35	13		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T212	2		T235	3		T192	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T19	10		T211	10		T147	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T18	17		T94	2		T186	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T195	9		T147	14		T191	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T94	1		T140	2		T103	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T33	2		T102	13		T213	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T108	2		T50	2		T113	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T32	9		T102	15		T109	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T186	4		T102	5		T118	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T109	6		T199	14		T214	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T50	3		T215	2		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T19	3		T34	3		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T100	15		T163	3		T46	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T147	2		T198	7		T200	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1092	1			T15	20		T16	21		T53	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T21	3		T108	2		T202	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T98	6		T188	3		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	1		T19	13		T21	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T186	2		T141	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	1		T32	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T18	18		T94	8		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T21	1		T127	1		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T140	7		T107	1		T103	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T117	1		T33	4		T187	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T105	1		T186	5		T108	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	1		T127	1		T32	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T187	1		T101	1		T102	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T186	1		T109	18		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T13	2		T15	23		T16	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T19	7		T34	7		T105	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T46	6		T48	1		T164	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T20	1		T117	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T21	1		T105	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T21	5		T187	1		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T157	10		T190	1		T203	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T140	2		T52	1		T205	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17389	1			T5	1		T23	1		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T107	1		T195	9		T111	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T98	3		T158	13		T221	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T19	6		T21	6		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T208	6		T217	11		T148	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T147	12		T193	12		T194	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T94	2		T46	10		T181	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T21	1		T108	1		T195	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T140	2		T103	1		T195	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T117	2		T33	1		T236	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T105	4		T186	1		T108	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T32	8		T118	1		T196	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T118	3		T197	10		T219	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T186	1		T109	6		T199	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T13	13		T17	10		T22	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	13		T163	2		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	2		T164	1		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	14		T117	12		T199	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T21	2		T105	5		T158	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T21	3		T202	6		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T157	8		T190	16		T304	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T194	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T101	2		T309	12		T310	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T195	8		T111	12		T130	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T115	1		T190	1		T306	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T157	3		T249	11		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T124	1		T185	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T98	6		T101	5		T188	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T21	9		T35	14		T107	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T141	1		T110	1		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T14	1		T19	13		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T18	18		T94	4		T186	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	1		T21	1		T108	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T94	4		T140	7		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T117	1		T127	1		T33	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T105	1		T108	4		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T32	13		T102	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T186	5		T187	1		T101	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T127	1		T186	1		T109	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T127	1		T209	1		T50	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T19	7		T34	7		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T100	16		T163	4		T46	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T117	1		T105	1		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T13	2		T15	23		T16	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T20	1		T21	5		T140	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T190	16		T222	9		T291	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T157	2		T249	10		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T124	4		T185	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T98	3		T101	2		T207	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T21	6		T35	13		T195	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T158	13		T221	4		T217	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	6		T211	11		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T94	1		T46	10		T208	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T21	1		T108	1		T195	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T94	1		T140	2		T103	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T117	2		T33	1		T236	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T105	4		T108	1		T111	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T32	8		T118	1		T196	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T186	1		T118	3		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T186	1		T109	6		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T215	2		T216	8		T218	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T138	13		T163	2		T211	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T100	14		T163	10		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T117	12		T147	2		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T13	13		T17	10		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	14		T21	3		T202	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6