Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25827

1

T5

1

T23

1

T24

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22567

1

T5

1

T23

1

T24

1

auto[ADC_CTRL_FILTER_COND_OUT]

3260

1

T14

3

T20

15

T21

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19999

1

T5

1

T23

1

T24

1

auto[1]

5828

1

T13

15

T14

3

T15

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21724

1

T13

15

T14

3

T15

3

auto[1]

4103

1

T5

1

T23

1

T24

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	473	1			T19	10		T21	21		T34	3
values[0]	36	1			T206	15		T126	1		T134	3
values[1]	486	1			T19	7		T21	18		T102	20
values[2]	2590	1			T13	15		T14	1		T15	23
values[3]	570	1			T94	3		T117	3		T138	14
values[4]	588	1			T14	2		T140	2		T163	17
values[5]	631	1			T21	8		T186	6		T107	2
values[6]	793	1			T20	15		T127	1		T186	2
values[7]	623	1			T105	6		T127	1		T140	9
values[8]	769	1			T21	2		T34	7		T94	7
values[9]	1375	1			T18	18		T100	30		T33	5
minimum	16893	1			T5	1		T23	1		T24	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T19	26		T21	18		T35	27
values[1]	2399	1			T13	15		T14	1		T15	23
values[2]	669	1			T14	1		T94	3		T138	14
values[3]	602	1			T14	1		T140	2		T186	6
values[4]	712	1			T21	8		T109	12		T108	5
values[5]	705	1			T20	15		T127	1		T186	4
values[6]	697	1			T117	13		T105	6		T127	1
values[7]	668	1			T21	2		T34	7		T94	7
values[8]	983	1			T100	30		T127	1		T33	5
values[9]	296	1			T18	18		T163	14		T196	33
minimum	17344	1			T5	1		T23	1		T24	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

3486

1

T13

13

T17

10

T19

6

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T19	13		T21	8		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T21	3		T35	14		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T13	15		T15	3		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	1		T117	3		T105	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T32	1		T101	6		T103	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	1		T94	2		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T140	2		T163	3		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	1		T186	2		T107	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T21	5		T195	9		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T109	2		T108	3		T164	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T127	1		T48	1		T242	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T20	15		T186	3		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T117	13		T105	5		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T105	1		T140	7		T32	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T94	5		T109	7		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T21	2		T34	4		T98	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T100	15		T107	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T127	1		T33	3		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T18	1		T163	11		T196	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T224	1		T258	1		T231	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17201	1			T18	50		T19	131		T21	423
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T19	13		T21	7		T102	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T35	13		T102	13		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T15	20		T16	21		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T108	2		T202	11		T311	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T101	1		T103	4		T189	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T94	1		T253	3		T277	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T163	14		T199	14		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T186	4		T46	5		T147	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T21	3		T195	9		T50	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T109	10		T108	2		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T263	12		T200	17		T193	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T186	1		T197	14		T130	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T118	10		T157	12		T246	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T140	2		T32	9		T102	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T94	2		T109	6		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T34	3		T98	4		T211	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T100	15		T195	8		T118	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T33	2		T199	7		T212	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T18	17		T163	3		T196	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T231	10		T131	12		T312	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	461	1			T19	10		T21	21		T34	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T313	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T134	3		T314	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T206	9		T126	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T19	4		T21	8		T102	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T21	3		T102	1		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T13	15		T15	3		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T35	14		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T101	6		T189	1		T217	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T94	2		T117	3		T138	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	2		T163	3		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	2		T46	3		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T21	5		T195	9		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T186	2		T107	2		T109	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T127	1		T48	1		T242	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T20	15		T186	2		T197	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T105	5		T127	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T105	1		T140	7		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T94	5		T117	13		T109	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T21	2		T34	4		T98	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T18	1		T100	15		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T33	3		T187	2		T211	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16750	1			T18	50		T19	121		T21	402
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T118	2		T210	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T313	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T314	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T206	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T19	3		T21	7		T102	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T102	13		T46	10		T118	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T15	20		T16	21		T19	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	13		T108	2		T202	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T101	1		T189	7		T180	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T94	1		T253	3		T122	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T163	14		T199	14		T216	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T46	5		T147	13		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T21	3		T195	9		T50	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T186	4		T109	10		T108	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T263	12		T236	13		T200	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T197	14		T130	12		T198	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T157	12		T131	10		T275	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	2		T186	1		T102	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T94	2		T109	6		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T34	3		T98	4		T32	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T18	17		T100	15		T163	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T33	2		T211	11		T231	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	1		T23	1		T24	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T19	20		T21	9		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T21	1		T35	14		T102	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T13	2		T15	23		T16	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	1		T117	1		T105	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	1		T101	5		T103	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T94	2		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	2		T163	15		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T186	5		T107	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T21	5		T195	10		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T109	12		T108	4		T164	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T127	1		T48	1		T242	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T20	1		T186	3		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T117	1		T105	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T105	1		T140	7		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T94	6		T109	7		T50	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T21	1		T34	7		T98	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T100	16		T107	1		T48	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T127	1		T33	4		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T18	18		T163	4		T196	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T224	1		T258	1		T231	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17344	1			T5	1		T23	1		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T19	6		T21	6		T157	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T21	2		T35	13		T46	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T13	13		T17	10		T22	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T117	2		T105	5		T202	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T101	2		T103	1		T208	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T94	1		T138	13		T111	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T163	2		T199	5		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T186	1		T46	2		T147	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T21	3		T195	8		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T108	1		T164	1		T211	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	8		T286	17		T190	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	14		T186	1		T197	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T117	12		T105	4		T118	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T140	2		T32	8		T108	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T94	1		T109	6		T248	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T21	1		T98	3		T211	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T100	14		T195	8		T220	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	1		T217	11		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T163	10		T196	16		T287	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T231	9		T312	12		T313	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	461	1			T19	10		T21	21		T34	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T313	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T134	1		T314	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T206	8		T126	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T19	7		T21	9		T102	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T21	1		T102	14		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T13	2		T15	23		T16	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T35	14		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T101	5		T189	8		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T94	2		T117	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T140	2		T163	15		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	2		T46	6		T147	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T21	5		T195	10		T50	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T186	5		T107	2		T109	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T127	1		T48	1		T242	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	1		T186	1		T197	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T105	1		T127	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T105	1		T140	7		T186	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T94	6		T117	1		T109	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T21	1		T34	7		T98	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T18	18		T100	16		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T33	4		T187	2		T211	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16893	1			T5	1		T23	1		T24	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T118	1		T210	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T313	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T134	2		T314	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T206	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T21	6		T221	1		T245	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T21	2		T46	10		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T13	13		T17	10		T19	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T35	13		T105	5		T202	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T101	2		T217	3		T191	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T94	1		T117	2		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T163	2		T208	6		T199	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T46	2		T147	12		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T21	3		T195	8		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T186	1		T108	1		T164	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T236	14		T152	8		T190	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	14		T186	1		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T105	4		T157	11		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T140	2		T108	1		T286	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T94	1		T117	12		T109	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T21	1		T98	3		T32	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T100	14		T163	10		T195	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T33	1		T211	12		T221	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T5

1

T23

1

T24

1

auto[1]

auto[0]

3486

1

T13

13

T17

10

T19

6