Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 98.98 95.70 100.00 100.00 98.18 98.64 90.72


Total test records in report: 916
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T779 /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1395215860 Dec 27 12:38:46 PM PST 23 Dec 27 12:40:28 PM PST 23 162804336462 ps
T329 /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3402049201 Dec 27 12:39:20 PM PST 23 Dec 27 12:59:31 PM PST 23 496931414186 ps
T780 /workspace/coverage/default/47.adc_ctrl_poweron_counter.638003284 Dec 27 12:38:55 PM PST 23 Dec 27 12:39:14 PM PST 23 4548374212 ps
T781 /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.790924295 Dec 27 12:37:34 PM PST 23 Dec 27 12:38:33 PM PST 23 186937184110 ps
T339 /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2780713407 Dec 27 12:37:29 PM PST 23 Dec 27 12:39:17 PM PST 23 163368225817 ps
T782 /workspace/coverage/default/38.adc_ctrl_alert_test.1337132518 Dec 27 12:38:48 PM PST 23 Dec 27 12:38:58 PM PST 23 287069525 ps
T783 /workspace/coverage/default/19.adc_ctrl_filters_both.252817522 Dec 27 12:38:05 PM PST 23 Dec 27 12:44:41 PM PST 23 167565595199 ps
T784 /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4078590726 Dec 27 12:37:35 PM PST 23 Dec 27 12:56:35 PM PST 23 492214989438 ps
T785 /workspace/coverage/default/28.adc_ctrl_poweron_counter.1783048986 Dec 27 12:38:15 PM PST 23 Dec 27 12:38:33 PM PST 23 4128439511 ps
T786 /workspace/coverage/default/13.adc_ctrl_alert_test.3058867016 Dec 27 12:37:56 PM PST 23 Dec 27 12:38:06 PM PST 23 436914223 ps
T787 /workspace/coverage/default/36.adc_ctrl_clock_gating.1527893144 Dec 27 12:38:52 PM PST 23 Dec 27 12:41:12 PM PST 23 484201663635 ps
T788 /workspace/coverage/default/10.adc_ctrl_filters_polled.357559998 Dec 27 12:37:46 PM PST 23 Dec 27 12:50:04 PM PST 23 325428991013 ps
T789 /workspace/coverage/default/15.adc_ctrl_clock_gating.3772992432 Dec 27 12:37:45 PM PST 23 Dec 27 12:57:09 PM PST 23 496970677772 ps
T790 /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1977000726 Dec 27 12:38:37 PM PST 23 Dec 27 12:52:30 PM PST 23 334442401132 ps
T791 /workspace/coverage/default/28.adc_ctrl_alert_test.42041532 Dec 27 12:38:47 PM PST 23 Dec 27 12:38:57 PM PST 23 364934740 ps
T305 /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1672518383 Dec 27 12:38:09 PM PST 23 Dec 27 12:39:58 PM PST 23 158984457655 ps
T792 /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3856039867 Dec 27 12:39:04 PM PST 23 Dec 27 12:44:05 PM PST 23 239795861925 ps
T793 /workspace/coverage/default/20.adc_ctrl_stress_all.934042807 Dec 27 12:37:53 PM PST 23 Dec 27 12:39:13 PM PST 23 173893705185 ps
T794 /workspace/coverage/default/20.adc_ctrl_filters_polled.3264810711 Dec 27 12:37:53 PM PST 23 Dec 27 12:44:13 PM PST 23 155947028964 ps
T146 /workspace/coverage/default/49.adc_ctrl_clock_gating.3005665317 Dec 27 12:38:47 PM PST 23 Dec 27 12:43:05 PM PST 23 491262142300 ps
T795 /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4080253073 Dec 27 12:38:52 PM PST 23 Dec 27 12:39:30 PM PST 23 39826802041 ps
T324 /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2101200054 Dec 27 12:37:57 PM PST 23 Dec 27 12:51:24 PM PST 23 329405643109 ps
T796 /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1106406825 Dec 27 12:40:56 PM PST 23 Dec 27 12:43:08 PM PST 23 167029260812 ps
T44 /workspace/coverage/default/2.adc_ctrl_sec_cm.283707990 Dec 27 12:37:05 PM PST 23 Dec 27 12:37:38 PM PST 23 4026575337 ps
T797 /workspace/coverage/default/39.adc_ctrl_filters_polled.4112811361 Dec 27 12:38:54 PM PST 23 Dec 27 12:44:57 PM PST 23 162404647507 ps
T798 /workspace/coverage/default/23.adc_ctrl_clock_gating.3974187905 Dec 27 12:38:14 PM PST 23 Dec 27 12:39:57 PM PST 23 164846783653 ps
T799 /workspace/coverage/default/15.adc_ctrl_fsm_reset.2221168957 Dec 27 12:37:42 PM PST 23 Dec 27 12:50:13 PM PST 23 137849340442 ps
T800 /workspace/coverage/default/25.adc_ctrl_fsm_reset.4175817014 Dec 27 12:38:22 PM PST 23 Dec 27 12:48:22 PM PST 23 106658294290 ps
T801 /workspace/coverage/default/21.adc_ctrl_poweron_counter.3774113602 Dec 27 12:38:07 PM PST 23 Dec 27 12:38:19 PM PST 23 4110363268 ps
T802 /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2285147862 Dec 27 12:37:25 PM PST 23 Dec 27 12:43:46 PM PST 23 160375770958 ps
T803 /workspace/coverage/default/14.adc_ctrl_clock_gating.3915992303 Dec 27 12:37:31 PM PST 23 Dec 27 12:43:48 PM PST 23 163439092017 ps
T804 /workspace/coverage/default/48.adc_ctrl_fsm_reset.1776933499 Dec 27 12:38:59 PM PST 23 Dec 27 12:47:00 PM PST 23 111551153651 ps
T805 /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.653929693 Dec 27 12:38:29 PM PST 23 Dec 27 12:40:19 PM PST 23 160968666706 ps
T806 /workspace/coverage/default/31.adc_ctrl_alert_test.3921942408 Dec 27 12:38:08 PM PST 23 Dec 27 12:38:21 PM PST 23 412637175 ps
T257 /workspace/coverage/default/21.adc_ctrl_filters_interrupt.540234878 Dec 27 12:38:04 PM PST 23 Dec 27 12:54:29 PM PST 23 485885870594 ps
T807 /workspace/coverage/default/47.adc_ctrl_alert_test.819796659 Dec 27 12:38:54 PM PST 23 Dec 27 12:39:10 PM PST 23 492425892 ps
T808 /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.745988319 Dec 27 12:38:39 PM PST 23 Dec 27 12:39:29 PM PST 23 118079570424 ps
T809 /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3576071028 Dec 27 12:38:44 PM PST 23 Dec 27 12:44:07 PM PST 23 483602926896 ps
T155 /workspace/coverage/default/44.adc_ctrl_filters_polled.1726033267 Dec 27 12:38:39 PM PST 23 Dec 27 12:41:16 PM PST 23 335736536811 ps
T810 /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1426885672 Dec 27 12:38:15 PM PST 23 Dec 27 12:57:21 PM PST 23 492008386580 ps
T811 /workspace/coverage/default/9.adc_ctrl_clock_gating.1727549838 Dec 27 12:37:20 PM PST 23 Dec 27 12:41:49 PM PST 23 490136474010 ps
T340 /workspace/coverage/default/23.adc_ctrl_filters_wakeup.400148879 Dec 27 12:38:33 PM PST 23 Dec 27 12:40:06 PM PST 23 514196150918 ps
T812 /workspace/coverage/default/2.adc_ctrl_stress_all.2794204326 Dec 27 12:37:42 PM PST 23 Dec 27 12:47:11 PM PST 23 145193814140 ps
T813 /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1128565555 Dec 27 12:38:35 PM PST 23 Dec 27 12:41:53 PM PST 23 164264260230 ps
T814 /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2527733283 Dec 27 12:38:00 PM PST 23 Dec 27 12:57:08 PM PST 23 490174816942 ps
T815 /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1595353441 Dec 27 12:38:50 PM PST 23 Dec 27 12:50:24 PM PST 23 321912357427 ps
T816 /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2141228705 Dec 27 12:38:05 PM PST 23 Dec 27 12:38:27 PM PST 23 27984158186 ps
T817 /workspace/coverage/default/6.adc_ctrl_smoke.3014317283 Dec 27 12:38:07 PM PST 23 Dec 27 12:38:17 PM PST 23 5540545576 ps
T818 /workspace/coverage/default/38.adc_ctrl_filters_polled.2665345132 Dec 27 12:38:38 PM PST 23 Dec 27 12:47:15 PM PST 23 501835242810 ps
T819 /workspace/coverage/default/18.adc_ctrl_poweron_counter.882101951 Dec 27 12:38:58 PM PST 23 Dec 27 12:39:16 PM PST 23 4074491745 ps
T204 /workspace/coverage/default/45.adc_ctrl_stress_all.297933192 Dec 27 12:38:49 PM PST 23 Dec 27 12:51:00 PM PST 23 332091809632 ps
T820 /workspace/coverage/default/11.adc_ctrl_smoke.2862002083 Dec 27 12:37:26 PM PST 23 Dec 27 12:38:00 PM PST 23 5980361439 ps
T821 /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2745701762 Dec 27 12:39:19 PM PST 23 Dec 27 12:52:01 PM PST 23 330964696917 ps
T822 /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3815644019 Dec 27 12:37:37 PM PST 23 Dec 27 12:50:04 PM PST 23 320481359195 ps
T823 /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.4240985601 Dec 27 12:37:06 PM PST 23 Dec 27 12:40:25 PM PST 23 167455652556 ps
T824 /workspace/coverage/default/3.adc_ctrl_clock_gating.3987581406 Dec 27 12:37:05 PM PST 23 Dec 27 12:47:22 PM PST 23 483069306601 ps
T825 /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.112588581 Dec 27 12:38:02 PM PST 23 Dec 27 12:42:26 PM PST 23 239739489204 ps
T280 /workspace/coverage/default/41.adc_ctrl_filters_both.1355707956 Dec 27 12:38:17 PM PST 23 Dec 27 12:39:46 PM PST 23 166473778407 ps
T826 /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3828532078 Dec 27 12:38:45 PM PST 23 Dec 27 12:45:11 PM PST 23 332439908404 ps
T827 /workspace/coverage/default/4.adc_ctrl_clock_gating.319332556 Dec 27 12:37:09 PM PST 23 Dec 27 12:39:15 PM PST 23 169207819835 ps
T283 /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3963543225 Dec 27 12:37:13 PM PST 23 Dec 27 12:49:37 PM PST 23 316115840559 ps
T828 /workspace/coverage/default/44.adc_ctrl_poweron_counter.1959631517 Dec 27 12:38:34 PM PST 23 Dec 27 12:38:43 PM PST 23 5479393070 ps
T232 /workspace/coverage/default/36.adc_ctrl_stress_all.919631453 Dec 27 12:38:33 PM PST 23 Dec 27 12:53:04 PM PST 23 289837329662 ps
T829 /workspace/coverage/default/22.adc_ctrl_poweron_counter.639055071 Dec 27 12:38:15 PM PST 23 Dec 27 12:38:28 PM PST 23 4626109373 ps
T233 /workspace/coverage/default/39.adc_ctrl_stress_all.457170409 Dec 27 12:38:20 PM PST 23 Dec 27 12:54:45 PM PST 23 533189548745 ps
T830 /workspace/coverage/default/22.adc_ctrl_alert_test.3908974638 Dec 27 12:37:41 PM PST 23 Dec 27 12:37:51 PM PST 23 462254415 ps
T831 /workspace/coverage/default/38.adc_ctrl_filters_both.3029764294 Dec 27 12:38:17 PM PST 23 Dec 27 12:44:52 PM PST 23 327636274186 ps
T304 /workspace/coverage/default/17.adc_ctrl_stress_all.2531157207 Dec 27 12:37:56 PM PST 23 Dec 27 12:40:18 PM PST 23 505783944298 ps
T832 /workspace/coverage/default/22.adc_ctrl_clock_gating.971262881 Dec 27 12:38:20 PM PST 23 Dec 27 12:39:43 PM PST 23 159665071438 ps
T833 /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3811822693 Dec 27 12:38:26 PM PST 23 Dec 27 12:40:26 PM PST 23 92975845947 ps
T834 /workspace/coverage/default/44.adc_ctrl_smoke.102078882 Dec 27 12:38:49 PM PST 23 Dec 27 12:39:05 PM PST 23 5856227126 ps
T835 /workspace/coverage/default/10.adc_ctrl_fsm_reset.22574600 Dec 27 12:37:16 PM PST 23 Dec 27 12:49:01 PM PST 23 115888444596 ps
T836 /workspace/coverage/default/3.adc_ctrl_filters_both.1610291436 Dec 27 12:37:04 PM PST 23 Dec 27 12:38:11 PM PST 23 171854336400 ps
T837 /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3444335062 Dec 27 12:37:49 PM PST 23 Dec 27 12:38:53 PM PST 23 319594497823 ps
T838 /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3255514368 Dec 27 12:38:26 PM PST 23 Dec 27 12:43:10 PM PST 23 489888441692 ps
T839 /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2693285491 Dec 27 12:37:20 PM PST 23 Dec 27 12:40:22 PM PST 23 325084261651 ps
T264 /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1635936588 Dec 27 12:37:58 PM PST 23 Dec 27 12:47:22 PM PST 23 491909817231 ps
T840 /workspace/coverage/default/33.adc_ctrl_fsm_reset.3335209428 Dec 27 12:38:58 PM PST 23 Dec 27 12:45:30 PM PST 23 90915604806 ps
T841 /workspace/coverage/default/29.adc_ctrl_fsm_reset.2763863215 Dec 27 12:38:04 PM PST 23 Dec 27 12:42:33 PM PST 23 82508075176 ps
T322 /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2647552264 Dec 27 12:37:56 PM PST 23 Dec 27 12:54:32 PM PST 23 496311532109 ps
T842 /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2765419217 Dec 27 12:38:26 PM PST 23 Dec 27 12:50:17 PM PST 23 334079587363 ps
T843 /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3232178629 Dec 27 12:38:27 PM PST 23 Dec 27 12:39:13 PM PST 23 34154780508 ps
T844 /workspace/coverage/default/0.adc_ctrl_filters_both.2250343256 Dec 27 12:36:33 PM PST 23 Dec 27 12:42:01 PM PST 23 494350242238 ps
T845 /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3724012549 Dec 27 12:38:32 PM PST 23 Dec 27 12:45:35 PM PST 23 325635254431 ps
T846 /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2340435919 Dec 27 12:38:02 PM PST 23 Dec 27 12:40:36 PM PST 23 328819177685 ps
T847 /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4269385437 Dec 27 12:38:15 PM PST 23 Dec 27 12:41:24 PM PST 23 323787541422 ps
T848 /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1938920866 Dec 27 12:38:51 PM PST 23 Dec 27 12:41:51 PM PST 23 320609283086 ps
T849 /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1521715919 Dec 27 12:38:18 PM PST 23 Dec 27 12:42:58 PM PST 23 158348587131 ps
T850 /workspace/coverage/default/24.adc_ctrl_stress_all.1164113752 Dec 27 12:38:13 PM PST 23 Dec 27 12:40:21 PM PST 23 55391734744 ps
T334 /workspace/coverage/default/35.adc_ctrl_clock_gating.2725474032 Dec 27 12:38:30 PM PST 23 Dec 27 12:41:53 PM PST 23 332348396190 ps
T851 /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1227566706 Dec 27 12:37:09 PM PST 23 Dec 27 12:39:35 PM PST 23 326106307667 ps
T852 /workspace/coverage/default/46.adc_ctrl_smoke.4030012418 Dec 27 12:38:45 PM PST 23 Dec 27 12:38:57 PM PST 23 5849855727 ps
T853 /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.437374629 Dec 27 12:38:57 PM PST 23 Dec 27 12:41:42 PM PST 23 66855330066 ps
T854 /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1690000778 Dec 27 12:38:20 PM PST 23 Dec 27 12:56:32 PM PST 23 496459683491 ps
T855 /workspace/coverage/default/37.adc_ctrl_fsm_reset.3785185570 Dec 27 12:38:51 PM PST 23 Dec 27 12:46:10 PM PST 23 112205960660 ps
T856 /workspace/coverage/default/33.adc_ctrl_clock_gating.2773403328 Dec 27 12:38:32 PM PST 23 Dec 27 12:41:43 PM PST 23 332995942559 ps
T857 /workspace/coverage/default/2.adc_ctrl_lowpower_counter.924096920 Dec 27 12:37:28 PM PST 23 Dec 27 12:38:03 PM PST 23 33143168647 ps
T858 /workspace/coverage/default/33.adc_ctrl_filters_polled.2966825845 Dec 27 12:38:33 PM PST 23 Dec 27 12:41:15 PM PST 23 317619170874 ps
T185 /workspace/coverage/default/16.adc_ctrl_clock_gating.299927476 Dec 27 12:37:53 PM PST 23 Dec 27 12:50:19 PM PST 23 331538818216 ps
T859 /workspace/coverage/default/31.adc_ctrl_fsm_reset.3725659584 Dec 27 12:37:55 PM PST 23 Dec 27 12:45:05 PM PST 23 132012217480 ps
T860 /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3251533271 Dec 27 12:38:26 PM PST 23 Dec 27 12:42:42 PM PST 23 487133582964 ps
T861 /workspace/coverage/default/13.adc_ctrl_filters_polled.3957002823 Dec 27 12:37:26 PM PST 23 Dec 27 12:43:36 PM PST 23 325758874573 ps
T862 /workspace/coverage/default/34.adc_ctrl_filters_both.4114752285 Dec 27 12:38:44 PM PST 23 Dec 27 12:42:24 PM PST 23 331847861013 ps
T863 /workspace/coverage/default/33.adc_ctrl_poweron_counter.340558708 Dec 27 12:38:33 PM PST 23 Dec 27 12:38:45 PM PST 23 4641251508 ps
T864 /workspace/coverage/default/11.adc_ctrl_alert_test.3530883873 Dec 27 12:39:20 PM PST 23 Dec 27 12:39:48 PM PST 23 570642218 ps
T259 /workspace/coverage/default/24.adc_ctrl_filters_both.3128336888 Dec 27 12:38:05 PM PST 23 Dec 27 12:44:55 PM PST 23 166259157302 ps
T865 /workspace/coverage/default/36.adc_ctrl_poweron_counter.342354530 Dec 27 12:38:25 PM PST 23 Dec 27 12:38:41 PM PST 23 3514438163 ps
T866 /workspace/coverage/default/45.adc_ctrl_fsm_reset.2171920751 Dec 27 12:38:30 PM PST 23 Dec 27 12:44:38 PM PST 23 107566223990 ps
T315 /workspace/coverage/default/47.adc_ctrl_clock_gating.1483202760 Dec 27 12:38:51 PM PST 23 Dec 27 12:42:08 PM PST 23 480412128555 ps
T867 /workspace/coverage/default/0.adc_ctrl_fsm_reset.2972770702 Dec 27 12:39:12 PM PST 23 Dec 27 12:46:09 PM PST 23 99457368082 ps
T868 /workspace/coverage/default/34.adc_ctrl_alert_test.1305687046 Dec 27 12:38:04 PM PST 23 Dec 27 12:38:12 PM PST 23 340200787 ps
T336 /workspace/coverage/default/0.adc_ctrl_clock_gating.2217532902 Dec 27 12:38:06 PM PST 23 Dec 27 12:38:34 PM PST 23 163670571075 ps
T345 /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1521366839 Dec 27 12:38:26 PM PST 23 Dec 27 12:56:42 PM PST 23 498942683295 ps
T869 /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1285614879 Dec 27 12:40:20 PM PST 23 Dec 27 12:42:56 PM PST 23 168794635001 ps
T341 /workspace/coverage/default/49.adc_ctrl_filters_interrupt.186500842 Dec 27 12:39:07 PM PST 23 Dec 27 12:41:06 PM PST 23 168514987413 ps
T870 /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.531045439 Dec 27 12:38:36 PM PST 23 Dec 27 12:52:14 PM PST 23 327249274717 ps
T333 /workspace/coverage/default/14.adc_ctrl_filters_polled.2594810932 Dec 27 12:38:10 PM PST 23 Dec 27 12:56:09 PM PST 23 513097553907 ps
T871 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.533766045 Dec 27 12:40:30 PM PST 23 Dec 27 12:41:28 PM PST 23 536442506 ps
T872 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2834485047 Dec 27 12:40:40 PM PST 23 Dec 27 12:41:44 PM PST 23 1005240234 ps
T873 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4242457649 Dec 27 12:40:40 PM PST 23 Dec 27 12:41:42 PM PST 23 449260975 ps
T91 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.576308538 Dec 27 12:40:45 PM PST 23 Dec 27 12:41:47 PM PST 23 346387571 ps
T874 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1280302413 Dec 27 12:40:42 PM PST 23 Dec 27 12:41:44 PM PST 23 435590670 ps
T875 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.271342477 Dec 27 12:41:09 PM PST 23 Dec 27 12:42:14 PM PST 23 322987688 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3156220086 Dec 27 12:40:34 PM PST 23 Dec 27 12:42:29 PM PST 23 26957380726 ps
T877 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1888168717 Dec 27 12:40:50 PM PST 23 Dec 27 12:41:55 PM PST 23 398485219 ps
T878 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1776349516 Dec 27 12:40:58 PM PST 23 Dec 27 12:42:17 PM PST 23 4482380883 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1812199501 Dec 27 12:40:32 PM PST 23 Dec 27 12:41:39 PM PST 23 491216144 ps
T880 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.562879187 Dec 27 12:40:34 PM PST 23 Dec 27 12:41:39 PM PST 23 4273784017 ps
T881 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1496826865 Dec 27 12:40:46 PM PST 23 Dec 27 12:41:58 PM PST 23 4246465649 ps
T882 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2583695788 Dec 27 12:40:51 PM PST 23 Dec 27 12:41:56 PM PST 23 524602463 ps
T883 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3765046065 Dec 27 12:40:36 PM PST 23 Dec 27 12:41:37 PM PST 23 454093742 ps
T884 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.420514066 Dec 27 12:40:44 PM PST 23 Dec 27 12:41:55 PM PST 23 4547351173 ps
T885 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.125040112 Dec 27 12:40:59 PM PST 23 Dec 27 12:42:04 PM PST 23 429689280 ps
T886 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.52678532 Dec 27 12:40:49 PM PST 23 Dec 27 12:41:53 PM PST 23 426849465 ps
T92 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3951677898 Dec 27 12:40:46 PM PST 23 Dec 27 12:41:48 PM PST 23 499209989 ps
T887 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4067413280 Dec 27 12:40:59 PM PST 23 Dec 27 12:42:04 PM PST 23 699193361 ps
T888 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3553510826 Dec 27 12:40:53 PM PST 23 Dec 27 12:41:58 PM PST 23 499418882 ps
T889 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2441699443 Dec 27 12:40:53 PM PST 23 Dec 27 12:41:59 PM PST 23 405549172 ps
T890 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.31726377 Dec 27 12:41:04 PM PST 23 Dec 27 12:42:14 PM PST 23 336271984 ps
T93 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2632042029 Dec 27 12:40:38 PM PST 23 Dec 27 12:41:39 PM PST 23 449794427 ps
T891 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.880274809 Dec 27 12:40:37 PM PST 23 Dec 27 12:41:37 PM PST 23 475318734 ps
T892 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3485863228 Dec 27 12:40:37 PM PST 23 Dec 27 12:41:38 PM PST 23 351216724 ps
T893 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3913043869 Dec 27 12:40:56 PM PST 23 Dec 27 12:42:01 PM PST 23 359639037 ps
T894 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.14476622 Dec 27 12:41:00 PM PST 23 Dec 27 12:42:06 PM PST 23 515405087 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3367897532 Dec 27 12:41:07 PM PST 23 Dec 27 12:42:17 PM PST 23 2499648124 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2634884256 Dec 27 12:40:39 PM PST 23 Dec 27 12:41:41 PM PST 23 517939386 ps
T897 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2377031359 Dec 27 12:40:51 PM PST 23 Dec 27 12:41:57 PM PST 23 441785444 ps
T898 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.597327771 Dec 27 12:40:57 PM PST 23 Dec 27 12:42:02 PM PST 23 555183816 ps
T899 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3680911362 Dec 27 12:40:33 PM PST 23 Dec 27 12:41:32 PM PST 23 484561706 ps
T900 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2061366115 Dec 27 12:40:43 PM PST 23 Dec 27 12:41:44 PM PST 23 663335203 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.939669597 Dec 27 12:40:28 PM PST 23 Dec 27 12:41:26 PM PST 23 394780325 ps
T902 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.29303190 Dec 27 12:40:34 PM PST 23 Dec 27 12:41:40 PM PST 23 8326532064 ps
T903 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2566564933 Dec 27 12:40:33 PM PST 23 Dec 27 12:41:33 PM PST 23 397760550 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2722914068 Dec 27 12:40:35 PM PST 23 Dec 27 12:41:37 PM PST 23 474668950 ps
T905 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1805177313 Dec 27 12:40:46 PM PST 23 Dec 27 12:41:50 PM PST 23 1525131639 ps
T906 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4050227101 Dec 27 12:40:35 PM PST 23 Dec 27 12:41:37 PM PST 23 681192131 ps
T907 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2478807794 Dec 27 12:40:39 PM PST 23 Dec 27 12:41:41 PM PST 23 668630334 ps
T908 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3140066643 Dec 27 12:40:35 PM PST 23 Dec 27 12:41:37 PM PST 23 362328025 ps
T909 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3103429792 Dec 27 12:41:05 PM PST 23 Dec 27 12:42:11 PM PST 23 660392330 ps
T910 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.406731972 Dec 27 12:41:15 PM PST 23 Dec 27 12:42:20 PM PST 23 312575673 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4007237056 Dec 27 12:40:40 PM PST 23 Dec 27 12:41:42 PM PST 23 475083725 ps
T912 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1911926148 Dec 27 12:41:05 PM PST 23 Dec 27 12:42:10 PM PST 23 530536194 ps
T913 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1714498244 Dec 27 12:40:47 PM PST 23 Dec 27 12:41:57 PM PST 23 7938222816 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.483824243 Dec 27 12:40:37 PM PST 23 Dec 27 12:41:41 PM PST 23 2237036204 ps
T915 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4210223923 Dec 27 12:41:11 PM PST 23 Dec 27 12:42:16 PM PST 23 363076277 ps
T916 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2372640467 Dec 27 12:40:49 PM PST 23 Dec 27 12:41:53 PM PST 23 434973113 ps

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2432594706
Short name T4
Test name
Test status
Simulation time 427277744 ps
CPU time 1.69 seconds
Started Dec 27 12:40:44 PM PST 23
Finished Dec 27 12:41:47 PM PST 23
Peak memory 200616 kb
Host smart-35a27e9d-40a6-4f4a-b7e5-0a9938676395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432594706 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2432594706
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3217563875
Short name T21
Test name
Test status
Simulation time 665073874081 ps
CPU time 783.16 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:51:20 PM PST 23
Peak memory 209396 kb
Host smart-67de88bf-e84b-4319-afdb-2439eeb4bd1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217563875 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3217563875
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.372780277
Short name T9
Test name
Test status
Simulation time 4482842440 ps
CPU time 5.09 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 12:41:54 PM PST 23
Peak memory 200748 kb
Host smart-f7dbeb00-972c-4777-ab61-b8211756ce0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372780277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.372780277
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3786802209
Short name T118
Test name
Test status
Simulation time 520799576578 ps
CPU time 317.2 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:43:28 PM PST 23
Peak memory 200824 kb
Host smart-2c372c34-c144-4063-9396-3d546e47f540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786802209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3786802209
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3517289388
Short name T23
Test name
Test status
Simulation time 326649800 ps
CPU time 0.8 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200244 kb
Host smart-24e9fcec-ddb0-4544-aeb0-0e729efd3e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517289388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3517289388
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1341233397
Short name T147
Test name
Test status
Simulation time 498670082925 ps
CPU time 229.44 seconds
Started Dec 27 12:37:39 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200788 kb
Host smart-6b44af45-e963-419e-88ef-01df26a91fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341233397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1341233397
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3583339147
Short name T56
Test name
Test status
Simulation time 656665944 ps
CPU time 3.47 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 200764 kb
Host smart-383670f0-3009-4602-ac21-98cda693802c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583339147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3583339147
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2455345042
Short name T14
Test name
Test status
Simulation time 491257955984 ps
CPU time 185.93 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:40:47 PM PST 23
Peak memory 200812 kb
Host smart-79d9bff6-3af0-4296-8669-81143e477d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455345042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2455345042
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4272479686
Short name T157
Test name
Test status
Simulation time 531072809912 ps
CPU time 236.53 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:42:42 PM PST 23
Peak memory 200796 kb
Host smart-73a32c9d-5507-4e4f-99a1-9ea1b4843433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272479686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4272479686
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1456854240
Short name T199
Test name
Test status
Simulation time 498904996405 ps
CPU time 71.19 seconds
Started Dec 27 12:37:43 PM PST 23
Finished Dec 27 12:39:02 PM PST 23
Peak memory 200892 kb
Host smart-3cb0e01f-17cd-42e3-9ef8-ce4b128683a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456854240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1456854240
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3633041864
Short name T186
Test name
Test status
Simulation time 489677606570 ps
CPU time 163.59 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:41:31 PM PST 23
Peak memory 200792 kb
Host smart-292a2695-29f7-4532-8d5e-267cba4bbf3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633041864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3633041864
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3612374457
Short name T211
Test name
Test status
Simulation time 488465592084 ps
CPU time 1040.45 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:56:29 PM PST 23
Peak memory 200568 kb
Host smart-bacd76da-3c9c-4695-bdf5-2a927e2432fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612374457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3612374457
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2180967989
Short name T94
Test name
Test status
Simulation time 75957689985 ps
CPU time 172.36 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 209044 kb
Host smart-6da271d0-60a5-4c43-a6ee-bdaba98e7b97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180967989 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2180967989
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4021688559
Short name T19
Test name
Test status
Simulation time 437771207467 ps
CPU time 462.54 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:45:52 PM PST 23
Peak memory 209380 kb
Host smart-2d2663a3-4523-490d-8d3b-91e1685ed538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021688559 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4021688559
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1413717629
Short name T216
Test name
Test status
Simulation time 494991071798 ps
CPU time 717.89 seconds
Started Dec 27 12:38:03 PM PST 23
Finished Dec 27 12:50:09 PM PST 23
Peak memory 200804 kb
Host smart-adcc201e-d620-4e97-a4e2-9687485db2ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413717629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1413717629
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.950121129
Short name T195
Test name
Test status
Simulation time 488541223910 ps
CPU time 1185.33 seconds
Started Dec 27 12:38:08 PM PST 23
Finished Dec 27 12:58:00 PM PST 23
Peak memory 200888 kb
Host smart-32967c69-e6d8-4ede-9f9e-79fc11f5656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950121129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.950121129
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3245815049
Short name T16
Test name
Test status
Simulation time 488906791812 ps
CPU time 226.75 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:41:22 PM PST 23
Peak memory 200832 kb
Host smart-27a8bc85-29bb-43b5-b94a-761fbeba93c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245815049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3245815049
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2007840444
Short name T54
Test name
Test status
Simulation time 8127645660 ps
CPU time 21.21 seconds
Started Dec 27 12:40:54 PM PST 23
Finished Dec 27 12:42:19 PM PST 23
Peak memory 200772 kb
Host smart-1577759a-f284-4218-84ad-ac1f279f2b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007840444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2007840444
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1339940182
Short name T191
Test name
Test status
Simulation time 505192288985 ps
CPU time 609.66 seconds
Started Dec 27 12:37:55 PM PST 23
Finished Dec 27 12:48:13 PM PST 23
Peak memory 200740 kb
Host smart-9a46360e-5baa-4741-9493-b459b63c0fb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339940182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1339940182
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1705977139
Short name T131
Test name
Test status
Simulation time 484989276882 ps
CPU time 279.45 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 200760 kb
Host smart-d3e7a798-93cf-4f7c-852c-014d7a9e5fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705977139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1705977139
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3614538664
Short name T190
Test name
Test status
Simulation time 492771106282 ps
CPU time 273.17 seconds
Started Dec 27 12:40:15 PM PST 23
Finished Dec 27 12:45:40 PM PST 23
Peak memory 200436 kb
Host smart-1db2ed4f-c50a-45f9-8e98-64d3ed312188
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614538664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3614538664
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3054897902
Short name T142
Test name
Test status
Simulation time 494345197617 ps
CPU time 70.53 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:42:46 PM PST 23
Peak memory 200560 kb
Host smart-e4eb600d-3d55-4d3c-b53e-5bf2d715b9c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054897902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3054897902
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2403323614
Short name T83
Test name
Test status
Simulation time 901004176 ps
CPU time 2.61 seconds
Started Dec 27 12:40:20 PM PST 23
Finished Dec 27 12:41:17 PM PST 23
Peak memory 200632 kb
Host smart-732f5c13-45a1-414d-8d32-a387a7bfb269
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403323614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2403323614
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.264586735
Short name T164
Test name
Test status
Simulation time 223866916959 ps
CPU time 373.86 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:44:45 PM PST 23
Peak memory 217612 kb
Host smart-d4613bde-286a-47e6-901d-8d97c0f244e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264586735 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.264586735
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1446942951
Short name T194
Test name
Test status
Simulation time 506145056542 ps
CPU time 267.78 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 200752 kb
Host smart-9e4b244b-f80d-4940-ba15-51a096b38464
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446942951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1446942951
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3788102175
Short name T41
Test name
Test status
Simulation time 7590873547 ps
CPU time 4.57 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:38:02 PM PST 23
Peak memory 216972 kb
Host smart-9e7631e3-b441-4426-b86c-68acb1452b33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788102175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3788102175
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1357280636
Short name T33
Test name
Test status
Simulation time 270650517725 ps
CPU time 360.33 seconds
Started Dec 27 12:39:16 PM PST 23
Finished Dec 27 12:45:42 PM PST 23
Peak memory 209384 kb
Host smart-47998877-d7ab-4cbd-8ec2-73666c8ce720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357280636 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1357280636
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1922608923
Short name T192
Test name
Test status
Simulation time 355632243286 ps
CPU time 153.24 seconds
Started Dec 27 12:38:21 PM PST 23
Finished Dec 27 12:41:04 PM PST 23
Peak memory 208992 kb
Host smart-055f158a-1871-4eee-b86f-1696aee98aa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922608923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1922608923
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1706737487
Short name T124
Test name
Test status
Simulation time 502818949710 ps
CPU time 166.96 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:40:56 PM PST 23
Peak memory 200816 kb
Host smart-455e8046-38ae-4f7d-8267-c16bee224a7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706737487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1706737487
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3875304510
Short name T108
Test name
Test status
Simulation time 270008589127 ps
CPU time 62.6 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:39:40 PM PST 23
Peak memory 209064 kb
Host smart-5a89dffd-58e2-45ea-b148-230ef80a5607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875304510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3875304510
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.540234878
Short name T257
Test name
Test status
Simulation time 485885870594 ps
CPU time 977.45 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:54:29 PM PST 23
Peak memory 200876 kb
Host smart-227f2b05-5366-4a36-b5bc-b9f73e88ec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540234878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.540234878
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3310844486
Short name T201
Test name
Test status
Simulation time 495365810217 ps
CPU time 547.02 seconds
Started Dec 27 12:37:48 PM PST 23
Finished Dec 27 12:47:00 PM PST 23
Peak memory 200736 kb
Host smart-822cfade-afab-4fe0-a8cd-eb3165fd8901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310844486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3310844486
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.155271021
Short name T196
Test name
Test status
Simulation time 214401971561 ps
CPU time 240.27 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:42:32 PM PST 23
Peak memory 200772 kb
Host smart-b8526737-9626-444c-9291-627476e1e246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155271021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
155271021
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2538914990
Short name T206
Test name
Test status
Simulation time 501541232851 ps
CPU time 498.06 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:45:57 PM PST 23
Peak memory 209460 kb
Host smart-787b79a7-6855-4bb3-878d-f48d0068ff43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538914990 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2538914990
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3780441758
Short name T325
Test name
Test status
Simulation time 491645887525 ps
CPU time 367.52 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:44:53 PM PST 23
Peak memory 200768 kb
Host smart-3c974e57-3e40-4631-a368-4b5d4708ddee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780441758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3780441758
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2959017634
Short name T35
Test name
Test status
Simulation time 169129211778 ps
CPU time 54.21 seconds
Started Dec 27 12:39:08 PM PST 23
Finished Dec 27 12:40:22 PM PST 23
Peak memory 200812 kb
Host smart-b3fc8a80-7516-4bb5-ae00-7a09e567fdef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959017634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2959017634
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3157871822
Short name T255
Test name
Test status
Simulation time 323579678519 ps
CPU time 384.68 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:44:06 PM PST 23
Peak memory 200788 kb
Host smart-7ef7576f-a616-4ac6-ac59-a3c92003c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157871822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3157871822
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1183828937
Short name T151
Test name
Test status
Simulation time 328641177226 ps
CPU time 197.01 seconds
Started Dec 27 12:37:34 PM PST 23
Finished Dec 27 12:41:04 PM PST 23
Peak memory 200796 kb
Host smart-d7b699e7-8158-450c-9d89-b2fb8b4eda47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183828937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1183828937
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.457170409
Short name T233
Test name
Test status
Simulation time 533189548745 ps
CPU time 977.51 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:54:45 PM PST 23
Peak memory 200788 kb
Host smart-a45c5bbe-6930-4fd9-8be0-388b2530abd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457170409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
457170409
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3963543225
Short name T283
Test name
Test status
Simulation time 316115840559 ps
CPU time 722.6 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:49:37 PM PST 23
Peak memory 200732 kb
Host smart-b7660d7e-c666-4ed6-a3f2-262b7c76b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963543225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3963543225
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3484505757
Short name T153
Test name
Test status
Simulation time 325104286249 ps
CPU time 97.64 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:40:28 PM PST 23
Peak memory 200796 kb
Host smart-a680e4a3-2d45-4527-9b66-18ea2fea75e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484505757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3484505757
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.901825072
Short name T247
Test name
Test status
Simulation time 295741844844 ps
CPU time 268.93 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:42:17 PM PST 23
Peak memory 209492 kb
Host smart-5f28d184-15ce-4999-9a85-0aec09691455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901825072 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.901825072
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.299927476
Short name T185
Test name
Test status
Simulation time 331538818216 ps
CPU time 741.95 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:50:19 PM PST 23
Peak memory 200768 kb
Host smart-e3e2fade-4b79-40aa-97c8-e0903e0d355a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299927476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.299927476
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2725474032
Short name T334
Test name
Test status
Simulation time 332348396190 ps
CPU time 195.18 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200776 kb
Host smart-af0ea786-dd66-4154-bbad-52dedb9b85ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725474032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2725474032
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3272699897
Short name T127
Test name
Test status
Simulation time 494736130783 ps
CPU time 1055.77 seconds
Started Dec 27 12:37:04 PM PST 23
Finished Dec 27 12:55:04 PM PST 23
Peak memory 200812 kb
Host smart-2d188356-e98e-4c55-b43e-30bbbca861d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272699897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3272699897
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1483202760
Short name T315
Test name
Test status
Simulation time 480412128555 ps
CPU time 182.35 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:42:08 PM PST 23
Peak memory 200736 kb
Host smart-20ce4c81-896e-40f9-8afa-9cedfe83f5c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483202760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1483202760
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1915295588
Short name T148
Test name
Test status
Simulation time 492408876094 ps
CPU time 270.64 seconds
Started Dec 27 12:37:27 PM PST 23
Finished Dec 27 12:42:13 PM PST 23
Peak memory 200744 kb
Host smart-0ebfbbdf-4929-4efa-a045-cdddd21aef15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915295588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1915295588
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.445432156
Short name T166
Test name
Test status
Simulation time 90986821093 ps
CPU time 313.56 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 201352 kb
Host smart-5a32a180-e1d0-482a-8197-d97b7fc0f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445432156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.445432156
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.919631453
Short name T232
Test name
Test status
Simulation time 289837329662 ps
CPU time 862.39 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:53:04 PM PST 23
Peak memory 209560 kb
Host smart-ac84df10-f02a-4fe1-bfcf-d03ae9064ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919631453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
919631453
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1579549477
Short name T313
Test name
Test status
Simulation time 490192326319 ps
CPU time 279.66 seconds
Started Dec 27 12:40:32 PM PST 23
Finished Dec 27 12:46:10 PM PST 23
Peak memory 200588 kb
Host smart-c0c940c9-9cf0-43b5-a839-6421f58f98a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579549477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1579549477
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1147233391
Short name T281
Test name
Test status
Simulation time 159458512814 ps
CPU time 357.95 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:43:39 PM PST 23
Peak memory 200760 kb
Host smart-aae44486-3e90-43e8-8c33-f9b68688832d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147233391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1147233391
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1224483260
Short name T241
Test name
Test status
Simulation time 167445466173 ps
CPU time 182.54 seconds
Started Dec 27 12:38:03 PM PST 23
Finished Dec 27 12:41:14 PM PST 23
Peak memory 209612 kb
Host smart-b75ba1c1-3c7c-4604-9b6d-28dd69d783ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224483260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1224483260
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3128336888
Short name T259
Test name
Test status
Simulation time 166259157302 ps
CPU time 403.01 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:44:55 PM PST 23
Peak memory 200756 kb
Host smart-add77296-9057-45bd-9f7d-40d2617591d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128336888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3128336888
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3506207869
Short name T314
Test name
Test status
Simulation time 176002797792 ps
CPU time 387.14 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:44:41 PM PST 23
Peak memory 200740 kb
Host smart-6f805256-da51-4715-a08c-6e918a357ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506207869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3506207869
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2802812021
Short name T268
Test name
Test status
Simulation time 332571544949 ps
CPU time 183.71 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:41:27 PM PST 23
Peak memory 200668 kb
Host smart-e208c16b-e59a-43c0-94df-f2b8f208cadd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802812021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2802812021
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2251846017
Short name T197
Test name
Test status
Simulation time 324778886940 ps
CPU time 285.38 seconds
Started Dec 27 12:38:56 PM PST 23
Finished Dec 27 12:43:57 PM PST 23
Peak memory 200740 kb
Host smart-a507fce5-0da1-4e82-9293-c9753980fe78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251846017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2251846017
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3047995627
Short name T320
Test name
Test status
Simulation time 418719378542 ps
CPU time 1280.1 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:59:14 PM PST 23
Peak memory 209440 kb
Host smart-ec195a5f-220d-410c-82f9-8d7acc900e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047995627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3047995627
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.937991783
Short name T38
Test name
Test status
Simulation time 478842397 ps
CPU time 0.69 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:38:06 PM PST 23
Peak memory 200476 kb
Host smart-13333250-af1b-4867-a7ef-d93c0a7fab46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937991783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.937991783
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2830526377
Short name T282
Test name
Test status
Simulation time 325673459581 ps
CPU time 208.68 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:41:18 PM PST 23
Peak memory 200836 kb
Host smart-ee6af8b0-9140-46b9-9e40-12f009d745a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830526377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2830526377
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3124140954
Short name T175
Test name
Test status
Simulation time 134586274302 ps
CPU time 476.22 seconds
Started Dec 27 12:37:45 PM PST 23
Finished Dec 27 12:45:48 PM PST 23
Peak memory 201136 kb
Host smart-db7c45a1-7df6-4352-8af5-6d32d8037311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124140954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3124140954
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.221354427
Short name T272
Test name
Test status
Simulation time 512523087874 ps
CPU time 806.28 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:52:29 PM PST 23
Peak memory 200764 kb
Host smart-04424570-bc2f-495f-af38-8ce02748d171
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221354427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.221354427
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2687348202
Short name T184
Test name
Test status
Simulation time 166527824864 ps
CPU time 100.85 seconds
Started Dec 27 12:38:19 PM PST 23
Finished Dec 27 12:40:08 PM PST 23
Peak memory 200748 kb
Host smart-e42688c4-3f7f-4ac8-a21f-ef3d1576583c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687348202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2687348202
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.891937990
Short name T335
Test name
Test status
Simulation time 489834228617 ps
CPU time 1053.69 seconds
Started Dec 27 12:40:04 PM PST 23
Finished Dec 27 12:58:27 PM PST 23
Peak memory 200476 kb
Host smart-4acdbcc6-4134-4770-9759-39a0dc98b981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891937990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.891937990
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1889066749
Short name T59
Test name
Test status
Simulation time 8423399046 ps
CPU time 7.32 seconds
Started Dec 27 12:40:53 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 200708 kb
Host smart-cd2fbfcf-20a8-4922-b4eb-aed599193114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889066749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1889066749
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1962239493
Short name T330
Test name
Test status
Simulation time 375980273844 ps
CPU time 74.17 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:38:38 PM PST 23
Peak memory 200792 kb
Host smart-f24e57a8-7e49-4950-a48e-f3ba16409861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962239493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1962239493
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3445191437
Short name T319
Test name
Test status
Simulation time 474689577287 ps
CPU time 809.06 seconds
Started Dec 27 12:37:27 PM PST 23
Finished Dec 27 12:51:12 PM PST 23
Peak memory 209540 kb
Host smart-2b6b5460-ddec-4fa5-9f6a-6dec7649cdaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445191437 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3445191437
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2647552264
Short name T322
Test name
Test status
Simulation time 496311532109 ps
CPU time 986.58 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:54:32 PM PST 23
Peak memory 200772 kb
Host smart-123108ae-0ea6-4ad1-acab-298c6c2ad909
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647552264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2647552264
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.4076016377
Short name T285
Test name
Test status
Simulation time 169058355334 ps
CPU time 22.11 seconds
Started Dec 27 12:37:21 PM PST 23
Finished Dec 27 12:38:03 PM PST 23
Peak memory 200876 kb
Host smart-a259355b-15d0-4186-b622-905b6e6b206e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076016377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.4076016377
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.716245775
Short name T271
Test name
Test status
Simulation time 163419402438 ps
CPU time 239.29 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:42:09 PM PST 23
Peak memory 200768 kb
Host smart-75f5a805-0df0-4b2a-b4fe-edd434096837
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716245775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.716245775
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3751957369
Short name T323
Test name
Test status
Simulation time 487864653176 ps
CPU time 302.61 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:43:34 PM PST 23
Peak memory 200848 kb
Host smart-39c3551a-f968-42f4-ac2f-f64e4664efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751957369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3751957369
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2523285033
Short name T354
Test name
Test status
Simulation time 508176813 ps
CPU time 1.77 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 200208 kb
Host smart-9b67ad3a-4ee5-441a-9179-c33e650cc8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523285033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2523285033
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2217532902
Short name T336
Test name
Test status
Simulation time 163670571075 ps
CPU time 20.89 seconds
Started Dec 27 12:38:06 PM PST 23
Finished Dec 27 12:38:34 PM PST 23
Peak memory 199548 kb
Host smart-d3acbf23-1e9a-473f-8529-201d8b55e5f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217532902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2217532902
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.322012460
Short name T180
Test name
Test status
Simulation time 290102331264 ps
CPU time 383.27 seconds
Started Dec 27 12:37:21 PM PST 23
Finished Dec 27 12:44:04 PM PST 23
Peak memory 209536 kb
Host smart-c0532495-195d-4fbe-8165-cfd1f169b438
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322012460 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.322012460
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3660671002
Short name T205
Test name
Test status
Simulation time 490845136651 ps
CPU time 1218.3 seconds
Started Dec 27 12:37:38 PM PST 23
Finished Dec 27 12:58:08 PM PST 23
Peak memory 200808 kb
Host smart-36c40254-7e15-486b-a9b9-e357eb1845cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660671002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3660671002
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2171229793
Short name T161
Test name
Test status
Simulation time 506417165004 ps
CPU time 601.12 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:48:34 PM PST 23
Peak memory 200800 kb
Host smart-88241ab8-b344-4303-ba53-7bc3f6f64826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171229793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2171229793
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3602785638
Short name T238
Test name
Test status
Simulation time 158457037868 ps
CPU time 82.68 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:40:19 PM PST 23
Peak memory 200872 kb
Host smart-5a2bda2f-4ecf-4803-b3c2-9c16d8bca12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602785638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3602785638
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3961579102
Short name T296
Test name
Test status
Simulation time 324717958905 ps
CPU time 393.59 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:45:16 PM PST 23
Peak memory 200808 kb
Host smart-78abbc05-f6e4-4e54-aebf-abf2e450e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961579102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3961579102
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1889215710
Short name T174
Test name
Test status
Simulation time 128775950377 ps
CPU time 443.04 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:46:04 PM PST 23
Peak memory 201168 kb
Host smart-f938ba3a-7695-4e8f-8cb5-186da214224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889215710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1889215710
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.9513957
Short name T219
Test name
Test status
Simulation time 164045941645 ps
CPU time 419.51 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:45:15 PM PST 23
Peak memory 200744 kb
Host smart-6777427b-9eb2-4443-85ba-bdf69612453f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9513957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_wa
keup.9513957
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3487689467
Short name T261
Test name
Test status
Simulation time 485314097904 ps
CPU time 133.6 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:40:37 PM PST 23
Peak memory 200920 kb
Host smart-3816d8e5-d756-4bfd-9e76-3b47895e1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487689467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3487689467
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2122648846
Short name T295
Test name
Test status
Simulation time 144910107015 ps
CPU time 386.05 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:45:15 PM PST 23
Peak memory 217216 kb
Host smart-96d89dfc-2553-476b-aade-d50e4902d91d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122648846 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2122648846
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.4170197664
Short name T276
Test name
Test status
Simulation time 495877683573 ps
CPU time 1169.48 seconds
Started Dec 27 12:38:52 PM PST 23
Finished Dec 27 12:58:36 PM PST 23
Peak memory 200768 kb
Host smart-2e9f572b-c5b0-47a1-b111-7a6a69bfefc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170197664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.4170197664
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3216824719
Short name T101
Test name
Test status
Simulation time 55647382476 ps
CPU time 103.61 seconds
Started Dec 27 12:40:03 PM PST 23
Finished Dec 27 12:42:36 PM PST 23
Peak memory 208800 kb
Host smart-c7d196a6-aeee-4f8a-8987-f55dc2d3724f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216824719 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3216824719
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1628981270
Short name T299
Test name
Test status
Simulation time 500868182555 ps
CPU time 576.82 seconds
Started Dec 27 12:37:33 PM PST 23
Finished Dec 27 12:47:24 PM PST 23
Peak memory 200804 kb
Host smart-fd5e3268-883a-47a4-bd70-f45a02bea4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628981270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1628981270
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4233796337
Short name T171
Test name
Test status
Simulation time 131064030368 ps
CPU time 426.3 seconds
Started Dec 27 12:37:39 PM PST 23
Finished Dec 27 12:44:56 PM PST 23
Peak memory 201196 kb
Host smart-5c00ff02-00a1-4ed6-963d-054f41976c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233796337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4233796337
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2871027766
Short name T162
Test name
Test status
Simulation time 1477655141 ps
CPU time 3.08 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:03 PM PST 23
Peak memory 200652 kb
Host smart-29f4905c-5ece-4583-993c-72997cf7bf8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871027766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2871027766
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.322314613
Short name T90
Test name
Test status
Simulation time 26800077276 ps
CPU time 32.33 seconds
Started Dec 27 12:40:26 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200764 kb
Host smart-d797e0ca-4645-43c9-a2a1-cafa5bccb110
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322314613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.322314613
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.681155186
Short name T371
Test name
Test status
Simulation time 1186407139 ps
CPU time 3.56 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 200492 kb
Host smart-55ef6c72-2add-4c49-b088-b05b884e10be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681155186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.681155186
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3140066643
Short name T908
Test name
Test status
Simulation time 362328025 ps
CPU time 1.56 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 200556 kb
Host smart-2ec3fc96-96a4-4fbd-9900-272a454ad7db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140066643 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3140066643
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2453297533
Short name T86
Test name
Test status
Simulation time 398247922 ps
CPU time 0.92 seconds
Started Dec 27 12:40:44 PM PST 23
Finished Dec 27 12:41:47 PM PST 23
Peak memory 200476 kb
Host smart-f1cb63b3-fe3c-41a6-8da2-538781d2a3ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453297533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2453297533
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.599557322
Short name T2
Test name
Test status
Simulation time 5131827866 ps
CPU time 3.62 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:46 PM PST 23
Peak memory 200716 kb
Host smart-67adb641-0f3c-4ef3-b4fc-88f23c6e76f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599557322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.599557322
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1961802293
Short name T386
Test name
Test status
Simulation time 991386977 ps
CPU time 2.64 seconds
Started Dec 27 12:40:19 PM PST 23
Finished Dec 27 12:41:15 PM PST 23
Peak memory 216528 kb
Host smart-e3654ad6-5e78-47cc-a976-0aaaaa5ab587
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961802293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1961802293
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.29303190
Short name T902
Test name
Test status
Simulation time 8326532064 ps
CPU time 7.63 seconds
Started Dec 27 12:40:34 PM PST 23
Finished Dec 27 12:41:40 PM PST 23
Peak memory 200648 kb
Host smart-7f56b803-d720-4dca-a726-b6bc862c181c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29303190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_intg
_err.29303190
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3894955491
Short name T361
Test name
Test status
Simulation time 1312284483 ps
CPU time 5.8 seconds
Started Dec 27 12:40:31 PM PST 23
Finished Dec 27 12:41:36 PM PST 23
Peak memory 200680 kb
Host smart-250065f1-4c10-439a-85d5-bef9e72c9b95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894955491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3894955491
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.530863550
Short name T84
Test name
Test status
Simulation time 18217736705 ps
CPU time 18.41 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:42:05 PM PST 23
Peak memory 200756 kb
Host smart-55f6b194-7156-4768-85a3-cdfd119d8bc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530863550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.530863550
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.254470995
Short name T396
Test name
Test status
Simulation time 1060014316 ps
CPU time 0.97 seconds
Started Dec 27 12:40:29 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 200496 kb
Host smart-605dc57b-69b5-4b8e-9c73-429b62e6416d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254470995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.254470995
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2468707281
Short name T359
Test name
Test status
Simulation time 610719206 ps
CPU time 1 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 12:41:57 PM PST 23
Peak memory 200484 kb
Host smart-d3ac6527-aeb5-492c-a50d-eb01df3aec86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468707281 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2468707281
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4124052725
Short name T89
Test name
Test status
Simulation time 505469713 ps
CPU time 1.34 seconds
Started Dec 27 12:40:31 PM PST 23
Finished Dec 27 12:41:29 PM PST 23
Peak memory 200464 kb
Host smart-2f39aa8c-4788-4d11-86f6-289a0e967ab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124052725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4124052725
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1275653791
Short name T24
Test name
Test status
Simulation time 455659110 ps
CPU time 0.77 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 12:41:47 PM PST 23
Peak memory 200348 kb
Host smart-2a19bbb1-d60b-4c5e-a098-ec163b522602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275653791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1275653791
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.648959804
Short name T29
Test name
Test status
Simulation time 2519774886 ps
CPU time 3.88 seconds
Started Dec 27 12:40:31 PM PST 23
Finished Dec 27 12:41:31 PM PST 23
Peak memory 200596 kb
Host smart-8082df66-dc54-4ba9-916c-e4b8f783d84b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648959804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.648959804
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2834485047
Short name T872
Test name
Test status
Simulation time 1005240234 ps
CPU time 2.73 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200796 kb
Host smart-ff4d9b5d-c699-47c3-b61e-6a787c0a23b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834485047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2834485047
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.710028782
Short name T400
Test name
Test status
Simulation time 4326072234 ps
CPU time 10.74 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:41:46 PM PST 23
Peak memory 200784 kb
Host smart-44b96d5a-7635-4c99-8537-bb7e0bdc6438
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710028782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.710028782
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1675141449
Short name T7
Test name
Test status
Simulation time 664113895 ps
CPU time 1.4 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:01 PM PST 23
Peak memory 200768 kb
Host smart-56fbb4bf-f8b7-4a0a-99c6-ca23db61f148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675141449 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1675141449
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.367667439
Short name T88
Test name
Test status
Simulation time 466633075 ps
CPU time 0.85 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:41:57 PM PST 23
Peak memory 200496 kb
Host smart-5c3f520e-710c-4bc6-a65d-2550839d26fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367667439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.367667439
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.469373406
Short name T363
Test name
Test status
Simulation time 2036954952 ps
CPU time 3.88 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200512 kb
Host smart-d60fe377-6f31-4dc9-9f42-573dbfff8caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469373406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.469373406
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1183811103
Short name T55
Test name
Test status
Simulation time 604730056 ps
CPU time 1.87 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 216552 kb
Host smart-0d256806-2662-4b3a-96b1-960cc7918c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183811103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1183811103
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.466772273
Short name T6
Test name
Test status
Simulation time 4179962367 ps
CPU time 8.97 seconds
Started Dec 27 12:40:53 PM PST 23
Finished Dec 27 12:42:06 PM PST 23
Peak memory 200708 kb
Host smart-3d990b3c-261b-4cc6-93d8-2e1c41e3a139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466772273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.466772273
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.802243670
Short name T405
Test name
Test status
Simulation time 435573759 ps
CPU time 1.65 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200484 kb
Host smart-4e87bf62-6bd6-4c86-90de-e5dc8733050b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802243670 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.802243670
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2632042029
Short name T93
Test name
Test status
Simulation time 449794427 ps
CPU time 0.94 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200480 kb
Host smart-d7e78ab4-b2ad-46ce-abbc-93d0748718b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632042029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2632042029
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3553510826
Short name T888
Test name
Test status
Simulation time 499418882 ps
CPU time 0.89 seconds
Started Dec 27 12:40:53 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200244 kb
Host smart-c4c5f07b-ae88-4ed9-8cdd-b583e8ee8958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553510826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3553510826
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1165223085
Short name T8
Test name
Test status
Simulation time 4506102092 ps
CPU time 15.66 seconds
Started Dec 27 12:40:29 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200740 kb
Host smart-01728845-fcc8-4233-a610-b506bff2402b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165223085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1165223085
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.979642322
Short name T382
Test name
Test status
Simulation time 571527914 ps
CPU time 2.12 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 200748 kb
Host smart-538d239c-0f4c-40c2-8f3e-fc2a1f03d53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979642322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.979642322
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.335262275
Short name T388
Test name
Test status
Simulation time 7854172714 ps
CPU time 6.9 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 200768 kb
Host smart-2be3f92f-e96c-486a-a4a8-ec852c2f7986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335262275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.335262275
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4067413280
Short name T887
Test name
Test status
Simulation time 699193361 ps
CPU time 1.1 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 200556 kb
Host smart-6a394d0e-6c01-41ba-863f-c90d55000ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067413280 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4067413280
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3485863228
Short name T892
Test name
Test status
Simulation time 351216724 ps
CPU time 1.47 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:38 PM PST 23
Peak memory 200440 kb
Host smart-2ba253da-759f-427b-b6c8-8ff77be4fe3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485863228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3485863228
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3913043869
Short name T893
Test name
Test status
Simulation time 359639037 ps
CPU time 0.83 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 12:42:01 PM PST 23
Peak memory 200128 kb
Host smart-41c9950c-a887-4c5d-b102-dbc0138c0411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913043869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3913043869
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3367897532
Short name T895
Test name
Test status
Simulation time 2499648124 ps
CPU time 4.87 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 12:42:17 PM PST 23
Peak memory 200508 kb
Host smart-4c953a47-e699-42cc-bd90-1f260e59bec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367897532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3367897532
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4007237056
Short name T911
Test name
Test status
Simulation time 475083725 ps
CPU time 1.24 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:42 PM PST 23
Peak memory 200796 kb
Host smart-2bee97a7-e4f9-4286-a31d-45817a482b45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007237056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4007237056
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1714498244
Short name T913
Test name
Test status
Simulation time 7938222816 ps
CPU time 7.69 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:57 PM PST 23
Peak memory 200744 kb
Host smart-0bde1613-fa2f-4fcc-86b5-5c51728d3977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714498244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1714498244
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2531241838
Short name T355
Test name
Test status
Simulation time 510678024 ps
CPU time 1.06 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200528 kb
Host smart-3f639cfa-21a8-42d6-9bde-44531b29b48b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531241838 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2531241838
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.88659997
Short name T375
Test name
Test status
Simulation time 330615045 ps
CPU time 1.52 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200488 kb
Host smart-83e5bd40-acf6-478f-90c3-b17c8c9509ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88659997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.88659997
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3350508588
Short name T81
Test name
Test status
Simulation time 441151717 ps
CPU time 0.84 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:42:05 PM PST 23
Peak memory 200352 kb
Host smart-c5f1d573-9a3c-4df8-9bf0-c35e15566e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350508588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3350508588
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.234071208
Short name T30
Test name
Test status
Simulation time 2414308212 ps
CPU time 2.77 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:09 PM PST 23
Peak memory 200424 kb
Host smart-d8a996d9-af18-4b07-a079-52b7ab323d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234071208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.234071208
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3103429792
Short name T909
Test name
Test status
Simulation time 660392330 ps
CPU time 2.27 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 12:42:11 PM PST 23
Peak memory 208924 kb
Host smart-d7cdc9bd-368e-4211-b576-5daaefdb02f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103429792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3103429792
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3346323545
Short name T401
Test name
Test status
Simulation time 4252447299 ps
CPU time 10.19 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:47 PM PST 23
Peak memory 200736 kb
Host smart-c80c7cd2-0355-4ce0-b16a-9458818f1b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346323545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3346323545
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1459164365
Short name T395
Test name
Test status
Simulation time 626574794 ps
CPU time 0.9 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 12:42:13 PM PST 23
Peak memory 200512 kb
Host smart-7a19c710-8ee9-4cc4-bff2-ab570a296754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459164365 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1459164365
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3874658547
Short name T67
Test name
Test status
Simulation time 430138299 ps
CPU time 1.13 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:42:17 PM PST 23
Peak memory 200476 kb
Host smart-b2e3bec4-17d9-4f47-afc9-62cb44559b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874658547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3874658547
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2566564933
Short name T903
Test name
Test status
Simulation time 397760550 ps
CPU time 1.5 seconds
Started Dec 27 12:40:33 PM PST 23
Finished Dec 27 12:41:33 PM PST 23
Peak memory 200404 kb
Host smart-8ab86c60-ec87-4504-b36d-76879d39684c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566564933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2566564933
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4050227101
Short name T906
Test name
Test status
Simulation time 681192131 ps
CPU time 2.58 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 209024 kb
Host smart-2a938bc9-c57f-4f01-973e-3d173c2c48a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050227101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4050227101
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3951677898
Short name T92
Test name
Test status
Simulation time 499209989 ps
CPU time 1.05 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 200492 kb
Host smart-c5c7ebde-18e4-44d1-9b2d-ebdc46cf9017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951677898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3951677898
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2858665627
Short name T377
Test name
Test status
Simulation time 379024573 ps
CPU time 1.46 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 200196 kb
Host smart-2813a9bc-7691-4a9b-a9d1-6dd5c1be1be6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858665627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2858665627
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.420514066
Short name T884
Test name
Test status
Simulation time 4547351173 ps
CPU time 10.41 seconds
Started Dec 27 12:40:44 PM PST 23
Finished Dec 27 12:41:55 PM PST 23
Peak memory 200740 kb
Host smart-4e88673e-94b5-45af-aba9-82e0bce8b202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420514066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.420514066
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2024208810
Short name T381
Test name
Test status
Simulation time 582433863 ps
CPU time 1.71 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:08 PM PST 23
Peak memory 200716 kb
Host smart-4c2d825c-0113-4ebe-960b-ae3e192aa6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024208810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2024208810
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4109278129
Short name T71
Test name
Test status
Simulation time 4639259407 ps
CPU time 4.11 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 200772 kb
Host smart-f77ed90d-357c-438f-98f8-c36204480f90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109278129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4109278129
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2253490288
Short name T27
Test name
Test status
Simulation time 575143387 ps
CPU time 1.07 seconds
Started Dec 27 12:41:07 PM PST 23
Finished Dec 27 12:42:12 PM PST 23
Peak memory 200552 kb
Host smart-ad9789bb-50e9-44a1-b2cf-5d2b4ce4a62b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253490288 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2253490288
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2722914068
Short name T904
Test name
Test status
Simulation time 474668950 ps
CPU time 1.23 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 200476 kb
Host smart-49a55938-e7b6-4f7f-b1f7-c698f9bd8ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722914068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2722914068
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.4210223923
Short name T915
Test name
Test status
Simulation time 363076277 ps
CPU time 0.79 seconds
Started Dec 27 12:41:11 PM PST 23
Finished Dec 27 12:42:16 PM PST 23
Peak memory 200204 kb
Host smart-6af6aac2-b83d-4807-af9b-99eacb1edc58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210223923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.4210223923
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1496826865
Short name T881
Test name
Test status
Simulation time 4246465649 ps
CPU time 10.3 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200788 kb
Host smart-fc4705ed-5f0b-48f7-8a8f-0ab4d7f1889d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496826865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1496826865
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2232936223
Short name T70
Test name
Test status
Simulation time 536634924 ps
CPU time 2.33 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 200708 kb
Host smart-a73969c8-2bd4-42b8-9871-88a941b8be35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232936223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2232936223
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1074752813
Short name T394
Test name
Test status
Simulation time 8655679782 ps
CPU time 22.61 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 12:42:09 PM PST 23
Peak memory 200768 kb
Host smart-7e9d2149-f1df-43bc-adfd-3133e4647531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074752813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1074752813
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4157660695
Short name T25
Test name
Test status
Simulation time 499384685 ps
CPU time 1.23 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:49 PM PST 23
Peak memory 200616 kb
Host smart-03bfd03e-2f9a-432b-9618-801a3b2b5a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157660695 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4157660695
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3506036478
Short name T367
Test name
Test status
Simulation time 445560633 ps
CPU time 1.1 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 200440 kb
Host smart-567bcaa9-5701-4b91-a08b-35b1aabae376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506036478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3506036478
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2052385646
Short name T74
Test name
Test status
Simulation time 376936501 ps
CPU time 1.58 seconds
Started Dec 27 12:40:48 PM PST 23
Finished Dec 27 12:41:52 PM PST 23
Peak memory 200380 kb
Host smart-cd914361-4ffa-4058-938e-bf595c94ce9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052385646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2052385646
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2969985990
Short name T390
Test name
Test status
Simulation time 4032268817 ps
CPU time 5.34 seconds
Started Dec 27 12:40:54 PM PST 23
Finished Dec 27 12:42:03 PM PST 23
Peak memory 200760 kb
Host smart-1d8bf398-b518-41b8-abc9-9144ae8459b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969985990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2969985990
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1805177313
Short name T905
Test name
Test status
Simulation time 1525131639 ps
CPU time 3.25 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 200712 kb
Host smart-3355804d-2a48-4361-a7e9-948ceb6a475c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805177313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1805177313
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1483666051
Short name T60
Test name
Test status
Simulation time 8420757150 ps
CPU time 8.72 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 200756 kb
Host smart-87acc413-8327-4336-a35e-607a8bf2fc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483666051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1483666051
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.620646055
Short name T379
Test name
Test status
Simulation time 503622549 ps
CPU time 1.97 seconds
Started Dec 27 12:40:57 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 200540 kb
Host smart-89ee2f88-8374-45d5-ae98-2f8a5cecab6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620646055 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.620646055
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4024388383
Short name T392
Test name
Test status
Simulation time 487144817 ps
CPU time 1.79 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:15 PM PST 23
Peak memory 200468 kb
Host smart-4ca6cb49-8b8c-42af-ab1a-549407cfb62c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024388383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4024388383
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3973631940
Short name T406
Test name
Test status
Simulation time 500186322 ps
CPU time 1.17 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 12:42:01 PM PST 23
Peak memory 200408 kb
Host smart-312fc0ea-b470-4d83-8afb-4d91e9edc7a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973631940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3973631940
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1776349516
Short name T878
Test name
Test status
Simulation time 4482380883 ps
CPU time 14.56 seconds
Started Dec 27 12:40:58 PM PST 23
Finished Dec 27 12:42:17 PM PST 23
Peak memory 200744 kb
Host smart-0e9c2913-02c6-4bee-b5c4-9b53c539cc53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776349516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1776349516
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.434982510
Short name T72
Test name
Test status
Simulation time 593654123 ps
CPU time 1.79 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200668 kb
Host smart-c15a8bfc-1da6-4daa-a380-cbe301be6244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434982510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.434982510
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2720201040
Short name T12
Test name
Test status
Simulation time 8047627654 ps
CPU time 7.23 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 200832 kb
Host smart-f1971012-5514-4d8d-9df0-3ee92f6db927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720201040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2720201040
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3657514084
Short name T77
Test name
Test status
Simulation time 608990325 ps
CPU time 1.66 seconds
Started Dec 27 12:40:53 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200528 kb
Host smart-341bbc54-9397-4159-8842-62469d041d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657514084 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3657514084
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1139454530
Short name T66
Test name
Test status
Simulation time 578152760 ps
CPU time 1.01 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 200508 kb
Host smart-cdf0d804-b592-4b58-a3cd-e170a818a1f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139454530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1139454530
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.880274809
Short name T891
Test name
Test status
Simulation time 475318734 ps
CPU time 0.78 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 200308 kb
Host smart-1e7dbd42-8ce7-41ca-967d-fe003d7a99eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880274809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.880274809
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4190241372
Short name T75
Test name
Test status
Simulation time 3828396376 ps
CPU time 4.8 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:42:01 PM PST 23
Peak memory 200812 kb
Host smart-01af372b-9e8b-48ad-a926-eccb3a6b23b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190241372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4190241372
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2441699443
Short name T889
Test name
Test status
Simulation time 405549172 ps
CPU time 2.28 seconds
Started Dec 27 12:40:53 PM PST 23
Finished Dec 27 12:41:59 PM PST 23
Peak memory 200748 kb
Host smart-9a9a8366-8dbd-4243-8c6a-d611cc357ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441699443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2441699443
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3571846325
Short name T68
Test name
Test status
Simulation time 4587620639 ps
CPU time 4.23 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 200760 kb
Host smart-e41abd53-f8e5-424f-b827-b3b87fbec822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571846325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3571846325
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3156220086
Short name T876
Test name
Test status
Simulation time 26957380726 ps
CPU time 56.92 seconds
Started Dec 27 12:40:34 PM PST 23
Finished Dec 27 12:42:29 PM PST 23
Peak memory 200772 kb
Host smart-2276f498-793c-42cb-8b51-88661dc60346
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156220086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3156220086
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2478807794
Short name T907
Test name
Test status
Simulation time 668630334 ps
CPU time 2.1 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200468 kb
Host smart-355b38cf-9c06-4535-8c72-299ee69cdeb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478807794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2478807794
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3680911362
Short name T899
Test name
Test status
Simulation time 484561706 ps
CPU time 1.03 seconds
Started Dec 27 12:40:33 PM PST 23
Finished Dec 27 12:41:32 PM PST 23
Peak memory 200508 kb
Host smart-fb4bba29-c120-4de8-84d4-ce047ec33cda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680911362 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3680911362
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3036666803
Short name T369
Test name
Test status
Simulation time 583707348 ps
CPU time 1.12 seconds
Started Dec 27 12:40:31 PM PST 23
Finished Dec 27 12:41:29 PM PST 23
Peak memory 200472 kb
Host smart-814b5b51-3abf-411a-9b9e-40ac66f24ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036666803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3036666803
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.939669597
Short name T901
Test name
Test status
Simulation time 394780325 ps
CPU time 1.42 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 200404 kb
Host smart-34a05cbf-e35b-478c-8326-a98c27037aa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939669597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.939669597
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3656793291
Short name T376
Test name
Test status
Simulation time 1963735975 ps
CPU time 1.7 seconds
Started Dec 27 12:40:48 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200508 kb
Host smart-2fd3bf1f-facd-4e64-95ea-2d52a17d7e9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656793291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3656793291
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1812199501
Short name T879
Test name
Test status
Simulation time 491216144 ps
CPU time 2.46 seconds
Started Dec 27 12:40:32 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200776 kb
Host smart-e5386e68-f1d8-4261-aaf9-cdcc556a3c46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812199501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1812199501
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2464570596
Short name T387
Test name
Test status
Simulation time 9336962610 ps
CPU time 4.41 seconds
Started Dec 27 12:40:27 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 200832 kb
Host smart-777a47fa-ab11-4e16-96e0-21423effd533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464570596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2464570596
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2583695788
Short name T882
Test name
Test status
Simulation time 524602463 ps
CPU time 1.87 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 12:41:56 PM PST 23
Peak memory 200192 kb
Host smart-3bb11f2f-5644-42b9-bd51-800cd4baec89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583695788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2583695788
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2372640467
Short name T916
Test name
Test status
Simulation time 434973113 ps
CPU time 0.76 seconds
Started Dec 27 12:40:49 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200180 kb
Host smart-0ebdb12a-677d-47fd-9cfc-469d5c2e591c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372640467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2372640467
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.406731972
Short name T910
Test name
Test status
Simulation time 312575673 ps
CPU time 0.97 seconds
Started Dec 27 12:41:15 PM PST 23
Finished Dec 27 12:42:20 PM PST 23
Peak memory 200224 kb
Host smart-b487805a-65d8-4254-939c-130d0729b557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406731972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.406731972
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2920007832
Short name T65
Test name
Test status
Simulation time 434861284 ps
CPU time 1.02 seconds
Started Dec 27 12:40:49 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200168 kb
Host smart-36da53d8-da94-4e9a-9956-93444acf88e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920007832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2920007832
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1166004441
Short name T358
Test name
Test status
Simulation time 515697555 ps
CPU time 0.91 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:49 PM PST 23
Peak memory 200112 kb
Host smart-776fd5d9-32ea-4069-b09f-a2a2e2b63301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166004441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1166004441
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3064826357
Short name T378
Test name
Test status
Simulation time 382523191 ps
CPU time 1.57 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:42:06 PM PST 23
Peak memory 200168 kb
Host smart-2876f0ba-caf4-4b0a-b34f-7c9caa71baa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064826357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3064826357
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2377031359
Short name T897
Test name
Test status
Simulation time 441785444 ps
CPU time 0.85 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 12:41:57 PM PST 23
Peak memory 200184 kb
Host smart-36349a9f-cad8-4bdb-bc23-c94fb1599739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377031359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2377031359
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2731793314
Short name T373
Test name
Test status
Simulation time 372924783 ps
CPU time 1 seconds
Started Dec 27 12:40:57 PM PST 23
Finished Dec 27 12:42:02 PM PST 23
Peak memory 200368 kb
Host smart-09c14bb1-b566-46ca-b57f-c877ff043761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731793314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2731793314
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.31726377
Short name T890
Test name
Test status
Simulation time 336271984 ps
CPU time 0.74 seconds
Started Dec 27 12:41:04 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 200404 kb
Host smart-b1354a4b-bf41-4de6-90a0-9f4a2c0ed940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31726377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.31726377
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1888168717
Short name T877
Test name
Test status
Simulation time 398485219 ps
CPU time 1.08 seconds
Started Dec 27 12:40:50 PM PST 23
Finished Dec 27 12:41:55 PM PST 23
Peak memory 200200 kb
Host smart-91f79bd9-c59c-48c1-9330-e48dcd69054a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888168717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1888168717
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1043395770
Short name T393
Test name
Test status
Simulation time 845841355 ps
CPU time 1.92 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:41:42 PM PST 23
Peak memory 200676 kb
Host smart-9f5c1080-a441-4ebb-8e5e-313b23bc6864
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043395770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1043395770
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3367986978
Short name T11
Test name
Test status
Simulation time 16470254742 ps
CPU time 82.92 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:43:03 PM PST 23
Peak memory 200696 kb
Host smart-7a943a53-04b7-44ec-9b39-93ad19350cb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367986978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3367986978
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.170169368
Short name T85
Test name
Test status
Simulation time 1287570115 ps
CPU time 1.29 seconds
Started Dec 27 12:40:21 PM PST 23
Finished Dec 27 12:41:16 PM PST 23
Peak memory 200492 kb
Host smart-01199e3d-3fc7-4688-85c8-393da8aa8663
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170169368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.170169368
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2061366115
Short name T900
Test name
Test status
Simulation time 663335203 ps
CPU time 0.85 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200616 kb
Host smart-44259801-6016-4d88-9bb6-77b70a27958f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061366115 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2061366115
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.576308538
Short name T91
Test name
Test status
Simulation time 346387571 ps
CPU time 1.13 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 12:41:47 PM PST 23
Peak memory 200540 kb
Host smart-004aac10-0627-446d-81ac-4c70ece74cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576308538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.576308538
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.228658941
Short name T366
Test name
Test status
Simulation time 490763226 ps
CPU time 0.78 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200384 kb
Host smart-51385365-e244-4316-835c-0e8a4e426b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228658941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.228658941
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4252061085
Short name T3
Test name
Test status
Simulation time 4318167783 ps
CPU time 14.86 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:42:03 PM PST 23
Peak memory 200752 kb
Host smart-87f643d7-156d-40d2-b029-fdaada3eabda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252061085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4252061085
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3159865630
Short name T404
Test name
Test status
Simulation time 603335598 ps
CPU time 2.55 seconds
Started Dec 27 12:40:33 PM PST 23
Finished Dec 27 12:41:40 PM PST 23
Peak memory 200764 kb
Host smart-010b8ffa-df8f-46ca-9a2b-bc52d832a74b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159865630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3159865630
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3388127314
Short name T385
Test name
Test status
Simulation time 4682222718 ps
CPU time 5.29 seconds
Started Dec 27 12:40:45 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 200712 kb
Host smart-bc0bb99f-14fa-4962-ae2c-912d14c47ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388127314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3388127314
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1457502028
Short name T365
Test name
Test status
Simulation time 355546440 ps
CPU time 0.85 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:42:05 PM PST 23
Peak memory 200136 kb
Host smart-52dd6ee1-e032-4187-989c-5f24949eda07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457502028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1457502028
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.371118304
Short name T360
Test name
Test status
Simulation time 493400061 ps
CPU time 0.85 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:13 PM PST 23
Peak memory 200268 kb
Host smart-3ffb1a5c-400f-4eca-9cb9-95a9ce8a6371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371118304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.371118304
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2871359977
Short name T76
Test name
Test status
Simulation time 544855911 ps
CPU time 0.93 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:49 PM PST 23
Peak memory 200444 kb
Host smart-67867546-c047-4521-8772-a86aa937acb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871359977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2871359977
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2519254200
Short name T62
Test name
Test status
Simulation time 630584302 ps
CPU time 0.68 seconds
Started Dec 27 12:41:16 PM PST 23
Finished Dec 27 12:42:20 PM PST 23
Peak memory 200448 kb
Host smart-69d8ec65-6441-41b6-a006-9bf25268eb9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519254200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2519254200
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1671163288
Short name T63
Test name
Test status
Simulation time 500233978 ps
CPU time 0.86 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200176 kb
Host smart-47518904-f90e-416b-b04c-06e1ebfcc1ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671163288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1671163288
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1911926148
Short name T912
Test name
Test status
Simulation time 530536194 ps
CPU time 1.03 seconds
Started Dec 27 12:41:05 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 200120 kb
Host smart-4e2e40ae-b082-44eb-b881-8f12d36ad4cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911926148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1911926148
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3528981205
Short name T64
Test name
Test status
Simulation time 398878356 ps
CPU time 1.4 seconds
Started Dec 27 12:40:54 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 200176 kb
Host smart-4b4935cc-4812-4cb1-96be-ae0fca5f0f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528981205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3528981205
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2121311404
Short name T380
Test name
Test status
Simulation time 513683587 ps
CPU time 0.9 seconds
Started Dec 27 12:41:28 PM PST 23
Finished Dec 27 12:42:31 PM PST 23
Peak memory 200384 kb
Host smart-6971b1d3-4659-4ed9-972d-cc36c33c882e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121311404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2121311404
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2518931635
Short name T389
Test name
Test status
Simulation time 339158037 ps
CPU time 1.01 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:07 PM PST 23
Peak memory 200164 kb
Host smart-143909ab-da9c-42d2-bec4-566bb70e3cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518931635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2518931635
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4058555399
Short name T356
Test name
Test status
Simulation time 489407934 ps
CPU time 0.88 seconds
Started Dec 27 12:41:08 PM PST 23
Finished Dec 27 12:42:13 PM PST 23
Peak memory 200180 kb
Host smart-e1b3b54b-b268-444b-aa68-8d9d9dd62b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058555399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4058555399
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.598981713
Short name T31
Test name
Test status
Simulation time 549256502 ps
CPU time 1.98 seconds
Started Dec 27 12:40:52 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200620 kb
Host smart-805febe0-8ac3-4d33-91a0-849ddb44e319
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598981713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.598981713
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4028387408
Short name T362
Test name
Test status
Simulation time 25358638377 ps
CPU time 43.7 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 200812 kb
Host smart-05df04b2-0a68-41a7-8490-879225df7fd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028387408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4028387408
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2516437258
Short name T28
Test name
Test status
Simulation time 1254541995 ps
CPU time 1.37 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200492 kb
Host smart-98b8704d-1a3a-463b-9d7d-5032dc4abcbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516437258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2516437258
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1280302413
Short name T874
Test name
Test status
Simulation time 435590670 ps
CPU time 0.93 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200552 kb
Host smart-780203fb-2e5e-4fbe-b7d2-f1350fc01871
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280302413 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1280302413
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.533766045
Short name T871
Test name
Test status
Simulation time 536442506 ps
CPU time 0.82 seconds
Started Dec 27 12:40:30 PM PST 23
Finished Dec 27 12:41:28 PM PST 23
Peak memory 200484 kb
Host smart-a320cf1c-ae66-441d-96fd-987c831538d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533766045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.533766045
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3483490943
Short name T407
Test name
Test status
Simulation time 466832362 ps
CPU time 1.11 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200176 kb
Host smart-54fde247-8b1b-4539-8258-8a8fe59114d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483490943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3483490943
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2474683933
Short name T403
Test name
Test status
Simulation time 4345446994 ps
CPU time 10.06 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 200740 kb
Host smart-3b52109b-f622-4034-a395-48ce6fec5c06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474683933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2474683933
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2425611771
Short name T78
Test name
Test status
Simulation time 793995415 ps
CPU time 1.74 seconds
Started Dec 27 12:40:26 PM PST 23
Finished Dec 27 12:41:23 PM PST 23
Peak memory 200736 kb
Host smart-d3fc7483-7b83-433d-82df-79a30a6bc252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425611771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2425611771
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1311936711
Short name T347
Test name
Test status
Simulation time 8365555016 ps
CPU time 20.94 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:42:09 PM PST 23
Peak memory 200752 kb
Host smart-ee479d7a-9e2e-4207-be6c-1aa253f81e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311936711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1311936711
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3155951287
Short name T370
Test name
Test status
Simulation time 328858069 ps
CPU time 0.99 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 200140 kb
Host smart-cd1def3d-4702-4bee-a5b8-bdd82af0cb16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155951287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3155951287
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.597327771
Short name T898
Test name
Test status
Simulation time 555183816 ps
CPU time 0.89 seconds
Started Dec 27 12:40:57 PM PST 23
Finished Dec 27 12:42:02 PM PST 23
Peak memory 200228 kb
Host smart-0fe2e0f1-450a-417a-b136-9f0597cdc6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597327771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.597327771
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.125040112
Short name T885
Test name
Test status
Simulation time 429689280 ps
CPU time 1.66 seconds
Started Dec 27 12:40:59 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 200124 kb
Host smart-41af1b05-e9c4-4286-8a9d-4c85be9805cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125040112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.125040112
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.52678532
Short name T886
Test name
Test status
Simulation time 426849465 ps
CPU time 0.84 seconds
Started Dec 27 12:40:49 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200188 kb
Host smart-55ff428d-9ada-4761-975e-175d85496b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52678532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.52678532
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.878085738
Short name T364
Test name
Test status
Simulation time 339484218 ps
CPU time 0.81 seconds
Started Dec 27 12:40:55 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 200172 kb
Host smart-0254f216-fd0c-4b51-8f19-522714518a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878085738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.878085738
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1905031244
Short name T402
Test name
Test status
Simulation time 309614559 ps
CPU time 0.96 seconds
Started Dec 27 12:40:51 PM PST 23
Finished Dec 27 12:41:56 PM PST 23
Peak memory 200168 kb
Host smart-5714f021-ccfb-408c-94b2-04a59d2866e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905031244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1905031244
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.271342477
Short name T875
Test name
Test status
Simulation time 322987688 ps
CPU time 1.21 seconds
Started Dec 27 12:41:09 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 200164 kb
Host smart-7d0d93c1-6cce-49b1-87bf-20ec4f502858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271342477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.271342477
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.14476622
Short name T894
Test name
Test status
Simulation time 515405087 ps
CPU time 1.73 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:42:06 PM PST 23
Peak memory 200452 kb
Host smart-bee4441f-d48d-4374-9d07-5fca44803539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.14476622
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2555800211
Short name T5
Test name
Test status
Simulation time 525177506 ps
CPU time 1.16 seconds
Started Dec 27 12:40:49 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200468 kb
Host smart-da516968-c25e-4d6e-92ed-250034009f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555800211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2555800211
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4279142519
Short name T408
Test name
Test status
Simulation time 500604829 ps
CPU time 0.87 seconds
Started Dec 27 12:41:01 PM PST 23
Finished Dec 27 12:42:06 PM PST 23
Peak memory 200376 kb
Host smart-a0d87711-be24-4f43-b13a-367dc94f9c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279142519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4279142519
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2634884256
Short name T896
Test name
Test status
Simulation time 517939386 ps
CPU time 1.98 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200596 kb
Host smart-3f850d21-0db6-41b4-b6fa-0f6a7d00e87c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634884256 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2634884256
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2736775114
Short name T87
Test name
Test status
Simulation time 498541259 ps
CPU time 1.28 seconds
Started Dec 27 12:41:03 PM PST 23
Finished Dec 27 12:42:08 PM PST 23
Peak memory 200452 kb
Host smart-71d9cf0b-0728-4981-90a8-61a6071f9a94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736775114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2736775114
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1983323694
Short name T26
Test name
Test status
Simulation time 520180898 ps
CPU time 0.76 seconds
Started Dec 27 12:40:46 PM PST 23
Finished Dec 27 12:41:48 PM PST 23
Peak memory 200152 kb
Host smart-44c6cd8d-7ece-4ac3-88c2-a48de022b2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983323694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1983323694
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2195022230
Short name T397
Test name
Test status
Simulation time 2690325746 ps
CPU time 3.03 seconds
Started Dec 27 12:40:31 PM PST 23
Finished Dec 27 12:41:30 PM PST 23
Peak memory 200684 kb
Host smart-814660a3-e034-4084-8ea1-bd3d22b76c60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195022230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2195022230
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3765046065
Short name T883
Test name
Test status
Simulation time 454093742 ps
CPU time 1.21 seconds
Started Dec 27 12:40:36 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 200604 kb
Host smart-cda4cee0-16c6-4089-8c4f-1edd354e8581
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765046065 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3765046065
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4033763097
Short name T357
Test name
Test status
Simulation time 417282202 ps
CPU time 1.85 seconds
Started Dec 27 12:40:34 PM PST 23
Finished Dec 27 12:41:34 PM PST 23
Peak memory 200440 kb
Host smart-23a51eaf-e107-4658-85a8-d47fd9db6eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033763097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4033763097
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.108336434
Short name T79
Test name
Test status
Simulation time 418409862 ps
CPU time 1.05 seconds
Started Dec 27 12:41:12 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 200448 kb
Host smart-32fb231c-0918-42d5-b17d-943825249425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108336434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.108336434
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1700877182
Short name T73
Test name
Test status
Simulation time 5044303041 ps
CPU time 3.56 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:54 PM PST 23
Peak memory 200688 kb
Host smart-cd2d1a88-cee2-48b3-a235-6464c7d28052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700877182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1700877182
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.478890711
Short name T61
Test name
Test status
Simulation time 1103493056 ps
CPU time 2.36 seconds
Started Dec 27 12:40:29 PM PST 23
Finished Dec 27 12:41:31 PM PST 23
Peak memory 200752 kb
Host smart-0623474c-694f-48ed-8701-bd7d60dab06c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478890711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.478890711
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3198276052
Short name T36
Test name
Test status
Simulation time 4681279035 ps
CPU time 4.06 seconds
Started Dec 27 12:40:38 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200696 kb
Host smart-803df3a3-53bb-4b85-bc97-ae029ca9f346
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198276052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3198276052
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.795449340
Short name T398
Test name
Test status
Simulation time 394919519 ps
CPU time 1.61 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:38 PM PST 23
Peak memory 200556 kb
Host smart-e8673845-4e50-4064-b5bc-55ccb8190ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795449340 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.795449340
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1649945998
Short name T80
Test name
Test status
Simulation time 408728324 ps
CPU time 1.21 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:25 PM PST 23
Peak memory 200452 kb
Host smart-9e494816-d0c2-4188-8e09-29db4cae72f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649945998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1649945998
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3405836060
Short name T372
Test name
Test status
Simulation time 327517563 ps
CPU time 1.31 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200340 kb
Host smart-ddd90f01-3259-4ec4-92f8-e09bd6d22925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405836060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3405836060
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3163685678
Short name T10
Test name
Test status
Simulation time 2412723083 ps
CPU time 2.01 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 200548 kb
Host smart-764b0dd8-2466-4e7e-ab39-157594382180
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163685678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3163685678
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4103580467
Short name T399
Test name
Test status
Simulation time 562955468 ps
CPU time 3.35 seconds
Started Dec 27 12:40:28 PM PST 23
Finished Dec 27 12:41:33 PM PST 23
Peak memory 200712 kb
Host smart-74e9a0f8-00ac-435c-afbb-cf14bbdf5046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103580467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4103580467
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.562879187
Short name T880
Test name
Test status
Simulation time 4273784017 ps
CPU time 6.18 seconds
Started Dec 27 12:40:34 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200772 kb
Host smart-40dd2962-dd18-4bb7-a35c-e63abbb7e420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562879187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.562879187
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.56964521
Short name T391
Test name
Test status
Simulation time 489428122 ps
CPU time 1.87 seconds
Started Dec 27 12:41:00 PM PST 23
Finished Dec 27 12:42:06 PM PST 23
Peak memory 200556 kb
Host smart-4feb5be0-caa9-4eb7-bf57-6506f32ba449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56964521 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.56964521
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2560767111
Short name T374
Test name
Test status
Simulation time 559491285 ps
CPU time 0.85 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:37 PM PST 23
Peak memory 200488 kb
Host smart-c206553d-7da8-4b09-8db1-5abf9a837b88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560767111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2560767111
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4242457649
Short name T873
Test name
Test status
Simulation time 449260975 ps
CPU time 0.66 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:42 PM PST 23
Peak memory 200244 kb
Host smart-c5a6f8c9-2e1b-4465-8c12-9f9ebce2fd49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242457649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4242457649
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3362405119
Short name T1
Test name
Test status
Simulation time 4672034252 ps
CPU time 3.55 seconds
Started Dec 27 12:41:02 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 200808 kb
Host smart-21d58488-ca29-40f2-8763-2ff8bdb2bd65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362405119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3362405119
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.4037776747
Short name T58
Test name
Test status
Simulation time 489096493 ps
CPU time 2.7 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200768 kb
Host smart-251e8bd2-e0e4-47a9-8fc3-576a721becf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037776747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.4037776747
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1090261037
Short name T383
Test name
Test status
Simulation time 4414756155 ps
CPU time 10.3 seconds
Started Dec 27 12:40:40 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 200792 kb
Host smart-cdb9e19b-71f9-454a-8890-efb27b9f7850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090261037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1090261037
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.476729147
Short name T368
Test name
Test status
Simulation time 352624627 ps
CPU time 1.45 seconds
Started Dec 27 12:40:29 PM PST 23
Finished Dec 27 12:41:27 PM PST 23
Peak memory 200588 kb
Host smart-2830b2e5-6854-41ae-a4e7-bcc352749e40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476729147 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.476729147
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.507206358
Short name T82
Test name
Test status
Simulation time 388375222 ps
CPU time 0.88 seconds
Started Dec 27 12:40:42 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200432 kb
Host smart-374b9d51-2bec-4589-97c8-a28b156e2bfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507206358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.507206358
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1446966575
Short name T384
Test name
Test status
Simulation time 479481266 ps
CPU time 1.8 seconds
Started Dec 27 12:40:41 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 200456 kb
Host smart-62f54eec-39dd-43cc-8a53-52b51f25e3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446966575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1446966575
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.483824243
Short name T914
Test name
Test status
Simulation time 2237036204 ps
CPU time 2.96 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200556 kb
Host smart-837f921d-c680-4130-a996-1bc6808f1116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483824243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.483824243
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2233725835
Short name T57
Test name
Test status
Simulation time 599092705 ps
CPU time 2.53 seconds
Started Dec 27 12:40:37 PM PST 23
Finished Dec 27 12:41:39 PM PST 23
Peak memory 200800 kb
Host smart-f539b853-0e2b-41a8-b06a-80876e9701fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233725835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2233725835
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4204705350
Short name T69
Test name
Test status
Simulation time 4583898852 ps
CPU time 10.97 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 12:42:10 PM PST 23
Peak memory 200820 kb
Host smart-e13edb6a-eb5f-4e1d-bcac-ca110ea56bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204705350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4204705350
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2315261110
Short name T651
Test name
Test status
Simulation time 422030898 ps
CPU time 0.69 seconds
Started Dec 27 12:37:00 PM PST 23
Finished Dec 27 12:37:26 PM PST 23
Peak memory 200504 kb
Host smart-29310042-7ba0-4fcd-abe8-b0f4c96315b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315261110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2315261110
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2250343256
Short name T844
Test name
Test status
Simulation time 494350242238 ps
CPU time 301.19 seconds
Started Dec 27 12:36:33 PM PST 23
Finished Dec 27 12:42:01 PM PST 23
Peak memory 200820 kb
Host smart-e6a91725-3a1e-4f12-b4fb-a2d23da9700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250343256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2250343256
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2511653306
Short name T123
Test name
Test status
Simulation time 496029100787 ps
CPU time 1119.09 seconds
Started Dec 27 12:37:07 PM PST 23
Finished Dec 27 12:56:10 PM PST 23
Peak memory 200744 kb
Host smart-36c41d1d-1da5-4a04-bb15-a4340740a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511653306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2511653306
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.797023237
Short name T512
Test name
Test status
Simulation time 162335786473 ps
CPU time 211.1 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:40:49 PM PST 23
Peak memory 200712 kb
Host smart-892e18aa-d5ba-460d-b08d-2bdf466325c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=797023237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.797023237
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.453689729
Short name T691
Test name
Test status
Simulation time 164631420471 ps
CPU time 79.39 seconds
Started Dec 27 12:36:50 PM PST 23
Finished Dec 27 12:38:37 PM PST 23
Peak memory 200760 kb
Host smart-06d81ecd-77d7-4a29-9091-09c761fc986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453689729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.453689729
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.194603526
Short name T439
Test name
Test status
Simulation time 334747453004 ps
CPU time 430.18 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:44:45 PM PST 23
Peak memory 200804 kb
Host smart-a60082cc-d97d-42b9-a57e-3ae68e2f1832
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=194603526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.194603526
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4015412074
Short name T736
Test name
Test status
Simulation time 334493465221 ps
CPU time 391.22 seconds
Started Dec 27 12:36:50 PM PST 23
Finished Dec 27 12:43:49 PM PST 23
Peak memory 200796 kb
Host smart-f1bcfc8a-3f8c-4f99-89d1-8b7e6b8e1ef8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015412074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4015412074
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3974981428
Short name T467
Test name
Test status
Simulation time 167749784911 ps
CPU time 192.4 seconds
Started Dec 27 12:37:11 PM PST 23
Finished Dec 27 12:40:46 PM PST 23
Peak memory 200708 kb
Host smart-0f8e12a5-b3de-4437-82c6-23042c26af3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974981428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3974981428
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2972770702
Short name T867
Test name
Test status
Simulation time 99457368082 ps
CPU time 393.14 seconds
Started Dec 27 12:39:12 PM PST 23
Finished Dec 27 12:46:09 PM PST 23
Peak memory 201104 kb
Host smart-9a0a2a61-05b5-4377-a047-afd348e78be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972770702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2972770702
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.4064123820
Short name T496
Test name
Test status
Simulation time 47321349372 ps
CPU time 111.98 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:39:13 PM PST 23
Peak memory 200600 kb
Host smart-cae744fa-63d4-4610-a928-75c6543423c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064123820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.4064123820
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.239634941
Short name T576
Test name
Test status
Simulation time 4445540925 ps
CPU time 10.57 seconds
Started Dec 27 12:36:50 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 200660 kb
Host smart-a0e7dd4b-16d5-4443-9c73-8f5a73f88199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239634941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.239634941
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3754499000
Short name T42
Test name
Test status
Simulation time 4521312403 ps
CPU time 8.49 seconds
Started Dec 27 12:36:42 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 215892 kb
Host smart-db3bf7ad-a7a0-4c30-be40-0cd205884c01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754499000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3754499000
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1791869278
Short name T487
Test name
Test status
Simulation time 5815250877 ps
CPU time 4.18 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:30 PM PST 23
Peak memory 200524 kb
Host smart-c9a3bc9f-79d4-408b-bd32-49ead8ee1d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791869278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1791869278
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2911122395
Short name T664
Test name
Test status
Simulation time 59848279766 ps
CPU time 41.03 seconds
Started Dec 27 12:36:37 PM PST 23
Finished Dec 27 12:37:47 PM PST 23
Peak memory 209148 kb
Host smart-378d9dbe-6aac-4a7c-875b-43687e28a3dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911122395 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2911122395
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1923734409
Short name T767
Test name
Test status
Simulation time 541990433 ps
CPU time 0.92 seconds
Started Dec 27 12:36:43 PM PST 23
Finished Dec 27 12:37:13 PM PST 23
Peak memory 200568 kb
Host smart-afe48250-87bf-4d4f-8f81-2d9c09fa59ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923734409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1923734409
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3282209784
Short name T711
Test name
Test status
Simulation time 321283718612 ps
CPU time 110.5 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:40:11 PM PST 23
Peak memory 200788 kb
Host smart-2e6ca310-01d3-45fb-91a2-2d35209e361c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282209784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3282209784
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.42224065
Short name T344
Test name
Test status
Simulation time 488295569611 ps
CPU time 557.11 seconds
Started Dec 27 12:37:00 PM PST 23
Finished Dec 27 12:46:42 PM PST 23
Peak memory 200824 kb
Host smart-2d435830-9076-4a3a-9dce-3c638106f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42224065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.42224065
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3355151006
Short name T251
Test name
Test status
Simulation time 328345771444 ps
CPU time 511.88 seconds
Started Dec 27 12:36:52 PM PST 23
Finished Dec 27 12:45:50 PM PST 23
Peak memory 200820 kb
Host smart-7967b033-e3ab-47e3-a451-0c347c64e771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355151006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3355151006
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3001288924
Short name T141
Test name
Test status
Simulation time 501235628565 ps
CPU time 268.59 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:42:04 PM PST 23
Peak memory 200672 kb
Host smart-ae2ea770-b237-4c98-b289-6d9948431c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001288924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3001288924
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1852478053
Short name T589
Test name
Test status
Simulation time 495428569806 ps
CPU time 1224.83 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 200756 kb
Host smart-02219e91-dab4-4167-b6b5-30b16260ca2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852478053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1852478053
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.4212529056
Short name T741
Test name
Test status
Simulation time 328038774841 ps
CPU time 486.14 seconds
Started Dec 27 12:37:21 PM PST 23
Finished Dec 27 12:45:46 PM PST 23
Peak memory 200768 kb
Host smart-4c0c817d-9d50-410a-87fd-ea0694f0e4ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212529056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.4212529056
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3028276743
Short name T674
Test name
Test status
Simulation time 335997177324 ps
CPU time 197.08 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:40:55 PM PST 23
Peak memory 200684 kb
Host smart-0b402110-f1e6-40bf-8d1a-3afb6dd05905
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028276743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3028276743
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1588545510
Short name T566
Test name
Test status
Simulation time 81198918100 ps
CPU time 300.14 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:42:27 PM PST 23
Peak memory 201100 kb
Host smart-57688bfe-aebc-4db7-91b8-fa595525ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588545510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1588545510
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.783284495
Short name T556
Test name
Test status
Simulation time 29379481065 ps
CPU time 68.28 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:38:57 PM PST 23
Peak memory 200612 kb
Host smart-50650b95-f781-421b-9e94-87ab319c5cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783284495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.783284495
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.4059011665
Short name T559
Test name
Test status
Simulation time 3596871482 ps
CPU time 9.2 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 200680 kb
Host smart-5448b452-54f2-4f7c-8fd1-5bc7de6a3ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059011665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.4059011665
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3453911373
Short name T491
Test name
Test status
Simulation time 5552454575 ps
CPU time 5.28 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:37:35 PM PST 23
Peak memory 200620 kb
Host smart-c311d700-e19b-430a-923a-ae7eb725b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453911373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3453911373
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4049112217
Short name T545
Test name
Test status
Simulation time 6675635955 ps
CPU time 4.87 seconds
Started Dec 27 12:37:10 PM PST 23
Finished Dec 27 12:37:37 PM PST 23
Peak memory 200620 kb
Host smart-2197a2ea-da65-4e46-ac8e-8fd47b0b1461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049112217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4049112217
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3916909076
Short name T302
Test name
Test status
Simulation time 329470629244 ps
CPU time 530.66 seconds
Started Dec 27 12:37:46 PM PST 23
Finished Dec 27 12:46:43 PM PST 23
Peak memory 200812 kb
Host smart-41afcda4-1552-41a7-a1f0-a99436390c62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916909076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3916909076
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2892792375
Short name T308
Test name
Test status
Simulation time 489418385654 ps
CPU time 326.54 seconds
Started Dec 27 12:37:28 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 200860 kb
Host smart-eb2a5f5e-483d-443e-99cd-bfb7a69a6258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892792375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2892792375
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.4078590726
Short name T784
Test name
Test status
Simulation time 492214989438 ps
CPU time 1127.33 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:56:35 PM PST 23
Peak memory 200788 kb
Host smart-9e5bee20-eec7-4a85-b93c-b8fe615cb25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078590726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.4078590726
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2291704004
Short name T557
Test name
Test status
Simulation time 165767621867 ps
CPU time 188.79 seconds
Started Dec 27 12:37:10 PM PST 23
Finished Dec 27 12:40:41 PM PST 23
Peak memory 200812 kb
Host smart-4d59ac92-07d9-4764-8e2e-046e335ca27a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291704004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2291704004
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.357559998
Short name T788
Test name
Test status
Simulation time 325428991013 ps
CPU time 732.34 seconds
Started Dec 27 12:37:46 PM PST 23
Finished Dec 27 12:50:04 PM PST 23
Peak memory 200752 kb
Host smart-8fa41ed9-de4b-4282-829b-f01dc1e39afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357559998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.357559998
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3573176791
Short name T421
Test name
Test status
Simulation time 162226881537 ps
CPU time 258.19 seconds
Started Dec 27 12:39:02 PM PST 23
Finished Dec 27 12:43:36 PM PST 23
Peak memory 200712 kb
Host smart-797b24a4-d961-4321-8753-c8c5b80e5c1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573176791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3573176791
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3727842476
Short name T286
Test name
Test status
Simulation time 503211984336 ps
CPU time 300.39 seconds
Started Dec 27 12:37:25 PM PST 23
Finished Dec 27 12:42:42 PM PST 23
Peak memory 200684 kb
Host smart-acccbfad-ee30-4b42-8e12-a4b842e32ed7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727842476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3727842476
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2297641513
Short name T465
Test name
Test status
Simulation time 330589242413 ps
CPU time 152.62 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:40:21 PM PST 23
Peak memory 200736 kb
Host smart-40b5ae3a-0ec7-486e-94dd-692f5d5ab0e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297641513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2297641513
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.22574600
Short name T835
Test name
Test status
Simulation time 115888444596 ps
CPU time 684.59 seconds
Started Dec 27 12:37:16 PM PST 23
Finished Dec 27 12:49:01 PM PST 23
Peak memory 201148 kb
Host smart-44e0c4c4-faae-455d-a843-f983270fa76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22574600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.22574600
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1682829042
Short name T416
Test name
Test status
Simulation time 42086083829 ps
CPU time 98.91 seconds
Started Dec 27 12:37:39 PM PST 23
Finished Dec 27 12:39:29 PM PST 23
Peak memory 200612 kb
Host smart-ecc60190-bf0b-4492-a265-33040582db56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682829042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1682829042
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3909989324
Short name T685
Test name
Test status
Simulation time 5280377237 ps
CPU time 13.27 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:37:49 PM PST 23
Peak memory 200664 kb
Host smart-1cee1b72-2221-4988-9c9f-abcb9ebe52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909989324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3909989324
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3094309650
Short name T435
Test name
Test status
Simulation time 5788590014 ps
CPU time 4.2 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:27 PM PST 23
Peak memory 200260 kb
Host smart-d7bb7266-9cc8-4a07-b3d2-c6b02faaeef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094309650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3094309650
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.391932093
Short name T173
Test name
Test status
Simulation time 125768300573 ps
CPU time 722.64 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:50:34 PM PST 23
Peak memory 217320 kb
Host smart-59e56c47-3e65-48f3-bcb5-c8297611a127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391932093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
391932093
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3179663803
Short name T346
Test name
Test status
Simulation time 159964011950 ps
CPU time 132.8 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:40:18 PM PST 23
Peak memory 209148 kb
Host smart-63e34123-b65e-421e-841d-8599f55e6e7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179663803 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3179663803
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3530883873
Short name T864
Test name
Test status
Simulation time 570642218 ps
CPU time 0.74 seconds
Started Dec 27 12:39:20 PM PST 23
Finished Dec 27 12:39:48 PM PST 23
Peak memory 200556 kb
Host smart-a940c244-574d-4af5-a135-c6e31f35e783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530883873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3530883873
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3444335062
Short name T837
Test name
Test status
Simulation time 319594497823 ps
CPU time 59.36 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:38:53 PM PST 23
Peak memory 200772 kb
Host smart-119a96b2-ce88-455c-bea7-0a78136841a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444335062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3444335062
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.385503066
Short name T129
Test name
Test status
Simulation time 165217613054 ps
CPU time 213.51 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:41:30 PM PST 23
Peak memory 200676 kb
Host smart-fa6b0e3b-7f47-4594-9863-abb1f1fb42c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=385503066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.385503066
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.667415503
Short name T680
Test name
Test status
Simulation time 490959818321 ps
CPU time 550.87 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 200796 kb
Host smart-55964952-f797-4f14-a3da-df5d76fa6125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667415503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.667415503
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.716134393
Short name T561
Test name
Test status
Simulation time 328286358876 ps
CPU time 711.52 seconds
Started Dec 27 12:37:26 PM PST 23
Finished Dec 27 12:49:34 PM PST 23
Peak memory 200752 kb
Host smart-1d4b767c-0907-4989-bbc6-27f8a0645057
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=716134393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.716134393
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2744089076
Short name T105
Test name
Test status
Simulation time 514600368364 ps
CPU time 283.46 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:42:53 PM PST 23
Peak memory 200732 kb
Host smart-7066436c-ecfa-4477-84ce-d2b29cf32d61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744089076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2744089076
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3231150456
Short name T705
Test name
Test status
Simulation time 327215786763 ps
CPU time 375.75 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:44:35 PM PST 23
Peak memory 200760 kb
Host smart-90020d89-d7cf-4385-a144-174f9156bc71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231150456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3231150456
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1355228189
Short name T508
Test name
Test status
Simulation time 126837591073 ps
CPU time 472.69 seconds
Started Dec 27 12:37:30 PM PST 23
Finished Dec 27 12:45:37 PM PST 23
Peak memory 201116 kb
Host smart-1ddd4021-e994-4972-b857-35bf6b192296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355228189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1355228189
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.988987890
Short name T697
Test name
Test status
Simulation time 29046263765 ps
CPU time 8.93 seconds
Started Dec 27 12:38:00 PM PST 23
Finished Dec 27 12:38:18 PM PST 23
Peak memory 200588 kb
Host smart-87a4399c-d732-4188-82d4-b7145d045d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988987890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.988987890
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2653000292
Short name T729
Test name
Test status
Simulation time 3615940768 ps
CPU time 1.32 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:37:47 PM PST 23
Peak memory 200572 kb
Host smart-4cb59e74-0046-4e7b-9c00-6da3e91ee775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653000292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2653000292
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2862002083
Short name T820
Test name
Test status
Simulation time 5980361439 ps
CPU time 14.65 seconds
Started Dec 27 12:37:26 PM PST 23
Finished Dec 27 12:38:00 PM PST 23
Peak memory 200524 kb
Host smart-df650028-1c06-46bf-956d-2025b7552114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862002083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2862002083
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.112588581
Short name T825
Test name
Test status
Simulation time 239739489204 ps
CPU time 256.18 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:42:26 PM PST 23
Peak memory 215996 kb
Host smart-a54c0c61-d591-47f9-beb8-13846be13834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112588581 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.112588581
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1504293699
Short name T434
Test name
Test status
Simulation time 285864564 ps
CPU time 1.28 seconds
Started Dec 27 12:37:45 PM PST 23
Finished Dec 27 12:37:53 PM PST 23
Peak memory 200452 kb
Host smart-e7988446-66ac-489b-86f5-72024f3c5e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504293699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1504293699
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3241874239
Short name T629
Test name
Test status
Simulation time 162854038806 ps
CPU time 81.24 seconds
Started Dec 27 12:38:22 PM PST 23
Finished Dec 27 12:39:51 PM PST 23
Peak memory 200820 kb
Host smart-282fa151-7c17-4f46-b024-ff7dfdccb314
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241874239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3241874239
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3312697339
Short name T249
Test name
Test status
Simulation time 163868288714 ps
CPU time 337.84 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:43:50 PM PST 23
Peak memory 200636 kb
Host smart-e1443ad2-77f1-4786-9f28-95e91411e729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312697339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3312697339
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1695164834
Short name T699
Test name
Test status
Simulation time 162469071527 ps
CPU time 96.23 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:39:30 PM PST 23
Peak memory 200780 kb
Host smart-3fe5eb9c-3129-4c19-8e85-79f5f0a8b0fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695164834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1695164834
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2744501115
Short name T553
Test name
Test status
Simulation time 160037428588 ps
CPU time 71.9 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:39:33 PM PST 23
Peak memory 200864 kb
Host smart-6c2ae54f-cd0b-40fb-a45d-7da3b5a52c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744501115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2744501115
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.663957341
Short name T738
Test name
Test status
Simulation time 324700978316 ps
CPU time 372.47 seconds
Started Dec 27 12:37:48 PM PST 23
Finished Dec 27 12:44:06 PM PST 23
Peak memory 200752 kb
Host smart-c5cc142c-15fd-4d2c-b7e7-63d68ba08e69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=663957341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.663957341
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3567584073
Short name T715
Test name
Test status
Simulation time 80743134615 ps
CPU time 336.57 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:43:22 PM PST 23
Peak memory 201244 kb
Host smart-5edb096e-14de-4f56-a081-f57ceb3365a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567584073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3567584073
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2611722114
Short name T541
Test name
Test status
Simulation time 34465931136 ps
CPU time 87.8 seconds
Started Dec 27 12:37:34 PM PST 23
Finished Dec 27 12:39:15 PM PST 23
Peak memory 200580 kb
Host smart-458b1f15-db5e-4391-a79d-e355fc07168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611722114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2611722114
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3350676290
Short name T441
Test name
Test status
Simulation time 5067855255 ps
CPU time 11.85 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:38:24 PM PST 23
Peak memory 200616 kb
Host smart-65a6811f-2478-4b09-921f-dcd328fd54d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350676290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3350676290
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1089486881
Short name T696
Test name
Test status
Simulation time 5884395343 ps
CPU time 3.69 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:37:52 PM PST 23
Peak memory 200564 kb
Host smart-55bf4965-6402-4521-a805-560b3e90fd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089486881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1089486881
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.568624352
Short name T700
Test name
Test status
Simulation time 331034394734 ps
CPU time 186.17 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:41:38 PM PST 23
Peak memory 200784 kb
Host smart-aaadbd5d-5548-4e45-a26b-2515c1d8b9bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568624352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
568624352
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3898179013
Short name T140
Test name
Test status
Simulation time 60729650297 ps
CPU time 141.96 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:40:54 PM PST 23
Peak memory 209552 kb
Host smart-ee75e273-105d-4d69-9fb9-723828401f81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898179013 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3898179013
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3058867016
Short name T786
Test name
Test status
Simulation time 436914223 ps
CPU time 1.59 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:38:06 PM PST 23
Peak memory 200600 kb
Host smart-007e82cc-6a10-40d6-af38-583badebb72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058867016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3058867016
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.781384740
Short name T670
Test name
Test status
Simulation time 169476651348 ps
CPU time 250.5 seconds
Started Dec 27 12:37:55 PM PST 23
Finished Dec 27 12:42:12 PM PST 23
Peak memory 200788 kb
Host smart-835e9bc4-6b41-4eb8-a2d0-d81639bce71a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781384740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.781384740
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1198608845
Short name T275
Test name
Test status
Simulation time 488289485474 ps
CPU time 267 seconds
Started Dec 27 12:40:00 PM PST 23
Finished Dec 27 12:45:16 PM PST 23
Peak memory 200544 kb
Host smart-b5094112-9f89-4f4d-9c99-c9272ef5731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198608845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1198608845
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2658676396
Short name T409
Test name
Test status
Simulation time 161520389917 ps
CPU time 380.01 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:45:29 PM PST 23
Peak memory 200796 kb
Host smart-1de707c8-680e-47a9-94d5-f68607128d6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658676396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2658676396
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3957002823
Short name T861
Test name
Test status
Simulation time 325758874573 ps
CPU time 353.79 seconds
Started Dec 27 12:37:26 PM PST 23
Finished Dec 27 12:43:36 PM PST 23
Peak memory 200768 kb
Host smart-00c287e8-08c7-4940-a9cb-79cb13127e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957002823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3957002823
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3118742929
Short name T137
Test name
Test status
Simulation time 160009915369 ps
CPU time 160.19 seconds
Started Dec 27 12:37:42 PM PST 23
Finished Dec 27 12:40:31 PM PST 23
Peak memory 200752 kb
Host smart-b4f3f2d9-769e-4fee-a9bf-696d4bb4eac0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118742929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3118742929
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.396324269
Short name T731
Test name
Test status
Simulation time 164170455401 ps
CPU time 102.22 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:39:54 PM PST 23
Peak memory 200144 kb
Host smart-dfeb4f56-7cbe-438d-b87d-18ee7a9c38d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396324269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.396324269
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.725096962
Short name T733
Test name
Test status
Simulation time 170134915730 ps
CPU time 207.36 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:41:58 PM PST 23
Peak memory 200684 kb
Host smart-2567c4cb-c7ef-467d-8224-a4cd0e132f53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725096962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.725096962
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2114285557
Short name T172
Test name
Test status
Simulation time 86916361642 ps
CPU time 452.85 seconds
Started Dec 27 12:38:19 PM PST 23
Finished Dec 27 12:46:00 PM PST 23
Peak memory 201296 kb
Host smart-c1f32d06-b9f8-4798-80a1-fa3c7bd0a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114285557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2114285557
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3383006087
Short name T447
Test name
Test status
Simulation time 40358509373 ps
CPU time 25.34 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:38:42 PM PST 23
Peak memory 200652 kb
Host smart-318fc804-bc12-498d-9ecc-073219f2f5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383006087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3383006087
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2709411942
Short name T455
Test name
Test status
Simulation time 5288041699 ps
CPU time 2.01 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:37:59 PM PST 23
Peak memory 200588 kb
Host smart-1a780f2f-2d7a-49c1-8e45-2d2c84f8931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709411942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2709411942
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3390214256
Short name T611
Test name
Test status
Simulation time 5953202710 ps
CPU time 5.39 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:38:26 PM PST 23
Peak memory 200556 kb
Host smart-882ed6c0-b50f-401e-aa03-3b8f9bacc380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390214256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3390214256
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1248817466
Short name T188
Test name
Test status
Simulation time 171609276116 ps
CPU time 214.48 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 200820 kb
Host smart-d0dd87d2-984f-41bc-8898-b142d4d750e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248817466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1248817466
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.453378128
Short name T39
Test name
Test status
Simulation time 410071339 ps
CPU time 1.57 seconds
Started Dec 27 12:37:27 PM PST 23
Finished Dec 27 12:37:45 PM PST 23
Peak memory 200556 kb
Host smart-61a179b6-8dd8-4882-937b-d8ae9d058a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453378128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.453378128
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3915992303
Short name T803
Test name
Test status
Simulation time 163439092017 ps
CPU time 363.08 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:43:48 PM PST 23
Peak memory 200816 kb
Host smart-d74b1880-9fe6-42c3-8e7c-33ba57fabdd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915992303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3915992303
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4274936806
Short name T237
Test name
Test status
Simulation time 499423762730 ps
CPU time 574.16 seconds
Started Dec 27 12:39:32 PM PST 23
Finished Dec 27 12:49:41 PM PST 23
Peak memory 199272 kb
Host smart-9afa91b7-97b1-4134-a86a-018e8c410518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274936806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4274936806
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1151534868
Short name T114
Test name
Test status
Simulation time 330191099743 ps
CPU time 402.4 seconds
Started Dec 27 12:37:47 PM PST 23
Finished Dec 27 12:44:35 PM PST 23
Peak memory 200740 kb
Host smart-8bdad2ac-c2cf-4860-b303-2d77162094ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151534868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1151534868
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2493442308
Short name T15
Test name
Test status
Simulation time 491750671616 ps
CPU time 355.06 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:44:00 PM PST 23
Peak memory 200712 kb
Host smart-12014d53-f9fd-4e68-8289-e3027ff8df17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493442308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2493442308
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2594810932
Short name T333
Test name
Test status
Simulation time 513097553907 ps
CPU time 1072.48 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:56:09 PM PST 23
Peak memory 200836 kb
Host smart-71d9298b-04f5-4903-b320-ad77d538ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594810932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2594810932
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.905939398
Short name T510
Test name
Test status
Simulation time 495533022925 ps
CPU time 392.9 seconds
Started Dec 27 12:40:20 PM PST 23
Finished Dec 27 12:47:47 PM PST 23
Peak memory 200484 kb
Host smart-3b2c2272-b53c-4358-a734-7d3676f0da12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=905939398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.905939398
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.4005013186
Short name T342
Test name
Test status
Simulation time 484850450216 ps
CPU time 284.69 seconds
Started Dec 27 12:37:50 PM PST 23
Finished Dec 27 12:42:39 PM PST 23
Peak memory 200800 kb
Host smart-ffe1a2e2-54df-4d86-ae53-6446b6a69e2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005013186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.4005013186
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2264596017
Short name T568
Test name
Test status
Simulation time 161551958835 ps
CPU time 90.87 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:39:41 PM PST 23
Peak memory 200700 kb
Host smart-964bd98a-249e-4d22-997f-72a22e7be19b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264596017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2264596017
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.203068230
Short name T460
Test name
Test status
Simulation time 136950933536 ps
CPU time 594.87 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:47:40 PM PST 23
Peak memory 201068 kb
Host smart-43f0a666-8b38-4850-8e23-74f354171c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203068230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.203068230
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3291629240
Short name T588
Test name
Test status
Simulation time 38250559625 ps
CPU time 84.05 seconds
Started Dec 27 12:39:21 PM PST 23
Finished Dec 27 12:41:17 PM PST 23
Peak memory 200556 kb
Host smart-c5bfc65e-26f4-4981-baac-bfaf4204cd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291629240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3291629240
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.4205547754
Short name T724
Test name
Test status
Simulation time 3860256920 ps
CPU time 9.43 seconds
Started Dec 27 12:37:41 PM PST 23
Finished Dec 27 12:38:02 PM PST 23
Peak memory 200608 kb
Host smart-7b374aa0-2a33-4a55-976b-fe6226ee9702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205547754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.4205547754
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2942110704
Short name T548
Test name
Test status
Simulation time 5995799438 ps
CPU time 1.88 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:38:08 PM PST 23
Peak memory 200632 kb
Host smart-13de7778-d750-4ad5-b154-f759d188267c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942110704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2942110704
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3439368913
Short name T762
Test name
Test status
Simulation time 197344295458 ps
CPU time 28.59 seconds
Started Dec 27 12:37:52 PM PST 23
Finished Dec 27 12:38:24 PM PST 23
Peak memory 200712 kb
Host smart-ab29bbbc-2b09-4fac-b6d8-6a7f6b15353e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439368913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3439368913
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.681730813
Short name T287
Test name
Test status
Simulation time 84566590490 ps
CPU time 285.84 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:43:54 PM PST 23
Peak memory 215736 kb
Host smart-76e0f0ea-bf60-4168-92fe-3080997a2ef5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681730813 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.681730813
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.4236306270
Short name T637
Test name
Test status
Simulation time 342606982 ps
CPU time 1 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:37:54 PM PST 23
Peak memory 200520 kb
Host smart-fe837199-a13a-4fe9-b8cd-f560e97c7891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236306270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4236306270
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3772992432
Short name T789
Test name
Test status
Simulation time 496970677772 ps
CPU time 1156.4 seconds
Started Dec 27 12:37:45 PM PST 23
Finished Dec 27 12:57:09 PM PST 23
Peak memory 200724 kb
Host smart-0bdbabf0-9c4e-487c-8b79-bf7a7beb75cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772992432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3772992432
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3515187734
Short name T203
Test name
Test status
Simulation time 331300434040 ps
CPU time 695.6 seconds
Started Dec 27 12:37:59 PM PST 23
Finished Dec 27 12:49:45 PM PST 23
Peak memory 200824 kb
Host smart-d79828d2-0a20-43ae-a8a5-c14d925ecf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515187734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3515187734
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.825188969
Short name T483
Test name
Test status
Simulation time 507971769911 ps
CPU time 1251.49 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:59:16 PM PST 23
Peak memory 200812 kb
Host smart-9074db3d-6380-4813-9bcc-a7b06487a99f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=825188969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.825188969
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3385784829
Short name T51
Test name
Test status
Simulation time 163547773213 ps
CPU time 374.88 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:44:25 PM PST 23
Peak memory 200820 kb
Host smart-47161f71-7397-47bc-8832-60236aee30e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385784829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3385784829
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.742891003
Short name T597
Test name
Test status
Simulation time 333312593344 ps
CPU time 745.26 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:50:57 PM PST 23
Peak memory 200888 kb
Host smart-18243fc3-ef4d-4d79-8f11-16083b4b3835
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=742891003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.742891003
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2639153421
Short name T149
Test name
Test status
Simulation time 320434234562 ps
CPU time 180.47 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:40:57 PM PST 23
Peak memory 200740 kb
Host smart-c0255a5e-d6a1-43ce-883c-881550248ccb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639153421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2639153421
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4285303911
Short name T476
Test name
Test status
Simulation time 335185568837 ps
CPU time 345.56 seconds
Started Dec 27 12:38:09 PM PST 23
Finished Dec 27 12:44:01 PM PST 23
Peak memory 200704 kb
Host smart-769e58b3-b73a-4fa9-89ba-29283d071c9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285303911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4285303911
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2221168957
Short name T799
Test name
Test status
Simulation time 137849340442 ps
CPU time 742.67 seconds
Started Dec 27 12:37:42 PM PST 23
Finished Dec 27 12:50:13 PM PST 23
Peak memory 201264 kb
Host smart-d86e58bc-cc39-48ea-87ee-a9cc730e11dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221168957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2221168957
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2828123051
Short name T687
Test name
Test status
Simulation time 23175918089 ps
CPU time 14.13 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:38:08 PM PST 23
Peak memory 200668 kb
Host smart-931a98c9-5418-4c6b-b5c4-e9ab89d72078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828123051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2828123051
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1099807424
Short name T490
Test name
Test status
Simulation time 2987917758 ps
CPU time 4.5 seconds
Started Dec 27 12:37:45 PM PST 23
Finished Dec 27 12:37:56 PM PST 23
Peak memory 200676 kb
Host smart-6fd1f5a2-de1c-497b-b670-841824bab2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099807424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1099807424
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1857714816
Short name T528
Test name
Test status
Simulation time 5754417515 ps
CPU time 2.69 seconds
Started Dec 27 12:37:39 PM PST 23
Finished Dec 27 12:37:53 PM PST 23
Peak memory 200684 kb
Host smart-07b47de0-f08a-4b24-b66a-5e8f2a225bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857714816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1857714816
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.926083552
Short name T630
Test name
Test status
Simulation time 383981106580 ps
CPU time 668.63 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:49:57 PM PST 23
Peak memory 200900 kb
Host smart-97c72b67-5587-45b2-88c5-8b05112e113d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926083552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
926083552
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.379832651
Short name T245
Test name
Test status
Simulation time 114780218933 ps
CPU time 67.45 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:39:15 PM PST 23
Peak memory 209088 kb
Host smart-e9784e01-0859-4043-b298-34898f812913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379832651 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.379832651
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.582049459
Short name T606
Test name
Test status
Simulation time 326334513 ps
CPU time 1.28 seconds
Started Dec 27 12:40:12 PM PST 23
Finished Dec 27 12:41:05 PM PST 23
Peak memory 200348 kb
Host smart-2ef8f189-3bb0-4d9a-8dad-a4ace993aee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582049459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.582049459
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.232327218
Short name T109
Test name
Test status
Simulation time 488937937030 ps
CPU time 301.83 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 200772 kb
Host smart-296cbe55-59aa-4e16-b8d9-b98f508a5e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232327218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.232327218
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1672518383
Short name T305
Test name
Test status
Simulation time 158984457655 ps
CPU time 102.5 seconds
Started Dec 27 12:38:09 PM PST 23
Finished Dec 27 12:39:58 PM PST 23
Peak memory 200876 kb
Host smart-41d06151-60d5-42db-bc55-6031a66fb662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672518383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1672518383
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2340435919
Short name T846
Test name
Test status
Simulation time 328819177685 ps
CPU time 145.29 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:40:36 PM PST 23
Peak memory 200740 kb
Host smart-626e43f3-4611-465a-a0ac-5613d6f1e461
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340435919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2340435919
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.4095400731
Short name T258
Test name
Test status
Simulation time 165628633947 ps
CPU time 104.14 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:39:50 PM PST 23
Peak memory 200800 kb
Host smart-dd8625d7-684b-4b7f-93b2-ef3c03d45313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095400731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.4095400731
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3356375129
Short name T763
Test name
Test status
Simulation time 327076589336 ps
CPU time 205.83 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:41:36 PM PST 23
Peak memory 200800 kb
Host smart-f2a6ef37-15a5-4d6d-8887-10956d75d8b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356375129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3356375129
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2400775155
Short name T134
Test name
Test status
Simulation time 492960756382 ps
CPU time 1085.16 seconds
Started Dec 27 12:37:46 PM PST 23
Finished Dec 27 12:55:58 PM PST 23
Peak memory 200832 kb
Host smart-8b44419b-6fd1-4b17-8f03-5e12b5102a8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400775155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2400775155
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4167119586
Short name T470
Test name
Test status
Simulation time 340690485791 ps
CPU time 294.75 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:43:06 PM PST 23
Peak memory 200840 kb
Host smart-6a8abd48-19f0-4f19-aaca-66be3a073063
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167119586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.4167119586
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2131015099
Short name T617
Test name
Test status
Simulation time 37773697015 ps
CPU time 92.38 seconds
Started Dec 27 12:40:03 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 200320 kb
Host smart-2e4c60a5-4314-4c03-9125-e76bb6ef4ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131015099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2131015099
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4000996293
Short name T469
Test name
Test status
Simulation time 3848203604 ps
CPU time 5.39 seconds
Started Dec 27 12:37:47 PM PST 23
Finished Dec 27 12:37:58 PM PST 23
Peak memory 200584 kb
Host smart-3d60504b-782d-4f9a-81e9-b1208b6b4198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000996293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4000996293
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2577405665
Short name T418
Test name
Test status
Simulation time 5854188168 ps
CPU time 1.43 seconds
Started Dec 27 12:38:09 PM PST 23
Finished Dec 27 12:38:17 PM PST 23
Peak memory 200612 kb
Host smart-f57e0d33-2494-4f2d-a870-523f85569398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577405665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2577405665
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1777890157
Short name T189
Test name
Test status
Simulation time 349527659439 ps
CPU time 418.89 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:45:05 PM PST 23
Peak memory 200844 kb
Host smart-1e199cb0-4eee-4d18-95b8-a8bbdd56b7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777890157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1777890157
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1505093179
Short name T103
Test name
Test status
Simulation time 98660352309 ps
CPU time 43.27 seconds
Started Dec 27 12:40:04 PM PST 23
Finished Dec 27 12:41:36 PM PST 23
Peak memory 209140 kb
Host smart-878738fb-a923-456b-953f-19171bd5ba67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505093179 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1505093179
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.834962843
Short name T577
Test name
Test status
Simulation time 324719642 ps
CPU time 0.83 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:38:32 PM PST 23
Peak memory 200552 kb
Host smart-0f409d48-5348-4069-aafb-70def6288dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834962843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.834962843
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4269385437
Short name T847
Test name
Test status
Simulation time 323787541422 ps
CPU time 181.74 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:41:24 PM PST 23
Peak memory 200960 kb
Host smart-d9bc15d7-d12a-4569-9ec6-555a261a11ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269385437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4269385437
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.667418015
Short name T658
Test name
Test status
Simulation time 490473212985 ps
CPU time 614.91 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:48:35 PM PST 23
Peak memory 200800 kb
Host smart-e00c6004-63e9-4cdb-9f4a-ec86392d2227
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=667418015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.667418015
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2406034620
Short name T306
Test name
Test status
Simulation time 335186343238 ps
CPU time 218.16 seconds
Started Dec 27 12:39:32 PM PST 23
Finished Dec 27 12:43:45 PM PST 23
Peak memory 198832 kb
Host smart-629e77c1-ddd1-4b23-a786-73563dd57218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406034620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2406034620
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3614597884
Short name T669
Test name
Test status
Simulation time 320724004134 ps
CPU time 371.56 seconds
Started Dec 27 12:38:06 PM PST 23
Finished Dec 27 12:44:24 PM PST 23
Peak memory 200700 kb
Host smart-17befeea-84f0-49ec-9a23-d09565c4cbf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614597884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3614597884
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.258957372
Short name T218
Test name
Test status
Simulation time 332466247957 ps
CPU time 774.02 seconds
Started Dec 27 12:38:53 PM PST 23
Finished Dec 27 12:52:02 PM PST 23
Peak memory 200904 kb
Host smart-c4ebfeaf-9ac4-4ea5-988d-be439205cff2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258957372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.258957372
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1880956903
Short name T440
Test name
Test status
Simulation time 326040029234 ps
CPU time 810.57 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:52:03 PM PST 23
Peak memory 200820 kb
Host smart-fb7bc4ac-031c-41e0-a939-785c4299b740
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880956903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1880956903
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4045555947
Short name T165
Test name
Test status
Simulation time 99178434332 ps
CPU time 553.89 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:47:03 PM PST 23
Peak memory 201228 kb
Host smart-72e9489a-168a-4610-b665-af03e4b172ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045555947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4045555947
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1853235551
Short name T746
Test name
Test status
Simulation time 23750541126 ps
CPU time 58.91 seconds
Started Dec 27 12:39:06 PM PST 23
Finished Dec 27 12:40:22 PM PST 23
Peak memory 200680 kb
Host smart-57eb5007-d387-4d78-b4b5-977327e43ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853235551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1853235551
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4234157714
Short name T666
Test name
Test status
Simulation time 5617590231 ps
CPU time 13.32 seconds
Started Dec 27 12:37:46 PM PST 23
Finished Dec 27 12:38:06 PM PST 23
Peak memory 200580 kb
Host smart-1f9b8194-fcb8-40f2-9a6e-4a4c9c87649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234157714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4234157714
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.489100351
Short name T579
Test name
Test status
Simulation time 5884681141 ps
CPU time 3.83 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:38:12 PM PST 23
Peak memory 200556 kb
Host smart-cd3b6d7b-a6af-408e-a5dd-49ebdb8aeb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489100351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.489100351
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2531157207
Short name T304
Test name
Test status
Simulation time 505783944298 ps
CPU time 134.44 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:40:18 PM PST 23
Peak memory 200828 kb
Host smart-48e46978-4f7f-4663-be2d-ca341653d240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531157207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2531157207
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.133352938
Short name T256
Test name
Test status
Simulation time 99515447791 ps
CPU time 61.29 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:38:51 PM PST 23
Peak memory 209084 kb
Host smart-2e5a7cfc-b255-4a5b-8579-ed7bd020d48c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133352938 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.133352938
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.429299367
Short name T547
Test name
Test status
Simulation time 307735848 ps
CPU time 0.89 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:38:09 PM PST 23
Peak memory 200504 kb
Host smart-7a7845a3-95f1-4ff8-bf1a-a58860f6c045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429299367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.429299367
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1600531726
Short name T246
Test name
Test status
Simulation time 332268176577 ps
CPU time 176.33 seconds
Started Dec 27 12:38:22 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 200760 kb
Host smart-e2ce802d-f61e-497c-ae4e-cbf75d755a11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600531726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1600531726
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.343500318
Short name T732
Test name
Test status
Simulation time 163483911145 ps
CPU time 74.06 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:39:46 PM PST 23
Peak memory 200796 kb
Host smart-99c741d4-6267-4919-8c8a-f21e2e9e17e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343500318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.343500318
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2461645017
Short name T213
Test name
Test status
Simulation time 163386326679 ps
CPU time 94.57 seconds
Started Dec 27 12:37:44 PM PST 23
Finished Dec 27 12:39:26 PM PST 23
Peak memory 200760 kb
Host smart-27ed362c-47ae-4d96-a45d-73ad25f20123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461645017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2461645017
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.742356848
Short name T516
Test name
Test status
Simulation time 330099674700 ps
CPU time 476.37 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:46:27 PM PST 23
Peak memory 200844 kb
Host smart-88afe0dd-5897-469e-b907-72835bdc3912
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=742356848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.742356848
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2984118800
Short name T642
Test name
Test status
Simulation time 494363351530 ps
CPU time 298.52 seconds
Started Dec 27 12:38:46 PM PST 23
Finished Dec 27 12:43:54 PM PST 23
Peak memory 200748 kb
Host smart-b23e9017-1286-4f08-9b2c-5fd33f6c4f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984118800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2984118800
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.735964993
Short name T419
Test name
Test status
Simulation time 491402918784 ps
CPU time 583.63 seconds
Started Dec 27 12:38:56 PM PST 23
Finished Dec 27 12:48:56 PM PST 23
Peak memory 200800 kb
Host smart-bf1afa3d-5cbb-4504-bbe4-faa9cab1239c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735964993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.735964993
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.971496721
Short name T610
Test name
Test status
Simulation time 494004090193 ps
CPU time 137.58 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 200740 kb
Host smart-b7b6f9a2-38a1-4547-b6f6-40d8edc374b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971496721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.971496721
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2521429952
Short name T725
Test name
Test status
Simulation time 119576601015 ps
CPU time 388.6 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:44:48 PM PST 23
Peak memory 201164 kb
Host smart-e5b8967b-f50a-47f5-a2dd-ae9d94253802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521429952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2521429952
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4080253073
Short name T795
Test name
Test status
Simulation time 39826802041 ps
CPU time 24.05 seconds
Started Dec 27 12:38:52 PM PST 23
Finished Dec 27 12:39:30 PM PST 23
Peak memory 200648 kb
Host smart-e8465e31-bdf5-4619-8d6b-6d034a2c483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080253073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4080253073
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.882101951
Short name T819
Test name
Test status
Simulation time 4074491745 ps
CPU time 2.14 seconds
Started Dec 27 12:38:58 PM PST 23
Finished Dec 27 12:39:16 PM PST 23
Peak memory 200564 kb
Host smart-7aac9e9b-d8ed-4adc-ad09-b5172563baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882101951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.882101951
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4264493079
Short name T679
Test name
Test status
Simulation time 5946712527 ps
CPU time 1.58 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:37:52 PM PST 23
Peak memory 200596 kb
Host smart-77cf13d4-6cc2-4e52-b747-607485e9d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264493079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4264493079
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1579974873
Short name T230
Test name
Test status
Simulation time 172682585638 ps
CPU time 380.74 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:44:11 PM PST 23
Peak memory 200784 kb
Host smart-35334f14-cc6a-4ffc-9556-39d182bfd408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579974873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1579974873
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2630476497
Short name T654
Test name
Test status
Simulation time 347341396 ps
CPU time 0.83 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:38:07 PM PST 23
Peak memory 200472 kb
Host smart-04036e7d-39a4-4476-ba64-eb9530c9b53f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630476497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2630476497
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.252817522
Short name T783
Test name
Test status
Simulation time 167565595199 ps
CPU time 388.41 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:44:41 PM PST 23
Peak memory 200164 kb
Host smart-bb676d8f-6ab5-4543-a2ca-05ced4617cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252817522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.252817522
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3273106887
Short name T53
Test name
Test status
Simulation time 172931907016 ps
CPU time 69.18 seconds
Started Dec 27 12:39:00 PM PST 23
Finished Dec 27 12:40:24 PM PST 23
Peak memory 200764 kb
Host smart-d2394501-7e12-47c6-a6e3-4c3d0d1d1540
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273106887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3273106887
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.248905686
Short name T107
Test name
Test status
Simulation time 494358550592 ps
CPU time 150.04 seconds
Started Dec 27 12:39:11 PM PST 23
Finished Dec 27 12:42:05 PM PST 23
Peak memory 200828 kb
Host smart-8b94c324-aeec-488b-82a8-cc094839e851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248905686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.248905686
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3524151203
Short name T754
Test name
Test status
Simulation time 494743160573 ps
CPU time 479.32 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:46:59 PM PST 23
Peak memory 200728 kb
Host smart-43f30ca2-e991-4374-93f7-c48cbf895620
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524151203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3524151203
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3402049201
Short name T329
Test name
Test status
Simulation time 496931414186 ps
CPU time 1184.04 seconds
Started Dec 27 12:39:20 PM PST 23
Finished Dec 27 12:59:31 PM PST 23
Peak memory 200764 kb
Host smart-abe58214-3213-4e48-8da5-3498224e408e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402049201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3402049201
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3330775585
Short name T737
Test name
Test status
Simulation time 161584908198 ps
CPU time 94.97 seconds
Started Dec 27 12:37:59 PM PST 23
Finished Dec 27 12:39:44 PM PST 23
Peak memory 200664 kb
Host smart-e80f619f-c7f3-4605-86b9-1a035b675b18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330775585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3330775585
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2113219119
Short name T667
Test name
Test status
Simulation time 23169478910 ps
CPU time 50.43 seconds
Started Dec 27 12:39:11 PM PST 23
Finished Dec 27 12:40:25 PM PST 23
Peak memory 200652 kb
Host smart-3bcd5209-7f07-44ac-994a-389819ca4454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113219119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2113219119
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2338225202
Short name T542
Test name
Test status
Simulation time 3776799249 ps
CPU time 8.9 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:38:18 PM PST 23
Peak memory 200632 kb
Host smart-1279154a-b7dd-4a6d-8107-0f1abbd28250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338225202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2338225202
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3515801227
Short name T614
Test name
Test status
Simulation time 5737688131 ps
CPU time 7.66 seconds
Started Dec 27 12:37:55 PM PST 23
Finished Dec 27 12:38:10 PM PST 23
Peak memory 200524 kb
Host smart-7a31c9be-bead-419e-affc-8b529c0e32c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515801227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3515801227
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3453497459
Short name T331
Test name
Test status
Simulation time 197634075150 ps
CPU time 45.69 seconds
Started Dec 27 12:37:59 PM PST 23
Finished Dec 27 12:38:55 PM PST 23
Peak memory 200788 kb
Host smart-21ec4150-6c91-4e59-b3d7-4b563ab2279f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453497459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3453497459
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.748851871
Short name T462
Test name
Test status
Simulation time 461984550 ps
CPU time 1.03 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:37:27 PM PST 23
Peak memory 200556 kb
Host smart-b9802703-3e03-4f97-9b61-606f93d4a437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748851871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.748851871
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3955945738
Short name T580
Test name
Test status
Simulation time 159872387198 ps
CPU time 90.95 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:39:15 PM PST 23
Peak memory 200808 kb
Host smart-6cdb3c5f-74a7-46c4-9e68-24a54aa33ac6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955945738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3955945738
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1205437957
Short name T250
Test name
Test status
Simulation time 323851445178 ps
CPU time 91.88 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:39:07 PM PST 23
Peak memory 200812 kb
Host smart-2efa923c-1c7e-438b-b9b2-d0c57c716567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205437957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1205437957
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1230769996
Short name T198
Test name
Test status
Simulation time 327888666528 ps
CPU time 384.93 seconds
Started Dec 27 12:36:56 PM PST 23
Finished Dec 27 12:43:46 PM PST 23
Peak memory 200840 kb
Host smart-75eed9d6-06ee-4f51-be8b-7be98c8020e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230769996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1230769996
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2720738625
Short name T690
Test name
Test status
Simulation time 506090577357 ps
CPU time 181.7 seconds
Started Dec 27 12:37:11 PM PST 23
Finished Dec 27 12:40:36 PM PST 23
Peak memory 200744 kb
Host smart-58487d71-5cc3-4fb6-8a3e-c77992077e75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720738625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2720738625
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3029399910
Short name T602
Test name
Test status
Simulation time 163798873249 ps
CPU time 59.86 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:38:26 PM PST 23
Peak memory 200796 kb
Host smart-4f082117-782a-46a2-a136-574560e28751
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029399910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3029399910
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.254128072
Short name T222
Test name
Test status
Simulation time 382485738288 ps
CPU time 202.8 seconds
Started Dec 27 12:37:29 PM PST 23
Finished Dec 27 12:41:07 PM PST 23
Peak memory 200736 kb
Host smart-bf9eb8fa-f84e-4517-a48a-446bfdac2a2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254128072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.254128072
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2962283345
Short name T756
Test name
Test status
Simulation time 322714308599 ps
CPU time 752.49 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:50:02 PM PST 23
Peak memory 200696 kb
Host smart-e5b489f3-f015-4a39-88b9-a5046cd28931
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962283345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2962283345
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1996960325
Short name T178
Test name
Test status
Simulation time 115190306848 ps
CPU time 626.52 seconds
Started Dec 27 12:37:41 PM PST 23
Finished Dec 27 12:48:17 PM PST 23
Peak memory 201244 kb
Host smart-bf043596-2819-4a5d-9f28-174b9969716d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996960325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1996960325
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.924096920
Short name T857
Test name
Test status
Simulation time 33143168647 ps
CPU time 20.17 seconds
Started Dec 27 12:37:28 PM PST 23
Finished Dec 27 12:38:03 PM PST 23
Peak memory 200572 kb
Host smart-0cc23cd3-57a2-4d89-b8b6-fa09ba5f5dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924096920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.924096920
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1139032508
Short name T578
Test name
Test status
Simulation time 3962149304 ps
CPU time 4.68 seconds
Started Dec 27 12:37:12 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 200616 kb
Host smart-70eb71cb-0e0c-462c-a097-66a04c491d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139032508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1139032508
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.283707990
Short name T44
Test name
Test status
Simulation time 4026575337 ps
CPU time 9.84 seconds
Started Dec 27 12:37:05 PM PST 23
Finished Dec 27 12:37:38 PM PST 23
Peak memory 215800 kb
Host smart-29719d95-4f33-48cf-8f3c-3410609cfd82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283707990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.283707990
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1320992235
Short name T444
Test name
Test status
Simulation time 6148774346 ps
CPU time 4.31 seconds
Started Dec 27 12:36:48 PM PST 23
Finished Dec 27 12:37:20 PM PST 23
Peak memory 200612 kb
Host smart-7941766d-941f-4fa7-8b5f-ba8fe7493eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320992235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1320992235
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2794204326
Short name T812
Test name
Test status
Simulation time 145193814140 ps
CPU time 560.26 seconds
Started Dec 27 12:37:42 PM PST 23
Finished Dec 27 12:47:11 PM PST 23
Peak memory 201248 kb
Host smart-479ba15a-f43f-4cbf-add1-25e36052ba54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794204326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2794204326
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2767236904
Short name T170
Test name
Test status
Simulation time 88123943692 ps
CPU time 143.63 seconds
Started Dec 27 12:37:15 PM PST 23
Finished Dec 27 12:39:59 PM PST 23
Peak memory 209452 kb
Host smart-60da5781-cb50-4580-926d-5a1cdc905947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767236904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2767236904
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.220898755
Short name T497
Test name
Test status
Simulation time 451193690 ps
CPU time 0.85 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:37:49 PM PST 23
Peak memory 200504 kb
Host smart-149438b6-e70f-465b-b592-74656151c610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220898755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.220898755
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2589692687
Short name T266
Test name
Test status
Simulation time 169502588009 ps
CPU time 186.87 seconds
Started Dec 27 12:37:50 PM PST 23
Finished Dec 27 12:41:01 PM PST 23
Peak memory 200776 kb
Host smart-77df0e02-24ee-4862-8e11-7644cb683c7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589692687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2589692687
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3515607417
Short name T343
Test name
Test status
Simulation time 490019268176 ps
CPU time 588.41 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:47:46 PM PST 23
Peak memory 200776 kb
Host smart-87455937-0b20-48a6-8ad4-b457f7874292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515607417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3515607417
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1635936588
Short name T264
Test name
Test status
Simulation time 491909817231 ps
CPU time 553.58 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 200904 kb
Host smart-656c4e05-80ea-44e4-9788-68de8b269e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635936588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1635936588
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3348496750
Short name T675
Test name
Test status
Simulation time 168041160134 ps
CPU time 393.55 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:44:41 PM PST 23
Peak memory 200772 kb
Host smart-284207b5-e37f-41a5-8efa-9e81dca03f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348496750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3348496750
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3264810711
Short name T794
Test name
Test status
Simulation time 155947028964 ps
CPU time 375.48 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:44:13 PM PST 23
Peak memory 200824 kb
Host smart-a89125b0-1cc1-4608-904b-8c0af836d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264810711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3264810711
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2477733708
Short name T538
Test name
Test status
Simulation time 164506596700 ps
CPU time 200.25 seconds
Started Dec 27 12:37:45 PM PST 23
Finished Dec 27 12:41:12 PM PST 23
Peak memory 200760 kb
Host smart-acea041a-0556-4de4-9ea6-4daf39da5dd8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477733708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2477733708
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1885988886
Short name T317
Test name
Test status
Simulation time 331095049870 ps
CPU time 764.55 seconds
Started Dec 27 12:38:56 PM PST 23
Finished Dec 27 12:51:55 PM PST 23
Peak memory 200816 kb
Host smart-a0151ee7-a1b8-410c-8671-abeaa7c6d8b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885988886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1885988886
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4067264630
Short name T437
Test name
Test status
Simulation time 162814324221 ps
CPU time 351.18 seconds
Started Dec 27 12:37:43 PM PST 23
Finished Dec 27 12:43:42 PM PST 23
Peak memory 200708 kb
Host smart-74c2018f-2bb6-49d0-b883-ca0a6dbbfc2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067264630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4067264630
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2036180662
Short name T698
Test name
Test status
Simulation time 37787791726 ps
CPU time 20.98 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:44 PM PST 23
Peak memory 200588 kb
Host smart-375d5a58-228e-493b-8efa-e0bdc58148bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036180662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2036180662
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1638465061
Short name T616
Test name
Test status
Simulation time 4316688936 ps
CPU time 2.99 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:38:35 PM PST 23
Peak memory 200608 kb
Host smart-b05a3815-2a92-478b-8894-b0a571ed1369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638465061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1638465061
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1451722393
Short name T502
Test name
Test status
Simulation time 5787108503 ps
CPU time 14.93 seconds
Started Dec 27 12:37:39 PM PST 23
Finished Dec 27 12:38:05 PM PST 23
Peak memory 200520 kb
Host smart-af9c2078-de76-420b-99e8-48e4bdf485ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451722393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1451722393
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.934042807
Short name T793
Test name
Test status
Simulation time 173893705185 ps
CPU time 75.55 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:39:13 PM PST 23
Peak memory 200776 kb
Host smart-1f7d672d-397a-4711-9faa-8096ca9b27d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934042807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
934042807
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1084008609
Short name T242
Test name
Test status
Simulation time 16089235172 ps
CPU time 36.01 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:38:58 PM PST 23
Peak memory 209448 kb
Host smart-3c1a1c30-c3b2-49b5-9684-e49856183cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084008609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1084008609
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2881746929
Short name T692
Test name
Test status
Simulation time 557461968 ps
CPU time 0.91 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:38:29 PM PST 23
Peak memory 200464 kb
Host smart-f6627270-6525-47e5-a245-706a48b987c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881746929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2881746929
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2484030421
Short name T328
Test name
Test status
Simulation time 328798403377 ps
CPU time 693.68 seconds
Started Dec 27 12:38:06 PM PST 23
Finished Dec 27 12:49:46 PM PST 23
Peak memory 200700 kb
Host smart-12815790-0bf3-476e-9519-a405185a3152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484030421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2484030421
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3025873300
Short name T267
Test name
Test status
Simulation time 333460308443 ps
CPU time 776.56 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:51:10 PM PST 23
Peak memory 200848 kb
Host smart-c7260e9e-516d-4e3d-b236-9c2138e34247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025873300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3025873300
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3033674752
Short name T609
Test name
Test status
Simulation time 487824988241 ps
CPU time 483.42 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:46:23 PM PST 23
Peak memory 200736 kb
Host smart-b5c0f941-e23d-436f-83dc-f384a7c04700
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033674752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3033674752
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.318526959
Short name T243
Test name
Test status
Simulation time 491663913723 ps
CPU time 1120.9 seconds
Started Dec 27 12:37:52 PM PST 23
Finished Dec 27 12:56:37 PM PST 23
Peak memory 200760 kb
Host smart-cb948ced-ba34-4efd-8ee0-79f002076d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318526959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.318526959
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.97501985
Short name T573
Test name
Test status
Simulation time 162789574593 ps
CPU time 98.67 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:39:28 PM PST 23
Peak memory 200764 kb
Host smart-4684b84b-5aaf-4fe7-9711-90303811c23c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=97501985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fixed
.97501985
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1287338543
Short name T17
Test name
Test status
Simulation time 163361561081 ps
CPU time 58.67 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 200680 kb
Host smart-339bb1f6-781d-4d3f-bea8-66bc1361c955
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287338543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1287338543
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1911933325
Short name T183
Test name
Test status
Simulation time 97315119878 ps
CPU time 509.37 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:46:41 PM PST 23
Peak memory 201260 kb
Host smart-38a760d2-e953-4fe1-8cce-c41ac9150c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911933325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1911933325
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3499413279
Short name T625
Test name
Test status
Simulation time 29646495374 ps
CPU time 15.95 seconds
Started Dec 27 12:38:03 PM PST 23
Finished Dec 27 12:38:27 PM PST 23
Peak memory 200588 kb
Host smart-0a127a34-4167-4dd7-ae60-80424de5960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499413279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3499413279
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3774113602
Short name T801
Test name
Test status
Simulation time 4110363268 ps
CPU time 5.01 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:38:19 PM PST 23
Peak memory 200616 kb
Host smart-fd78d7cf-1b83-4084-868a-f9631ff70f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774113602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3774113602
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2406812192
Short name T546
Test name
Test status
Simulation time 5887110406 ps
CPU time 4.53 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:38:12 PM PST 23
Peak memory 200544 kb
Host smart-1590c353-0838-4a71-8ab5-4859301752ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406812192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2406812192
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3908974638
Short name T830
Test name
Test status
Simulation time 462254415 ps
CPU time 0.87 seconds
Started Dec 27 12:37:41 PM PST 23
Finished Dec 27 12:37:51 PM PST 23
Peak memory 200528 kb
Host smart-48f072dc-5d52-4129-8a5b-0bca11d91517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908974638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3908974638
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.971262881
Short name T832
Test name
Test status
Simulation time 159665071438 ps
CPU time 74.82 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:39:43 PM PST 23
Peak memory 200832 kb
Host smart-a8ee5978-185c-480e-95fa-b02179c76971
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971262881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.971262881
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1119185431
Short name T274
Test name
Test status
Simulation time 491913037787 ps
CPU time 1116.33 seconds
Started Dec 27 12:37:59 PM PST 23
Finished Dec 27 12:56:46 PM PST 23
Peak memory 200868 kb
Host smart-95eae13e-5b64-4afd-9472-3746d03b6d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119185431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1119185431
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1588789963
Short name T102
Test name
Test status
Simulation time 484411080826 ps
CPU time 560.85 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:47:49 PM PST 23
Peak memory 200820 kb
Host smart-947ca8d2-6d51-481f-990d-05e1e1c43cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588789963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1588789963
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2431224400
Short name T494
Test name
Test status
Simulation time 326187510373 ps
CPU time 165.56 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:40:57 PM PST 23
Peak memory 200756 kb
Host smart-d919d1c5-8d43-4d8e-814d-eef202ad783d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431224400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2431224400
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.861909779
Short name T265
Test name
Test status
Simulation time 325142295174 ps
CPU time 97.1 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:39:54 PM PST 23
Peak memory 200756 kb
Host smart-cc58d09f-5947-4cc8-a08c-e0336296975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861909779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.861909779
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3251533271
Short name T860
Test name
Test status
Simulation time 487133582964 ps
CPU time 249.66 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:42:42 PM PST 23
Peak memory 200760 kb
Host smart-89a6bd5c-e9a5-46da-81eb-8db29774f64d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251533271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3251533271
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3360228827
Short name T501
Test name
Test status
Simulation time 155778324801 ps
CPU time 24.16 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:38:36 PM PST 23
Peak memory 200784 kb
Host smart-820800b2-afa0-4feb-a193-175dcc442641
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360228827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3360228827
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1694274971
Short name T352
Test name
Test status
Simulation time 104198660046 ps
CPU time 292.99 seconds
Started Dec 27 12:37:42 PM PST 23
Finished Dec 27 12:42:44 PM PST 23
Peak memory 201132 kb
Host smart-8d7aa24c-03d2-426d-bda8-b7f61cf871d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694274971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1694274971
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3426430226
Short name T766
Test name
Test status
Simulation time 24714889298 ps
CPU time 10.42 seconds
Started Dec 27 12:38:19 PM PST 23
Finished Dec 27 12:38:38 PM PST 23
Peak memory 200616 kb
Host smart-f2871a12-d927-40d9-bdd9-6d35d9f10798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426430226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3426430226
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.639055071
Short name T829
Test name
Test status
Simulation time 4626109373 ps
CPU time 6.22 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:28 PM PST 23
Peak memory 200668 kb
Host smart-7d87c9cc-6229-4e3c-af5f-bc98f9b8abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639055071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.639055071
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3508988374
Short name T509
Test name
Test status
Simulation time 5719733913 ps
CPU time 5.53 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:38:25 PM PST 23
Peak memory 200516 kb
Host smart-2f8148b5-4824-4793-a085-3aaa8e1fa556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508988374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3508988374
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3479877806
Short name T591
Test name
Test status
Simulation time 330790128580 ps
CPU time 276.79 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:42:51 PM PST 23
Peak memory 200740 kb
Host smart-76d4ef91-9e83-4b07-a836-d5cdaa7e8437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479877806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3479877806
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2992231795
Short name T478
Test name
Test status
Simulation time 475500717 ps
CPU time 1.71 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:38:13 PM PST 23
Peak memory 200548 kb
Host smart-7475f13a-a501-4578-86d7-bf40053f44ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992231795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2992231795
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3974187905
Short name T798
Test name
Test status
Simulation time 164846783653 ps
CPU time 95.18 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:39:57 PM PST 23
Peak memory 200736 kb
Host smart-c54fae4a-74c0-44a5-b731-f371127cccc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974187905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3974187905
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4163626889
Short name T125
Test name
Test status
Simulation time 502779794241 ps
CPU time 469.92 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:46:21 PM PST 23
Peak memory 200784 kb
Host smart-60bfed3d-d8e1-42af-94e5-3fa1b2cc4550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163626889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4163626889
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.653929693
Short name T805
Test name
Test status
Simulation time 160968666706 ps
CPU time 103.35 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:40:19 PM PST 23
Peak memory 200784 kb
Host smart-a1bf9339-9152-4c27-a57a-4db0f36d25ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653929693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.653929693
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.912079896
Short name T778
Test name
Test status
Simulation time 161927945867 ps
CPU time 181.45 seconds
Started Dec 27 12:37:43 PM PST 23
Finished Dec 27 12:40:52 PM PST 23
Peak memory 200684 kb
Host smart-539c0d6c-a0f7-49cb-92fa-34649ab506f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912079896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.912079896
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.278968982
Short name T722
Test name
Test status
Simulation time 326576611076 ps
CPU time 822.14 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:51:54 PM PST 23
Peak memory 200932 kb
Host smart-15cb8819-28f7-4102-ab91-bd9088264500
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=278968982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.278968982
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.400148879
Short name T340
Test name
Test status
Simulation time 514196150918 ps
CPU time 84.29 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:40:06 PM PST 23
Peak memory 200896 kb
Host smart-6c1d25cc-496f-420b-8747-c5d24e6b4d85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400148879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.400148879
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1812133965
Short name T13
Test name
Test status
Simulation time 336366832787 ps
CPU time 350.3 seconds
Started Dec 27 12:37:53 PM PST 23
Finished Dec 27 12:43:47 PM PST 23
Peak memory 200768 kb
Host smart-eaa0c387-4e36-4018-92e0-4bebfb7b236f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812133965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1812133965
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1557083099
Short name T350
Test name
Test status
Simulation time 100028254731 ps
CPU time 275.75 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:43:16 PM PST 23
Peak memory 201200 kb
Host smart-c2939b5c-e09e-4db3-bd41-e2da11344808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557083099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1557083099
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.11777212
Short name T515
Test name
Test status
Simulation time 43612341867 ps
CPU time 91.04 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:40:13 PM PST 23
Peak memory 200624 kb
Host smart-03cf9e99-c761-4079-9142-d562684c9fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11777212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.11777212
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3289021926
Short name T95
Test name
Test status
Simulation time 4270481198 ps
CPU time 9.25 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:38:26 PM PST 23
Peak memory 200704 kb
Host smart-4b5264d2-152e-49cc-b1d7-abc689215e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289021926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3289021926
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4092670646
Short name T425
Test name
Test status
Simulation time 5792182046 ps
CPU time 4.85 seconds
Started Dec 27 12:37:41 PM PST 23
Finished Dec 27 12:37:55 PM PST 23
Peak memory 200516 kb
Host smart-92f7e469-6b09-47eb-aa6e-09986514a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092670646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4092670646
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.38342919
Short name T574
Test name
Test status
Simulation time 49705826711 ps
CPU time 103.83 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:40:01 PM PST 23
Peak memory 200564 kb
Host smart-21d1364e-0709-405c-9061-2d0ad3c55183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38342919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.38342919
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1519994042
Short name T526
Test name
Test status
Simulation time 323119603 ps
CPU time 0.85 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:38:40 PM PST 23
Peak memory 200540 kb
Host smart-ebb16f66-698f-4090-bcae-9c18658d9f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519994042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1519994042
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3380594932
Short name T231
Test name
Test status
Simulation time 328878258489 ps
CPU time 197.51 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 200884 kb
Host smart-878a66d7-bd91-4950-afd2-57a35f747a74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380594932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3380594932
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.529743518
Short name T154
Test name
Test status
Simulation time 492416044146 ps
CPU time 195.56 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:41:26 PM PST 23
Peak memory 200896 kb
Host smart-4722ec6e-86e1-452a-8c31-bd658abdf2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529743518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.529743518
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2350226438
Short name T678
Test name
Test status
Simulation time 498391580070 ps
CPU time 286.04 seconds
Started Dec 27 12:38:21 PM PST 23
Finished Dec 27 12:43:15 PM PST 23
Peak memory 200720 kb
Host smart-f7a196c5-ad3d-4645-a56e-e7e3ba346210
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350226438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2350226438
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.164081667
Short name T710
Test name
Test status
Simulation time 494495393749 ps
CPU time 1232.28 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:59:04 PM PST 23
Peak memory 200848 kb
Host smart-9ea1b780-f758-4e5d-95bc-25a4c796d851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164081667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.164081667
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3866766891
Short name T477
Test name
Test status
Simulation time 324859110618 ps
CPU time 690.51 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:49:48 PM PST 23
Peak memory 200752 kb
Host smart-7ccd9d04-8e06-4d4f-b90a-4029add19a8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866766891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3866766891
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.24788579
Short name T518
Test name
Test status
Simulation time 165626266053 ps
CPU time 105.44 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:40:33 PM PST 23
Peak memory 200736 kb
Host smart-52d47227-1b07-4438-b350-b7b47ba09a3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24788579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.a
dc_ctrl_filters_wakeup_fixed.24788579
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.984142728
Short name T631
Test name
Test status
Simulation time 123045517617 ps
CPU time 442.99 seconds
Started Dec 27 12:38:13 PM PST 23
Finished Dec 27 12:45:44 PM PST 23
Peak memory 201092 kb
Host smart-d8c13e51-710d-4209-8355-e1f581d0d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984142728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.984142728
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2141228705
Short name T816
Test name
Test status
Simulation time 27984158186 ps
CPU time 14.74 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:38:27 PM PST 23
Peak memory 200616 kb
Host smart-0833fc71-a7bf-4f70-87bf-afd36a4bb8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141228705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2141228705
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1228542147
Short name T506
Test name
Test status
Simulation time 4002297020 ps
CPU time 2.84 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:38:40 PM PST 23
Peak memory 200696 kb
Host smart-d8d660be-0cac-47a0-a6eb-82ffa7e2acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228542147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1228542147
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.830764587
Short name T136
Test name
Test status
Simulation time 5938322351 ps
CPU time 4.18 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:38:10 PM PST 23
Peak memory 200612 kb
Host smart-8566c661-8c3c-4ea6-b5bb-6e51b9b9de4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830764587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.830764587
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1164113752
Short name T850
Test name
Test status
Simulation time 55391734744 ps
CPU time 121.05 seconds
Started Dec 27 12:38:13 PM PST 23
Finished Dec 27 12:40:21 PM PST 23
Peak memory 200720 kb
Host smart-5a91cd78-1f85-4de4-b5ed-2641614c4287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164113752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1164113752
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1521852242
Short name T748
Test name
Test status
Simulation time 77075899253 ps
CPU time 329.49 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:43:58 PM PST 23
Peak memory 209508 kb
Host smart-db620673-c012-4f84-8d53-15e7e0484a97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521852242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1521852242
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.945679667
Short name T488
Test name
Test status
Simulation time 467361966 ps
CPU time 0.88 seconds
Started Dec 27 12:37:33 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 200528 kb
Host smart-a5225af2-e11e-4ab7-81ad-8051fc310bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945679667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.945679667
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3197556319
Short name T757
Test name
Test status
Simulation time 322675536712 ps
CPU time 307.37 seconds
Started Dec 27 12:38:03 PM PST 23
Finished Dec 27 12:43:18 PM PST 23
Peak memory 200792 kb
Host smart-98829241-24c5-478b-ade3-17c45e779e5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197556319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3197556319
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1039499330
Short name T252
Test name
Test status
Simulation time 328802853907 ps
CPU time 760.92 seconds
Started Dec 27 12:38:18 PM PST 23
Finished Dec 27 12:51:11 PM PST 23
Peak memory 200900 kb
Host smart-7a1f5875-5995-4d26-a7d0-c80bfac27034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039499330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1039499330
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4055129606
Short name T311
Test name
Test status
Simulation time 162568029232 ps
CPU time 180.75 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:41:07 PM PST 23
Peak memory 200836 kb
Host smart-c54e361c-1068-413d-a98d-b86a6d9313cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055129606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4055129606
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3168236621
Short name T704
Test name
Test status
Simulation time 163844382230 ps
CPU time 66.71 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:39:23 PM PST 23
Peak memory 200772 kb
Host smart-2546258c-6725-4192-823c-07aec26c99fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168236621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3168236621
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2262300963
Short name T209
Test name
Test status
Simulation time 169757161006 ps
CPU time 380.13 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:44:42 PM PST 23
Peak memory 200804 kb
Host smart-ca8aef57-4c55-40ce-bf35-1acabd8fbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262300963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2262300963
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3256343006
Short name T620
Test name
Test status
Simulation time 325363398503 ps
CPU time 789.27 seconds
Started Dec 27 12:38:00 PM PST 23
Finished Dec 27 12:51:19 PM PST 23
Peak memory 200752 kb
Host smart-2fe9eff5-019d-4135-989d-9626463478f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256343006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3256343006
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2101200054
Short name T324
Test name
Test status
Simulation time 329405643109 ps
CPU time 796.9 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:51:24 PM PST 23
Peak memory 200796 kb
Host smart-620c9abd-658f-424f-a1e7-c277fb8742d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101200054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2101200054
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1140084744
Short name T681
Test name
Test status
Simulation time 166586812272 ps
CPU time 373.45 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:44:19 PM PST 23
Peak memory 200728 kb
Host smart-7d7cdf76-382a-4311-9527-e44ac6f9fde4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140084744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1140084744
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4175817014
Short name T800
Test name
Test status
Simulation time 106658294290 ps
CPU time 592.44 seconds
Started Dec 27 12:38:22 PM PST 23
Finished Dec 27 12:48:22 PM PST 23
Peak memory 201236 kb
Host smart-e00b40a8-8ae2-4ef8-af32-7fb10d260c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175817014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4175817014
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3171230974
Short name T427
Test name
Test status
Simulation time 26333455619 ps
CPU time 4.61 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:38:15 PM PST 23
Peak memory 200608 kb
Host smart-9e0bf782-7de5-4248-9680-cb7bb5de5559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171230974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3171230974
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.709910644
Short name T728
Test name
Test status
Simulation time 5152042715 ps
CPU time 3.65 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:38:45 PM PST 23
Peak memory 200612 kb
Host smart-51e6dd28-0b4d-4377-9a34-65982f2b0e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709910644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.709910644
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2478391865
Short name T623
Test name
Test status
Simulation time 5789452995 ps
CPU time 12.46 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:38:45 PM PST 23
Peak memory 200600 kb
Host smart-ae17dc49-80b9-4fe2-b72d-fc561595529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478391865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2478391865
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2482834722
Short name T596
Test name
Test status
Simulation time 329121049676 ps
CPU time 199.87 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:41:33 PM PST 23
Peak memory 200756 kb
Host smart-d66d38a7-dde6-4dcf-9b75-8f3ace195b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482834722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2482834722
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3892851079
Short name T635
Test name
Test status
Simulation time 428305789 ps
CPU time 1.09 seconds
Started Dec 27 12:38:09 PM PST 23
Finished Dec 27 12:38:16 PM PST 23
Peak memory 200508 kb
Host smart-865783a9-badf-4ab4-8fc6-f0621c4c433c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892851079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3892851079
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2785649390
Short name T332
Test name
Test status
Simulation time 330324545535 ps
CPU time 365.02 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:44:21 PM PST 23
Peak memory 200804 kb
Host smart-ae4f4445-5269-4553-a607-6fe17ebf9ab0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785649390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2785649390
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.478086433
Short name T648
Test name
Test status
Simulation time 485560346771 ps
CPU time 1163.13 seconds
Started Dec 27 12:38:08 PM PST 23
Finished Dec 27 12:57:37 PM PST 23
Peak memory 200672 kb
Host smart-9daa510d-5439-4c53-8fe3-306133fabe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478086433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.478086433
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3787800896
Short name T424
Test name
Test status
Simulation time 326413500518 ps
CPU time 179.34 seconds
Started Dec 27 12:38:35 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200792 kb
Host smart-d8fb22f7-6129-4307-a223-8e1b9caed46f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787800896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3787800896
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.540773744
Short name T120
Test name
Test status
Simulation time 160691767526 ps
CPU time 99.58 seconds
Started Dec 27 12:38:13 PM PST 23
Finished Dec 27 12:40:00 PM PST 23
Peak memory 200768 kb
Host smart-c5449962-d4d3-460c-9633-9c8057c3f625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540773744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.540773744
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4157858987
Short name T473
Test name
Test status
Simulation time 171241167812 ps
CPU time 88.5 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:40:02 PM PST 23
Peak memory 200724 kb
Host smart-ed390599-caee-4a21-b429-05567cd02d98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157858987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4157858987
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1008291829
Short name T226
Test name
Test status
Simulation time 159805571156 ps
CPU time 371.77 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:44:36 PM PST 23
Peak memory 200748 kb
Host smart-01e3ca31-8015-4f3d-8438-58ae66d856ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008291829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1008291829
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3081990312
Short name T760
Test name
Test status
Simulation time 166567840489 ps
CPU time 373.44 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:44:35 PM PST 23
Peak memory 200788 kb
Host smart-24667a9a-be4a-4d14-8ab4-c136d5f73269
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081990312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3081990312
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3556045820
Short name T445
Test name
Test status
Simulation time 90745162706 ps
CPU time 404.62 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:45:16 PM PST 23
Peak memory 201244 kb
Host smart-c6ec613e-cb32-4da6-bfc7-47c8707cafbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556045820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3556045820
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.968407779
Short name T694
Test name
Test status
Simulation time 35069064111 ps
CPU time 78.37 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:39:45 PM PST 23
Peak memory 200632 kb
Host smart-383c698a-1a67-4184-b805-eaa6aa7113c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968407779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.968407779
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3537109248
Short name T624
Test name
Test status
Simulation time 3090421358 ps
CPU time 2.75 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:25 PM PST 23
Peak memory 200556 kb
Host smart-3f33f219-e075-4146-85af-de88cddce8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537109248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3537109248
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3293589475
Short name T499
Test name
Test status
Simulation time 5907909984 ps
CPU time 14.4 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:39:01 PM PST 23
Peak memory 200664 kb
Host smart-6bd621c1-f68a-4402-844e-7388fad4f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293589475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3293589475
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.433171995
Short name T560
Test name
Test status
Simulation time 190845966231 ps
CPU time 79.16 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:39:42 PM PST 23
Peak memory 200824 kb
Host smart-d3926a32-01f2-47be-8008-284f24385c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433171995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
433171995
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1826888264
Short name T514
Test name
Test status
Simulation time 391055847 ps
CPU time 0.83 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:38:12 PM PST 23
Peak memory 200592 kb
Host smart-fa7591cd-9daf-458f-a4c9-8daa555ad380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826888264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1826888264
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.163167770
Short name T46
Test name
Test status
Simulation time 329567542010 ps
CPU time 569.43 seconds
Started Dec 27 12:37:56 PM PST 23
Finished Dec 27 12:47:35 PM PST 23
Peak memory 200860 kb
Host smart-df064df0-def4-4499-b174-5d9007f99eb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163167770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.163167770
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.174387070
Short name T309
Test name
Test status
Simulation time 162513242534 ps
CPU time 383.06 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:44:46 PM PST 23
Peak memory 200852 kb
Host smart-7b307901-8025-47cb-ab0d-a9b309c370ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174387070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.174387070
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.569238221
Short name T297
Test name
Test status
Simulation time 490275048630 ps
CPU time 1108.14 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:56:35 PM PST 23
Peak memory 200804 kb
Host smart-eff52a05-ee4e-4b94-9907-16189fa26228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569238221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.569238221
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1426885672
Short name T810
Test name
Test status
Simulation time 492008386580 ps
CPU time 1138.16 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:57:21 PM PST 23
Peak memory 200808 kb
Host smart-3801834c-b1b6-4bf3-ad79-54ac8b45964e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426885672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1426885672
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1512849127
Short name T52
Test name
Test status
Simulation time 163377298206 ps
CPU time 370.36 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:44:20 PM PST 23
Peak memory 200808 kb
Host smart-4e836fc4-f52e-4211-9d8c-208c94898114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512849127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1512849127
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1532512929
Short name T139
Test name
Test status
Simulation time 163562398750 ps
CPU time 86.45 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:39:33 PM PST 23
Peak memory 200756 kb
Host smart-adeedab9-65b4-4dea-91ce-d81184dd53e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532512929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1532512929
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1439914376
Short name T207
Test name
Test status
Simulation time 162798583308 ps
CPU time 171.87 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:41:17 PM PST 23
Peak memory 200824 kb
Host smart-a9d38459-a93c-467b-8167-81bdcebccac1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439914376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1439914376
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3255514368
Short name T838
Test name
Test status
Simulation time 489888441692 ps
CPU time 277.54 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:43:10 PM PST 23
Peak memory 200752 kb
Host smart-f22efc7c-53f3-46db-ac16-3758d0035005
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255514368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3255514368
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.4033485502
Short name T442
Test name
Test status
Simulation time 78641836212 ps
CPU time 315.67 seconds
Started Dec 27 12:38:08 PM PST 23
Finished Dec 27 12:43:30 PM PST 23
Peak memory 201168 kb
Host smart-c136d0e2-c072-4946-b6ee-2a0125ec3d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033485502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.4033485502
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1199839466
Short name T771
Test name
Test status
Simulation time 26192206667 ps
CPU time 60.14 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:39:17 PM PST 23
Peak memory 200588 kb
Host smart-259fec6a-6af1-40b4-9c4c-1a0609d0242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199839466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1199839466
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3255151146
Short name T752
Test name
Test status
Simulation time 3224414734 ps
CPU time 8.19 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:38:39 PM PST 23
Peak memory 200600 kb
Host smart-30891b5d-0679-4abb-b646-61a613638fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255151146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3255151146
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2956040542
Short name T646
Test name
Test status
Simulation time 5991095787 ps
CPU time 4.39 seconds
Started Dec 27 12:38:22 PM PST 23
Finished Dec 27 12:38:34 PM PST 23
Peak memory 200584 kb
Host smart-df6e6a15-b622-435a-8830-98d0d8af22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956040542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2956040542
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3748994867
Short name T48
Test name
Test status
Simulation time 322508620787 ps
CPU time 733.08 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:50:26 PM PST 23
Peak memory 200728 kb
Host smart-e4b7615f-4db0-4a00-8b60-edae651f0c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748994867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3748994867
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3811822693
Short name T833
Test name
Test status
Simulation time 92975845947 ps
CPU time 114.11 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:40:26 PM PST 23
Peak memory 200816 kb
Host smart-e030d1ab-8d10-4e49-a89c-470271ac6421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811822693 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3811822693
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.42041532
Short name T791
Test name
Test status
Simulation time 364934740 ps
CPU time 0.82 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:38:57 PM PST 23
Peak memory 200540 kb
Host smart-5b2885a0-aa14-4e7e-a6af-5f09c98d696a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42041532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.42041532
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.779013037
Short name T202
Test name
Test status
Simulation time 163464267256 ps
CPU time 200.12 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:41:55 PM PST 23
Peak memory 200744 kb
Host smart-f08ea2f6-abb4-4982-bd8e-6eb08430d2c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779013037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.779013037
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3248159112
Short name T569
Test name
Test status
Simulation time 165565080099 ps
CPU time 378.93 seconds
Started Dec 27 12:38:43 PM PST 23
Finished Dec 27 12:45:12 PM PST 23
Peak memory 200840 kb
Host smart-638cef22-e910-4533-a17f-7e474a6a7331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248159112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3248159112
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2720201700
Short name T288
Test name
Test status
Simulation time 327875833321 ps
CPU time 208.63 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 200764 kb
Host smart-f89e3a90-5acc-4e5a-94b1-9b14b943db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720201700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2720201700
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2650076075
Short name T511
Test name
Test status
Simulation time 328619089272 ps
CPU time 748.73 seconds
Started Dec 27 12:38:21 PM PST 23
Finished Dec 27 12:50:58 PM PST 23
Peak memory 200820 kb
Host smart-d2738d77-84df-473b-ae57-db9c0f6ee1ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650076075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2650076075
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2732321453
Short name T110
Test name
Test status
Simulation time 488233919391 ps
CPU time 88.29 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:40:02 PM PST 23
Peak memory 200736 kb
Host smart-bee5204d-5524-4555-8e6c-6572d6ef316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732321453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2732321453
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3724012549
Short name T845
Test name
Test status
Simulation time 325635254431 ps
CPU time 414.46 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:45:35 PM PST 23
Peak memory 200712 kb
Host smart-6f7bb155-6f8e-447c-8fbc-229c6b9070fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724012549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3724012549
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.903920485
Short name T337
Test name
Test status
Simulation time 324609385462 ps
CPU time 101.29 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:39:57 PM PST 23
Peak memory 200744 kb
Host smart-a6cf1316-c99f-4698-bc30-bf756787f434
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903920485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.903920485
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2765419217
Short name T842
Test name
Test status
Simulation time 334079587363 ps
CPU time 704.71 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:50:17 PM PST 23
Peak memory 200704 kb
Host smart-c2b7817a-197a-47c7-a3c9-ceb113b8fe4f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765419217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2765419217
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2976687498
Short name T773
Test name
Test status
Simulation time 76153557172 ps
CPU time 359.54 seconds
Started Dec 27 12:38:06 PM PST 23
Finished Dec 27 12:44:12 PM PST 23
Peak memory 201268 kb
Host smart-66eca7fa-f158-401b-bb14-afe4d72676c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976687498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2976687498
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2571373092
Short name T428
Test name
Test status
Simulation time 34315000902 ps
CPU time 20.43 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:38:42 PM PST 23
Peak memory 200648 kb
Host smart-7a1ac5e5-6e07-453b-8958-7cc7a01b5e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571373092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2571373092
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1783048986
Short name T785
Test name
Test status
Simulation time 4128439511 ps
CPU time 10.67 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 200612 kb
Host smart-580bbbac-8179-44d7-950b-5cc66d150e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783048986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1783048986
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4113193705
Short name T716
Test name
Test status
Simulation time 5767105199 ps
CPU time 4.19 seconds
Started Dec 27 12:38:00 PM PST 23
Finished Dec 27 12:38:13 PM PST 23
Peak memory 200556 kb
Host smart-fdfbc37a-775b-4eed-b161-4f663d02407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113193705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4113193705
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2933693140
Short name T652
Test name
Test status
Simulation time 246644325284 ps
CPU time 833.71 seconds
Started Dec 27 12:38:03 PM PST 23
Finished Dec 27 12:52:05 PM PST 23
Peak memory 217624 kb
Host smart-3184ffcf-4556-4c35-b04f-39a2e8a76af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933693140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2933693140
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3414544130
Short name T316
Test name
Test status
Simulation time 106938528857 ps
CPU time 135.9 seconds
Started Dec 27 12:38:22 PM PST 23
Finished Dec 27 12:40:46 PM PST 23
Peak memory 209544 kb
Host smart-ef08f38b-688b-4cd1-b7b6-f9b8e520b279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414544130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3414544130
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1801463625
Short name T745
Test name
Test status
Simulation time 505482103 ps
CPU time 1.87 seconds
Started Dec 27 12:39:24 PM PST 23
Finished Dec 27 12:39:54 PM PST 23
Peak memory 199740 kb
Host smart-5734abfe-6f94-4ef2-b594-8fea428e29a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801463625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1801463625
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2942055490
Short name T615
Test name
Test status
Simulation time 337115330065 ps
CPU time 345.93 seconds
Started Dec 27 12:38:19 PM PST 23
Finished Dec 27 12:44:13 PM PST 23
Peak memory 200812 kb
Host smart-3d94e684-0d84-4db1-a414-f01287c3b361
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942055490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2942055490
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2924254172
Short name T227
Test name
Test status
Simulation time 323865469099 ps
CPU time 191.26 seconds
Started Dec 27 12:38:21 PM PST 23
Finished Dec 27 12:41:40 PM PST 23
Peak memory 200712 kb
Host smart-bccb7ff2-5c29-4224-82da-6d8532d39201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924254172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2924254172
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2668500203
Short name T582
Test name
Test status
Simulation time 163584463886 ps
CPU time 387.64 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:44:44 PM PST 23
Peak memory 200736 kb
Host smart-604741f8-d728-4b18-901d-870fe9d3ff25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668500203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2668500203
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2527733283
Short name T814
Test name
Test status
Simulation time 490174816942 ps
CPU time 1138.83 seconds
Started Dec 27 12:38:00 PM PST 23
Finished Dec 27 12:57:08 PM PST 23
Peak memory 200824 kb
Host smart-dece140f-3f41-4d93-9ce9-98490cf6213e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527733283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2527733283
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2380370548
Short name T138
Test name
Test status
Simulation time 165828713452 ps
CPU time 104.55 seconds
Started Dec 27 12:40:02 PM PST 23
Finished Dec 27 12:42:36 PM PST 23
Peak memory 200488 kb
Host smart-ebb0a95e-a611-434d-b97f-b36688de3980
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380370548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2380370548
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.668732619
Short name T521
Test name
Test status
Simulation time 500960549075 ps
CPU time 1050.91 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:56:09 PM PST 23
Peak memory 200812 kb
Host smart-98576c41-6265-4305-9363-c7f353585fc5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668732619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.668732619
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2763863215
Short name T841
Test name
Test status
Simulation time 82508075176 ps
CPU time 261.5 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:42:33 PM PST 23
Peak memory 201228 kb
Host smart-6c685efa-643d-4df5-aa52-630ae14369b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763863215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2763863215
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3690485105
Short name T709
Test name
Test status
Simulation time 44809467537 ps
CPU time 26.68 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 200680 kb
Host smart-1eefdf99-ce3d-468d-89ef-6cbf0538aa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690485105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3690485105
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.85461460
Short name T524
Test name
Test status
Simulation time 3081024030 ps
CPU time 4.42 seconds
Started Dec 27 12:38:18 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 200636 kb
Host smart-534635d4-2cca-46c6-805a-02eeab3c8254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85461460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.85461460
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1285841365
Short name T519
Test name
Test status
Simulation time 5663625801 ps
CPU time 7.57 seconds
Started Dec 27 12:38:35 PM PST 23
Finished Dec 27 12:38:51 PM PST 23
Peak memory 200680 kb
Host smart-6eee3417-41b6-4c6b-bb30-185d5abf0cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285841365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1285841365
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.684698942
Short name T310
Test name
Test status
Simulation time 385606258401 ps
CPU time 419.07 seconds
Started Dec 27 12:38:44 PM PST 23
Finished Dec 27 12:45:53 PM PST 23
Peak memory 200752 kb
Host smart-c0dbc34b-4d51-4712-981d-5067e1b40838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684698942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
684698942
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4020179641
Short name T641
Test name
Test status
Simulation time 340618910 ps
CPU time 1.4 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:38:26 PM PST 23
Peak memory 200528 kb
Host smart-021a032e-841e-4b15-bc17-396aba6d9a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020179641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4020179641
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3987581406
Short name T824
Test name
Test status
Simulation time 483069306601 ps
CPU time 593.86 seconds
Started Dec 27 12:37:05 PM PST 23
Finished Dec 27 12:47:22 PM PST 23
Peak memory 200768 kb
Host smart-8918f872-894a-4848-837f-28009b56750e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987581406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3987581406
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1610291436
Short name T836
Test name
Test status
Simulation time 171854336400 ps
CPU time 42.71 seconds
Started Dec 27 12:37:04 PM PST 23
Finished Dec 27 12:38:11 PM PST 23
Peak memory 200872 kb
Host smart-d2dfc42d-929e-427e-98e6-cc2e1361c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610291436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1610291436
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1872333260
Short name T200
Test name
Test status
Simulation time 319911448353 ps
CPU time 709.92 seconds
Started Dec 27 12:37:30 PM PST 23
Finished Dec 27 12:49:35 PM PST 23
Peak memory 200820 kb
Host smart-e493d306-d571-4032-870b-586363755fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872333260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1872333260
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2244490814
Short name T758
Test name
Test status
Simulation time 491058578320 ps
CPU time 1134.19 seconds
Started Dec 27 12:38:01 PM PST 23
Finished Dec 27 12:57:07 PM PST 23
Peak memory 200744 kb
Host smart-9edd7b0b-4c5d-4376-9750-81bc92437523
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244490814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2244490814
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2843454817
Short name T145
Test name
Test status
Simulation time 503519793438 ps
CPU time 143.93 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:40:01 PM PST 23
Peak memory 200824 kb
Host smart-781f5e60-19e3-4950-bb52-b851a5b55e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843454817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2843454817
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4116486582
Short name T565
Test name
Test status
Simulation time 165492007263 ps
CPU time 407.98 seconds
Started Dec 27 12:37:10 PM PST 23
Finished Dec 27 12:44:20 PM PST 23
Peak memory 200768 kb
Host smart-8ad28b36-3560-4fe2-af7d-34e6c5ece8ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116486582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4116486582
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4054246037
Short name T657
Test name
Test status
Simulation time 492393848487 ps
CPU time 1156.17 seconds
Started Dec 27 12:36:55 PM PST 23
Finished Dec 27 12:56:37 PM PST 23
Peak memory 200740 kb
Host smart-11771b3f-961c-4f31-8485-8456f802fc2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054246037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4054246037
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1681461893
Short name T458
Test name
Test status
Simulation time 166519298071 ps
CPU time 179.57 seconds
Started Dec 27 12:37:21 PM PST 23
Finished Dec 27 12:40:39 PM PST 23
Peak memory 200796 kb
Host smart-b5245c5d-491a-45e3-a864-94b11ccb8f59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681461893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1681461893
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.324728963
Short name T179
Test name
Test status
Simulation time 112075208767 ps
CPU time 319.85 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:43:48 PM PST 23
Peak memory 201100 kb
Host smart-d2e890f1-59cc-421e-b946-96b96622ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324728963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.324728963
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4083259172
Short name T430
Test name
Test status
Simulation time 28575691882 ps
CPU time 18.42 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:37:59 PM PST 23
Peak memory 200684 kb
Host smart-8e5dfa57-c76e-4e79-bd0b-030d7931d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083259172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4083259172
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1189152872
Short name T613
Test name
Test status
Simulation time 4329355773 ps
CPU time 4.93 seconds
Started Dec 27 12:36:59 PM PST 23
Finished Dec 27 12:37:28 PM PST 23
Peak memory 200592 kb
Host smart-09fd8ce9-782e-4842-bfc8-edf2800467a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189152872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1189152872
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1204936931
Short name T43
Test name
Test status
Simulation time 3974787950 ps
CPU time 1.81 seconds
Started Dec 27 12:37:12 PM PST 23
Finished Dec 27 12:37:36 PM PST 23
Peak memory 216028 kb
Host smart-b7b2137e-387d-4fcd-b37b-f83f1082274b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204936931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1204936931
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.481490157
Short name T530
Test name
Test status
Simulation time 5843098227 ps
CPU time 7.19 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:37:45 PM PST 23
Peak memory 200596 kb
Host smart-34469953-6e66-4820-bcdf-558cf559a267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481490157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.481490157
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2605305610
Short name T169
Test name
Test status
Simulation time 99825993450 ps
CPU time 345.65 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:43:15 PM PST 23
Peak memory 209356 kb
Host smart-1d1990df-6faf-4d9c-8535-4c77d2666369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605305610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2605305610
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2179444688
Short name T774
Test name
Test status
Simulation time 60030810807 ps
CPU time 105.29 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:39:20 PM PST 23
Peak memory 209064 kb
Host smart-cc0965e5-4328-415e-9ba8-870fecc7b2ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179444688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2179444688
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3775186950
Short name T480
Test name
Test status
Simulation time 487146669 ps
CPU time 1.03 seconds
Started Dec 27 12:39:55 PM PST 23
Finished Dec 27 12:40:44 PM PST 23
Peak memory 200376 kb
Host smart-3c30faa4-d95a-42c1-987b-12328c8e70f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775186950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3775186950
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3750559437
Short name T289
Test name
Test status
Simulation time 330658280328 ps
CPU time 363.85 seconds
Started Dec 27 12:40:12 PM PST 23
Finished Dec 27 12:47:07 PM PST 23
Peak memory 200780 kb
Host smart-779fb5f8-374b-4801-b43c-8c507ff6818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750559437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3750559437
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1016280437
Short name T720
Test name
Test status
Simulation time 326346489847 ps
CPU time 825.58 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:52:20 PM PST 23
Peak memory 200848 kb
Host smart-1926e1af-200d-46d7-9081-f76d63feb632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016280437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1016280437
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2585612479
Short name T719
Test name
Test status
Simulation time 168772093233 ps
CPU time 424.57 seconds
Started Dec 27 12:38:35 PM PST 23
Finished Dec 27 12:45:47 PM PST 23
Peak memory 200788 kb
Host smart-cfa22bb3-107e-49f2-96c1-2e2ed5009660
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585612479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2585612479
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3371604881
Short name T761
Test name
Test status
Simulation time 161176042499 ps
CPU time 95.21 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:40:32 PM PST 23
Peak memory 200808 kb
Host smart-cc1683b5-4b8f-4ee4-a700-00fd06d489b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371604881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3371604881
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3608347317
Short name T650
Test name
Test status
Simulation time 324854429488 ps
CPU time 141.92 seconds
Started Dec 27 12:39:54 PM PST 23
Finished Dec 27 12:43:03 PM PST 23
Peak memory 200676 kb
Host smart-3da547bf-83eb-41aa-b8c4-9c132e49bf53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608347317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3608347317
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.452230692
Short name T618
Test name
Test status
Simulation time 493098992313 ps
CPU time 1139.48 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:57:16 PM PST 23
Peak memory 200764 kb
Host smart-df13c213-ed56-46ab-b988-929deaba0fc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452230692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.452230692
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2643765420
Short name T708
Test name
Test status
Simulation time 497255375561 ps
CPU time 1141.96 seconds
Started Dec 27 12:39:55 PM PST 23
Finished Dec 27 12:59:44 PM PST 23
Peak memory 200656 kb
Host smart-013de03e-6a96-4100-9f29-13d0f13d7ef2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643765420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2643765420
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.63081631
Short name T474
Test name
Test status
Simulation time 82974074623 ps
CPU time 317.09 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:44:17 PM PST 23
Peak memory 201132 kb
Host smart-71d5d98b-844e-4118-8fd0-f693a2e3a6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63081631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.63081631
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3232178629
Short name T843
Test name
Test status
Simulation time 34154780508 ps
CPU time 39.3 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:39:13 PM PST 23
Peak memory 200560 kb
Host smart-60c2637c-accc-49db-b784-305d646bb2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232178629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3232178629
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.106009432
Short name T563
Test name
Test status
Simulation time 5235724270 ps
CPU time 3.56 seconds
Started Dec 27 12:40:09 PM PST 23
Finished Dec 27 12:41:03 PM PST 23
Peak memory 200564 kb
Host smart-0a9a97c1-b551-49aa-9465-00cf1088cadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106009432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.106009432
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2172314948
Short name T417
Test name
Test status
Simulation time 5794264623 ps
CPU time 3.3 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:38:50 PM PST 23
Peak memory 200580 kb
Host smart-90c7bfa7-4dd3-46a8-abe9-55d5c850016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172314948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2172314948
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.306860832
Short name T764
Test name
Test status
Simulation time 363559295078 ps
CPU time 370.4 seconds
Started Dec 27 12:38:18 PM PST 23
Finished Dec 27 12:44:37 PM PST 23
Peak memory 200776 kb
Host smart-d6956413-fa62-4bdc-970f-e4dcee4ee15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306860832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
306860832
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1668267999
Short name T608
Test name
Test status
Simulation time 104565719149 ps
CPU time 70.16 seconds
Started Dec 27 12:40:12 PM PST 23
Finished Dec 27 12:42:14 PM PST 23
Peak memory 209528 kb
Host smart-a402fffb-eb91-4412-834a-6f9ef00c06ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668267999 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1668267999
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3921942408
Short name T806
Test name
Test status
Simulation time 412637175 ps
CPU time 0.7 seconds
Started Dec 27 12:38:08 PM PST 23
Finished Dec 27 12:38:21 PM PST 23
Peak memory 200612 kb
Host smart-357b38b1-5e44-492e-9b00-48d55f3451d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921942408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3921942408
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2705977212
Short name T121
Test name
Test status
Simulation time 330589588860 ps
CPU time 62.67 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:39:16 PM PST 23
Peak memory 200572 kb
Host smart-5363365a-bf4e-4e77-aa51-a865d2218791
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705977212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2705977212
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1269751099
Short name T300
Test name
Test status
Simulation time 159735264945 ps
CPU time 355.62 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:44:28 PM PST 23
Peak memory 200844 kb
Host smart-efd1d81d-97a6-4837-a4c4-b08a9cfa2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269751099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1269751099
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1525606248
Short name T721
Test name
Test status
Simulation time 160764585293 ps
CPU time 104.25 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:39:56 PM PST 23
Peak memory 200936 kb
Host smart-186d14a9-4a5e-40a5-9b41-18a5a3a6283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525606248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1525606248
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1521715919
Short name T849
Test name
Test status
Simulation time 158348587131 ps
CPU time 271.45 seconds
Started Dec 27 12:38:18 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 200664 kb
Host smart-1b2253f0-0447-466c-b598-cf70944c097d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521715919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1521715919
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3355009092
Short name T159
Test name
Test status
Simulation time 497299615493 ps
CPU time 281.81 seconds
Started Dec 27 12:38:13 PM PST 23
Finished Dec 27 12:43:02 PM PST 23
Peak memory 200744 kb
Host smart-c4310a11-ad8b-42ec-8c8c-131fd6c319a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355009092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3355009092
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3796524495
Short name T581
Test name
Test status
Simulation time 324415445740 ps
CPU time 200.36 seconds
Started Dec 27 12:38:21 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 200604 kb
Host smart-e9e54322-5e13-4d92-83d7-20bb984dee6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796524495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3796524495
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1521366839
Short name T345
Test name
Test status
Simulation time 498942683295 ps
CPU time 1089.64 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:56:42 PM PST 23
Peak memory 200708 kb
Host smart-fb88ebfd-afdf-4db5-8434-8afe245d1809
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521366839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1521366839
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3335532032
Short name T693
Test name
Test status
Simulation time 489133445701 ps
CPU time 613.96 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:48:46 PM PST 23
Peak memory 200676 kb
Host smart-d72dc540-c33a-4356-82c7-87f3426c1efc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335532032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3335532032
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3725659584
Short name T859
Test name
Test status
Simulation time 132012217480 ps
CPU time 423.6 seconds
Started Dec 27 12:37:55 PM PST 23
Finished Dec 27 12:45:05 PM PST 23
Peak memory 201300 kb
Host smart-023f8e2d-bf61-47cd-a98d-da8ed347a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725659584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3725659584
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1618266803
Short name T504
Test name
Test status
Simulation time 29476358563 ps
CPU time 34.32 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:39:05 PM PST 23
Peak memory 200588 kb
Host smart-f0a975d9-57a0-45af-9d3d-e4a692b57b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618266803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1618266803
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1077681126
Short name T585
Test name
Test status
Simulation time 3106278568 ps
CPU time 2.56 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:38:14 PM PST 23
Peak memory 200644 kb
Host smart-c44450ff-0065-4ebc-9f1c-4cc6ead17346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077681126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1077681126
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.716922286
Short name T96
Test name
Test status
Simulation time 5671247690 ps
CPU time 14.9 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:38:46 PM PST 23
Peak memory 200608 kb
Host smart-b54669a6-ab7a-4277-992d-c872a6c13701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716922286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.716922286
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1629515516
Short name T740
Test name
Test status
Simulation time 178563703830 ps
CPU time 73.43 seconds
Started Dec 27 12:38:35 PM PST 23
Finished Dec 27 12:39:56 PM PST 23
Peak memory 200724 kb
Host smart-b152aca6-2935-46ea-8997-6b30af8832ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629515516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1629515516
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3319398477
Short name T723
Test name
Test status
Simulation time 231948496910 ps
CPU time 137.7 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:41:04 PM PST 23
Peak memory 209444 kb
Host smart-0ae7a985-4f32-4035-a053-e35ead8154d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319398477 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3319398477
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3143102366
Short name T431
Test name
Test status
Simulation time 475225532 ps
CPU time 0.81 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 200488 kb
Host smart-6e859a4f-07b7-4e53-b067-4c9370af2f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143102366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3143102366
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.4103977427
Short name T248
Test name
Test status
Simulation time 162159221310 ps
CPU time 88.79 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:39:38 PM PST 23
Peak memory 200784 kb
Host smart-8ec73b4a-6f30-4f33-90d7-a1979b19b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103977427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.4103977427
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2546047774
Short name T590
Test name
Test status
Simulation time 329212031978 ps
CPU time 634.15 seconds
Started Dec 27 12:38:40 PM PST 23
Finished Dec 27 12:49:24 PM PST 23
Peak memory 200740 kb
Host smart-3e5e19c9-adc8-4746-8d46-4db753e852e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546047774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2546047774
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1849139633
Short name T143
Test name
Test status
Simulation time 329050806293 ps
CPU time 129.01 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:40:57 PM PST 23
Peak memory 200772 kb
Host smart-581be737-cc10-45b9-9ad9-c249529a5c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849139633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1849139633
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3849113460
Short name T507
Test name
Test status
Simulation time 482078671904 ps
CPU time 234.49 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 200728 kb
Host smart-22f430d6-cdaf-49c8-a012-fe16666458ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849113460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3849113460
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3089809354
Short name T269
Test name
Test status
Simulation time 160635242521 ps
CPU time 96.93 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:40:00 PM PST 23
Peak memory 200816 kb
Host smart-4214c3e2-9989-417a-a0d3-9dcd1676847b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089809354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3089809354
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1128565555
Short name T813
Test name
Test status
Simulation time 164264260230 ps
CPU time 189.84 seconds
Started Dec 27 12:38:35 PM PST 23
Finished Dec 27 12:41:53 PM PST 23
Peak memory 200692 kb
Host smart-d49c5e81-e3dd-4f78-a0d9-7e4de4d942d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128565555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1128565555
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3175447020
Short name T570
Test name
Test status
Simulation time 65139091308 ps
CPU time 298.66 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:43:18 PM PST 23
Peak memory 201144 kb
Host smart-40ddcc37-7941-4c44-8506-0994ede7a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175447020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3175447020
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3676272812
Short name T551
Test name
Test status
Simulation time 26175203275 ps
CPU time 32.01 seconds
Started Dec 27 12:39:32 PM PST 23
Finished Dec 27 12:40:39 PM PST 23
Peak memory 199180 kb
Host smart-a8ddc47c-307c-4973-afb6-60632b803783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676272812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3676272812
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2564794798
Short name T683
Test name
Test status
Simulation time 3465878488 ps
CPU time 8.23 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:38:30 PM PST 23
Peak memory 200556 kb
Host smart-85693998-d2dc-4f7f-9483-553b68ebbbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564794798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2564794798
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1195443458
Short name T598
Test name
Test status
Simulation time 5995123627 ps
CPU time 7.12 seconds
Started Dec 27 12:37:59 PM PST 23
Finished Dec 27 12:38:16 PM PST 23
Peak memory 200492 kb
Host smart-7434404b-48bf-41f1-b202-887603aff675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195443458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1195443458
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2556706909
Short name T163
Test name
Test status
Simulation time 409719693422 ps
CPU time 1224.48 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:58:35 PM PST 23
Peak memory 209344 kb
Host smart-8ee196d6-b8d0-4f78-9a75-ade58550459c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556706909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2556706909
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3393445966
Short name T235
Test name
Test status
Simulation time 214416973374 ps
CPU time 76.6 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:39:49 PM PST 23
Peak memory 209120 kb
Host smart-4a73a10a-71ba-4dee-8ec3-5eb4d80db184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393445966 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3393445966
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2024710422
Short name T663
Test name
Test status
Simulation time 330005095 ps
CPU time 0.84 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:38:18 PM PST 23
Peak memory 200456 kb
Host smart-84a9508f-a8dc-4cf6-b3e8-8ee6817e49fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024710422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2024710422
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2773403328
Short name T856
Test name
Test status
Simulation time 332995942559 ps
CPU time 182.53 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:41:43 PM PST 23
Peak memory 200732 kb
Host smart-309e926c-caf1-4d85-a50d-e231a2041fe9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773403328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2773403328
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1393335289
Short name T294
Test name
Test status
Simulation time 489523966663 ps
CPU time 317.05 seconds
Started Dec 27 12:38:09 PM PST 23
Finished Dec 27 12:43:33 PM PST 23
Peak memory 200852 kb
Host smart-b7d7dab7-77f6-4df4-b809-d979c583150a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393335289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1393335289
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1914436283
Short name T228
Test name
Test status
Simulation time 167182364650 ps
CPU time 188.25 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:42:02 PM PST 23
Peak memory 200732 kb
Host smart-ea0e6f90-7f30-4e7c-964d-f93e40cdc73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914436283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1914436283
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3904897666
Short name T479
Test name
Test status
Simulation time 330739951686 ps
CPU time 200.1 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:42:26 PM PST 23
Peak memory 200852 kb
Host smart-803fe064-ee4b-481c-b4b6-91f04b10db65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904897666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3904897666
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2966825845
Short name T858
Test name
Test status
Simulation time 317619170874 ps
CPU time 153.4 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:41:15 PM PST 23
Peak memory 200824 kb
Host smart-fbd478cc-244d-424b-b655-b2fba52dc10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966825845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2966825845
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1285614879
Short name T869
Test name
Test status
Simulation time 168794635001 ps
CPU time 102.23 seconds
Started Dec 27 12:40:20 PM PST 23
Finished Dec 27 12:42:56 PM PST 23
Peak memory 200380 kb
Host smart-a8bb56a7-85d5-4f32-8584-0e94b9d57c09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285614879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1285614879
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2809645952
Short name T221
Test name
Test status
Simulation time 328573440277 ps
CPU time 312 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:43:43 PM PST 23
Peak memory 200888 kb
Host smart-a69fceda-9baf-4cff-b25b-90abdb82c8be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809645952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2809645952
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.205830057
Short name T436
Test name
Test status
Simulation time 490932570095 ps
CPU time 1129.43 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:57:11 PM PST 23
Peak memory 200740 kb
Host smart-22fcc76e-bef5-41c9-810a-911281b36aa3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205830057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.205830057
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3335209428
Short name T840
Test name
Test status
Simulation time 90915604806 ps
CPU time 375.23 seconds
Started Dec 27 12:38:58 PM PST 23
Finished Dec 27 12:45:30 PM PST 23
Peak memory 201196 kb
Host smart-b3b702ab-0c0c-47c5-afee-6ba0ca940a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335209428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3335209428
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2085549574
Short name T587
Test name
Test status
Simulation time 47550184777 ps
CPU time 107.61 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:40:03 PM PST 23
Peak memory 200580 kb
Host smart-78c94479-fdf6-4c5b-9edc-6a2574e6cb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085549574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2085549574
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.340558708
Short name T863
Test name
Test status
Simulation time 4641251508 ps
CPU time 3.32 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:38:45 PM PST 23
Peak memory 200568 kb
Host smart-f23878ab-fa49-47a5-ae54-8570314a002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340558708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.340558708
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2239047975
Short name T475
Test name
Test status
Simulation time 5719996150 ps
CPU time 7.56 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:38:28 PM PST 23
Peak memory 200672 kb
Host smart-1729cb47-dbb4-4520-85a3-485924102584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239047975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2239047975
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.995432685
Short name T122
Test name
Test status
Simulation time 61775183951 ps
CPU time 280.45 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:43:05 PM PST 23
Peak memory 209528 kb
Host smart-a0ce842a-cd7c-4b26-be1a-d9d6e2ca5233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995432685 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.995432685
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1305687046
Short name T868
Test name
Test status
Simulation time 340200787 ps
CPU time 0.78 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:38:12 PM PST 23
Peak memory 200564 kb
Host smart-03fb2715-4dc6-4d85-a710-19d53f0ae627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305687046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1305687046
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1409162116
Short name T290
Test name
Test status
Simulation time 316574229915 ps
CPU time 332.17 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:44:34 PM PST 23
Peak memory 200724 kb
Host smart-7594a05e-ff7c-4dca-85ea-6aa4a9f7d818
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409162116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1409162116
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4114752285
Short name T862
Test name
Test status
Simulation time 331847861013 ps
CPU time 209.92 seconds
Started Dec 27 12:38:44 PM PST 23
Finished Dec 27 12:42:24 PM PST 23
Peak memory 200828 kb
Host smart-3f9be942-7fb7-49a0-90c7-1c9af8954715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114752285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4114752285
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2135275206
Short name T303
Test name
Test status
Simulation time 164248051616 ps
CPU time 24.23 seconds
Started Dec 27 12:40:14 PM PST 23
Finished Dec 27 12:41:30 PM PST 23
Peak memory 200820 kb
Host smart-861bd786-cf0c-4ae3-903a-23bf988c2138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135275206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2135275206
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3002834785
Short name T604
Test name
Test status
Simulation time 163664017629 ps
CPU time 152.54 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:41:04 PM PST 23
Peak memory 200776 kb
Host smart-1870eca3-2eeb-4528-8fd5-b9a1d5934e23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002834785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3002834785
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.484900303
Short name T327
Test name
Test status
Simulation time 163613035720 ps
CPU time 122.95 seconds
Started Dec 27 12:40:12 PM PST 23
Finished Dec 27 12:43:07 PM PST 23
Peak memory 200712 kb
Host smart-7f2e44cc-6cb5-4994-af9a-c2c84906dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484900303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.484900303
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2563824169
Short name T626
Test name
Test status
Simulation time 503576834134 ps
CPU time 288.43 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:43:23 PM PST 23
Peak memory 200804 kb
Host smart-434e209e-aa6c-4559-9167-3992c3d96cb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563824169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2563824169
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.299994692
Short name T338
Test name
Test status
Simulation time 167745227031 ps
CPU time 368.75 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:44:18 PM PST 23
Peak memory 200800 kb
Host smart-45fb7d12-68dd-4ba0-b43a-4e31434bfa3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299994692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.299994692
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3477097160
Short name T775
Test name
Test status
Simulation time 326050494780 ps
CPU time 718.63 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:50:41 PM PST 23
Peak memory 200736 kb
Host smart-1e49fb85-abdc-4534-9b54-a2e3db88894a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477097160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3477097160
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.799834653
Short name T353
Test name
Test status
Simulation time 95715226859 ps
CPU time 462.06 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:45:58 PM PST 23
Peak memory 201268 kb
Host smart-f0982ebc-4ccc-4ef4-bcd9-614bbf51180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799834653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.799834653
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2590995828
Short name T412
Test name
Test status
Simulation time 21511535043 ps
CPU time 24.04 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:38:42 PM PST 23
Peak memory 200544 kb
Host smart-2bb0b2f9-8358-43bf-a04d-1f8779187df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590995828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2590995828
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2527888688
Short name T450
Test name
Test status
Simulation time 5169036819 ps
CPU time 13.24 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 200616 kb
Host smart-21fa8ef2-ddac-4cfb-a600-e81e7059f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527888688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2527888688
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.942074095
Short name T734
Test name
Test status
Simulation time 5872270657 ps
CPU time 10.37 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:38:51 PM PST 23
Peak memory 200528 kb
Host smart-154aedae-7985-4123-999a-351add0ed7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942074095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.942074095
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.4155961192
Short name T583
Test name
Test status
Simulation time 411588630183 ps
CPU time 1205.35 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:58:41 PM PST 23
Peak memory 201288 kb
Host smart-1efb7478-74f8-49b6-a5eb-7faabb2ced47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155961192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.4155961192
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3597898754
Short name T776
Test name
Test status
Simulation time 159181765490 ps
CPU time 337.29 seconds
Started Dec 27 12:38:45 PM PST 23
Finished Dec 27 12:44:32 PM PST 23
Peak memory 209804 kb
Host smart-eba35e59-6761-4be8-a3ce-ee599c0023c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597898754 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3597898754
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2547086050
Short name T575
Test name
Test status
Simulation time 331408946 ps
CPU time 1.27 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:38:34 PM PST 23
Peak memory 200480 kb
Host smart-0497cd73-5096-4927-952c-28c542d972ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547086050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2547086050
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4063626310
Short name T229
Test name
Test status
Simulation time 324813953156 ps
CPU time 186.19 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:41:28 PM PST 23
Peak memory 200912 kb
Host smart-32b94b5b-52f2-4dc5-b507-bc4dce6be4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063626310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4063626310
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2531152307
Short name T150
Test name
Test status
Simulation time 319519183670 ps
CPU time 142.71 seconds
Started Dec 27 12:38:43 PM PST 23
Finished Dec 27 12:41:15 PM PST 23
Peak memory 200764 kb
Host smart-db867ef8-8ad9-4c53-acb6-0f4c4fcc4603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531152307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2531152307
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.531045439
Short name T870
Test name
Test status
Simulation time 327249274717 ps
CPU time 807.75 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:52:14 PM PST 23
Peak memory 200860 kb
Host smart-6db4f47c-3da6-40ec-8d74-145021f99ba8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=531045439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.531045439
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3307684129
Short name T695
Test name
Test status
Simulation time 169760669182 ps
CPU time 195.3 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:41:56 PM PST 23
Peak memory 200816 kb
Host smart-4668fe44-44dd-41a7-aaf2-8d6cf9ed44ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307684129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3307684129
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2037763071
Short name T522
Test name
Test status
Simulation time 487778286494 ps
CPU time 300.1 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:43:32 PM PST 23
Peak memory 200804 kb
Host smart-a91b111e-209c-401f-a935-20ae0d2dbcfa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037763071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2037763071
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1035449119
Short name T111
Test name
Test status
Simulation time 333557968148 ps
CPU time 356 seconds
Started Dec 27 12:38:45 PM PST 23
Finished Dec 27 12:44:51 PM PST 23
Peak memory 200868 kb
Host smart-1dd767c2-b23f-4ea0-af7e-0ed374134e65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035449119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1035449119
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2642619244
Short name T601
Test name
Test status
Simulation time 162835649233 ps
CPU time 65.64 seconds
Started Dec 27 12:38:19 PM PST 23
Finished Dec 27 12:39:33 PM PST 23
Peak memory 200868 kb
Host smart-c3d52a2f-0172-4ca6-87b4-a7fd8b4ba7fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642619244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2642619244
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3769209293
Short name T182
Test name
Test status
Simulation time 106133996360 ps
CPU time 622.33 seconds
Started Dec 27 12:38:46 PM PST 23
Finished Dec 27 12:49:17 PM PST 23
Peak memory 201276 kb
Host smart-9611fc87-673e-426c-9bfd-b41bb39dccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769209293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3769209293
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1510902849
Short name T493
Test name
Test status
Simulation time 24288725075 ps
CPU time 15.98 seconds
Started Dec 27 12:40:13 PM PST 23
Finished Dec 27 12:41:21 PM PST 23
Peak memory 200568 kb
Host smart-7f28d507-7cc2-4365-8b56-3fea0919441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510902849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1510902849
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1771521073
Short name T413
Test name
Test status
Simulation time 5079876001 ps
CPU time 12.64 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:38:44 PM PST 23
Peak memory 200612 kb
Host smart-cbb3a755-f3d7-4a3c-8a2b-f95b374d1f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771521073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1771521073
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1168408609
Short name T423
Test name
Test status
Simulation time 5953746449 ps
CPU time 1.85 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:38:48 PM PST 23
Peak memory 200508 kb
Host smart-b42377be-614e-492f-8407-4e134ee173d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168408609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1168408609
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1175411781
Short name T167
Test name
Test status
Simulation time 209336793000 ps
CPU time 798.52 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:51:54 PM PST 23
Peak memory 201112 kb
Host smart-e9b8d843-7da7-4670-993d-4409a8be4f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175411781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1175411781
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2772832713
Short name T32
Test name
Test status
Simulation time 363842788297 ps
CPU time 442.94 seconds
Started Dec 27 12:39:29 PM PST 23
Finished Dec 27 12:47:25 PM PST 23
Peak memory 209192 kb
Host smart-0aa6c997-dcd7-4d38-a1e4-d8f7be949a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772832713 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2772832713
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1212617997
Short name T536
Test name
Test status
Simulation time 466076210 ps
CPU time 0.92 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:38:24 PM PST 23
Peak memory 200588 kb
Host smart-1c7739e7-a80b-4108-a6c2-f57a797cb507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212617997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1212617997
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1527893144
Short name T787
Test name
Test status
Simulation time 484201663635 ps
CPU time 125.87 seconds
Started Dec 27 12:38:52 PM PST 23
Finished Dec 27 12:41:12 PM PST 23
Peak memory 200760 kb
Host smart-c0d05cb2-6566-491f-ac26-4304eb3c7811
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527893144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1527893144
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2874130976
Short name T298
Test name
Test status
Simulation time 163532575755 ps
CPU time 198.6 seconds
Started Dec 27 12:38:24 PM PST 23
Finished Dec 27 12:41:50 PM PST 23
Peak memory 200852 kb
Host smart-f08bd037-64ed-44ee-b00b-51b3f10195ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874130976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2874130976
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.734991897
Short name T260
Test name
Test status
Simulation time 167120646825 ps
CPU time 379.84 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:44:55 PM PST 23
Peak memory 200812 kb
Host smart-8d9f3901-0189-473c-877f-9506f268e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734991897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.734991897
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.103713343
Short name T45
Test name
Test status
Simulation time 326006531728 ps
CPU time 169.62 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:41:29 PM PST 23
Peak memory 200856 kb
Host smart-a929e3df-d79e-41fd-b127-0f6d78fd01ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=103713343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.103713343
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3903348566
Short name T112
Test name
Test status
Simulation time 488691566959 ps
CPU time 1038.89 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:55:58 PM PST 23
Peak memory 200736 kb
Host smart-4ef780c5-c7da-4479-b429-25b27bc35d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903348566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3903348566
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.493208214
Short name T554
Test name
Test status
Simulation time 328924860597 ps
CPU time 219.93 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:42:24 PM PST 23
Peak memory 200824 kb
Host smart-9d237ecb-0cde-4788-bb6c-c46eff4e64ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=493208214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.493208214
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1515098707
Short name T20
Test name
Test status
Simulation time 165983958332 ps
CPU time 95.2 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:40:16 PM PST 23
Peak memory 200740 kb
Host smart-b88e286e-a5f4-4e80-9db5-015681ad56a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515098707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1515098707
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3931821227
Short name T742
Test name
Test status
Simulation time 161890421359 ps
CPU time 394.43 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:45:39 PM PST 23
Peak memory 200824 kb
Host smart-486be204-b9fe-4d6c-981a-b060d52ea69a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931821227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3931821227
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2635935139
Short name T677
Test name
Test status
Simulation time 63257627007 ps
CPU time 238.7 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:42:28 PM PST 23
Peak memory 201148 kb
Host smart-82394223-edc2-45d9-93c2-0825b5c9c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635935139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2635935139
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1256147434
Short name T750
Test name
Test status
Simulation time 28714481233 ps
CPU time 65.27 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:39:38 PM PST 23
Peak memory 200676 kb
Host smart-4c648707-7061-4e1c-8c9e-5b23f58bf367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256147434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1256147434
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.342354530
Short name T865
Test name
Test status
Simulation time 3514438163 ps
CPU time 8.5 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:38:41 PM PST 23
Peak memory 200624 kb
Host smart-e99a9cbb-02cb-4d5c-bc58-2238ee56b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342354530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.342354530
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1533604966
Short name T558
Test name
Test status
Simulation time 5849249624 ps
CPU time 15.01 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:38:51 PM PST 23
Peak memory 200620 kb
Host smart-d574da33-3a26-4ee0-9aec-592ab4b1b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533604966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1533604966
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.437374629
Short name T853
Test name
Test status
Simulation time 66855330066 ps
CPU time 148.81 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:41:42 PM PST 23
Peak memory 209012 kb
Host smart-2d4209d4-c411-4b78-a6c1-8288aa114832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437374629 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.437374629
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3844690515
Short name T595
Test name
Test status
Simulation time 448869609 ps
CPU time 0.85 seconds
Started Dec 27 12:38:35 PM PST 23
Finished Dec 27 12:38:44 PM PST 23
Peak memory 200552 kb
Host smart-c9994efd-4cbb-47b2-a703-d096b23ed0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844690515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3844690515
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.35206728
Short name T619
Test name
Test status
Simulation time 163649723051 ps
CPU time 186.41 seconds
Started Dec 27 12:38:45 PM PST 23
Finished Dec 27 12:42:01 PM PST 23
Peak memory 200804 kb
Host smart-0869d02b-1596-4792-9b02-61c9b5ba234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35206728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.35206728
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1690000778
Short name T854
Test name
Test status
Simulation time 496459683491 ps
CPU time 1083.17 seconds
Started Dec 27 12:38:20 PM PST 23
Finished Dec 27 12:56:32 PM PST 23
Peak memory 200816 kb
Host smart-3f62d645-5b56-4504-8b29-78ba1efcb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690000778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1690000778
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.19193625
Short name T505
Test name
Test status
Simulation time 496120167790 ps
CPU time 290.22 seconds
Started Dec 27 12:38:31 PM PST 23
Finished Dec 27 12:43:35 PM PST 23
Peak memory 200816 kb
Host smart-3d61a1d4-3002-4e33-9e97-a342d39b8efd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=19193625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt
_fixed.19193625
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.653736208
Short name T770
Test name
Test status
Simulation time 324889288099 ps
CPU time 796.12 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:52:00 PM PST 23
Peak memory 200772 kb
Host smart-d88bc6ea-9c17-491f-b12b-6ba2fb9983da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653736208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.653736208
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1595353441
Short name T815
Test name
Test status
Simulation time 321912357427 ps
CPU time 680.7 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:50:24 PM PST 23
Peak memory 200792 kb
Host smart-80385092-c035-4b80-980a-5805554ef405
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595353441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1595353441
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1082062181
Short name T49
Test name
Test status
Simulation time 324222095750 ps
CPU time 795.32 seconds
Started Dec 27 12:38:29 PM PST 23
Finished Dec 27 12:51:51 PM PST 23
Peak memory 200864 kb
Host smart-e0e68ed2-a81f-410a-827b-40606db04732
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082062181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1082062181
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3785185570
Short name T855
Test name
Test status
Simulation time 112205960660 ps
CPU time 422.43 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:46:10 PM PST 23
Peak memory 201256 kb
Host smart-56f103e2-9dfb-4585-aab5-37bdfca69f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785185570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3785185570
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3533884287
Short name T426
Test name
Test status
Simulation time 27336951121 ps
CPU time 68.97 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:39:56 PM PST 23
Peak memory 200560 kb
Host smart-71cf3689-0f8b-46e7-b95c-44b01ab9e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533884287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3533884287
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2356122632
Short name T492
Test name
Test status
Simulation time 4999523081 ps
CPU time 6.92 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:38:47 PM PST 23
Peak memory 200588 kb
Host smart-a368fa41-ffc6-4e3b-9651-a2d2a344ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356122632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2356122632
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2183291355
Short name T464
Test name
Test status
Simulation time 5774919374 ps
CPU time 3.94 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:39:09 PM PST 23
Peak memory 200584 kb
Host smart-4a4e88d7-47b7-441a-84ab-a62b98aa7dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183291355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2183291355
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.930006023
Short name T253
Test name
Test status
Simulation time 243985222071 ps
CPU time 367.24 seconds
Started Dec 27 12:38:33 PM PST 23
Finished Dec 27 12:44:49 PM PST 23
Peak memory 209428 kb
Host smart-e118d14e-caf4-481d-a039-b73d068d8dc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930006023 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.930006023
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1337132518
Short name T782
Test name
Test status
Simulation time 287069525 ps
CPU time 1.19 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:38:58 PM PST 23
Peak memory 200592 kb
Host smart-a9904f0c-c75d-4e3e-80c5-0c7e2800f17b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337132518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1337132518
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.626580721
Short name T113
Test name
Test status
Simulation time 328614972710 ps
CPU time 681.79 seconds
Started Dec 27 12:38:19 PM PST 23
Finished Dec 27 12:49:49 PM PST 23
Peak memory 200740 kb
Host smart-0bda9d03-eb6f-4496-98a4-faf4f25abdee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626580721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.626580721
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3029764294
Short name T831
Test name
Test status
Simulation time 327636274186 ps
CPU time 387.24 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:44:52 PM PST 23
Peak memory 200800 kb
Host smart-1f7ef5f9-b25d-4f95-985f-33f849879717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029764294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3029764294
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2873950073
Short name T743
Test name
Test status
Simulation time 327149954034 ps
CPU time 747.58 seconds
Started Dec 27 12:38:14 PM PST 23
Finished Dec 27 12:50:50 PM PST 23
Peak memory 200788 kb
Host smart-77140681-aa87-407a-bc82-58d0f8ffbdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873950073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2873950073
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2509497674
Short name T411
Test name
Test status
Simulation time 162193154579 ps
CPU time 410.47 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:45:25 PM PST 23
Peak memory 200796 kb
Host smart-aadc0552-33b0-4a2f-8ab7-95749da08017
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509497674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2509497674
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2665345132
Short name T818
Test name
Test status
Simulation time 501835242810 ps
CPU time 508.06 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:47:15 PM PST 23
Peak memory 200736 kb
Host smart-15e46fe2-ef3f-43a7-8b59-873a24f3e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665345132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2665345132
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1471113295
Short name T453
Test name
Test status
Simulation time 162484856219 ps
CPU time 384.58 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:45:11 PM PST 23
Peak memory 200748 kb
Host smart-2c952c1e-69ef-4656-829c-13c68541fb92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471113295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1471113295
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1924445438
Short name T208
Test name
Test status
Simulation time 348055649186 ps
CPU time 423.56 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:45:44 PM PST 23
Peak memory 200716 kb
Host smart-42a9e1e3-2dab-43bc-8653-fd4100e68e5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924445438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1924445438
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1508338288
Short name T772
Test name
Test status
Simulation time 494668765533 ps
CPU time 257.58 seconds
Started Dec 27 12:39:01 PM PST 23
Finished Dec 27 12:43:35 PM PST 23
Peak memory 200700 kb
Host smart-90fb3178-3920-41a7-85a1-1d2badc35961
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508338288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1508338288
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.477285518
Short name T605
Test name
Test status
Simulation time 98159114927 ps
CPU time 307.07 seconds
Started Dec 27 12:38:41 PM PST 23
Finished Dec 27 12:43:58 PM PST 23
Peak memory 201244 kb
Host smart-099b14b5-9a46-48a3-a8a8-48465bea9433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477285518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.477285518
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3526017463
Short name T438
Test name
Test status
Simulation time 38288878350 ps
CPU time 25.17 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:39:38 PM PST 23
Peak memory 200584 kb
Host smart-10a4ac96-cb66-4e34-8219-fd536f270e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526017463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3526017463
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1654595059
Short name T454
Test name
Test status
Simulation time 4867662705 ps
CPU time 3.61 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 200544 kb
Host smart-58a1573b-13b1-41f5-9b90-a0fde2c4fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654595059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1654595059
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1345253033
Short name T701
Test name
Test status
Simulation time 5874241622 ps
CPU time 7.56 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:38:54 PM PST 23
Peak memory 200592 kb
Host smart-eb1b8758-6c8b-47db-8a3d-2a558a1d4834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345253033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1345253033
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.745988319
Short name T808
Test name
Test status
Simulation time 118079570424 ps
CPU time 41.43 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:39:29 PM PST 23
Peak memory 200868 kb
Host smart-d0bd7139-b163-4ed1-8c74-b838a6aa08d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745988319 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.745988319
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3043211253
Short name T718
Test name
Test status
Simulation time 482482951 ps
CPU time 0.87 seconds
Started Dec 27 12:38:31 PM PST 23
Finished Dec 27 12:38:40 PM PST 23
Peak memory 200492 kb
Host smart-4c219d5f-e548-4bb1-ac1e-a9407aa514d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043211253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3043211253
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4140146811
Short name T293
Test name
Test status
Simulation time 332299097172 ps
CPU time 343 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:44:52 PM PST 23
Peak memory 200824 kb
Host smart-8221ecd2-4c48-486d-a77c-ed9e5b7e4ec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140146811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4140146811
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3372439652
Short name T240
Test name
Test status
Simulation time 492413624270 ps
CPU time 548.65 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:48:08 PM PST 23
Peak memory 200772 kb
Host smart-3d7a4431-4646-4b13-86e3-466dc491769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372439652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3372439652
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2779219372
Short name T627
Test name
Test status
Simulation time 333289375133 ps
CPU time 125.27 seconds
Started Dec 27 12:38:15 PM PST 23
Finished Dec 27 12:40:32 PM PST 23
Peak memory 200784 kb
Host smart-d53c4408-a65e-4391-a88d-cef045213bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779219372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2779219372
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2728292028
Short name T777
Test name
Test status
Simulation time 162232505585 ps
CPU time 196.18 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:41:41 PM PST 23
Peak memory 200736 kb
Host smart-1226007b-164a-4135-bdba-e8ddc5bcf750
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728292028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2728292028
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.4112811361
Short name T797
Test name
Test status
Simulation time 162404647507 ps
CPU time 348.73 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:44:57 PM PST 23
Peak memory 200832 kb
Host smart-21f1acc9-9a1b-49ad-b594-7b764bf9f0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112811361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.4112811361
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2393611307
Short name T432
Test name
Test status
Simulation time 337656236326 ps
CPU time 770.7 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:51:23 PM PST 23
Peak memory 200728 kb
Host smart-17f53ac1-ba58-4558-8a35-c0715a75140f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393611307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2393611307
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1529906096
Short name T117
Test name
Test status
Simulation time 330785281403 ps
CPU time 554.22 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:47:48 PM PST 23
Peak memory 200820 kb
Host smart-8b4a2c21-56d7-4061-a869-1d2c9845305b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529906096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1529906096
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2664280888
Short name T622
Test name
Test status
Simulation time 166400761712 ps
CPU time 105.34 seconds
Started Dec 27 12:38:44 PM PST 23
Finished Dec 27 12:40:39 PM PST 23
Peak memory 200716 kb
Host smart-546afdb1-9cdb-4d1f-afd2-06015d82cb34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664280888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2664280888
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2924165416
Short name T647
Test name
Test status
Simulation time 91919525559 ps
CPU time 343.6 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:43:59 PM PST 23
Peak memory 201208 kb
Host smart-196a45aa-1219-4f66-ad43-7386121aaf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924165416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2924165416
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2669628649
Short name T47
Test name
Test status
Simulation time 27884106084 ps
CPU time 65.34 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:39:52 PM PST 23
Peak memory 200576 kb
Host smart-c799ed00-0362-414f-be0b-f96d20b8ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669628649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2669628649
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.452976673
Short name T550
Test name
Test status
Simulation time 3450703716 ps
CPU time 4.92 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:39:07 PM PST 23
Peak memory 200660 kb
Host smart-e79d0af2-482f-48b7-b321-ff152644957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452976673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.452976673
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.336882593
Short name T517
Test name
Test status
Simulation time 5815019144 ps
CPU time 4.39 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:38:50 PM PST 23
Peak memory 200660 kb
Host smart-8333a9b9-82c5-430b-bfda-0bdca7c2ed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336882593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.336882593
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3583384529
Short name T749
Test name
Test status
Simulation time 63724440952 ps
CPU time 132.71 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:40:55 PM PST 23
Peak memory 209480 kb
Host smart-50f7b747-c484-4015-b675-20a26f952d4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583384529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3583384529
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1167873778
Short name T768
Test name
Test status
Simulation time 559155849 ps
CPU time 0.96 seconds
Started Dec 27 12:37:08 PM PST 23
Finished Dec 27 12:37:32 PM PST 23
Peak memory 200536 kb
Host smart-d0c1dc1f-de4c-4073-938c-4ed9afae978e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167873778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1167873778
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.319332556
Short name T827
Test name
Test status
Simulation time 169207819835 ps
CPU time 103.45 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:39:15 PM PST 23
Peak memory 200768 kb
Host smart-4d6c104a-ea85-44a8-a6dd-a835b8f75d28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319332556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.319332556
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1218646944
Short name T100
Test name
Test status
Simulation time 166002154374 ps
CPU time 360.65 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:44:07 PM PST 23
Peak memory 200808 kb
Host smart-a58d7c86-6317-4aa1-be5f-80309c56a7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218646944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1218646944
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1227566706
Short name T851
Test name
Test status
Simulation time 326106307667 ps
CPU time 123.31 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:39:35 PM PST 23
Peak memory 200776 kb
Host smart-b8042a4a-b978-4174-893b-c4f0b09a800b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227566706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1227566706
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.84846792
Short name T712
Test name
Test status
Simulation time 163722921273 ps
CPU time 368.92 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:44:16 PM PST 23
Peak memory 200792 kb
Host smart-f76c83b1-911c-424f-8302-fbd3e84885f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=84846792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed.84846792
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3588584700
Short name T220
Test name
Test status
Simulation time 170183666840 ps
CPU time 107.35 seconds
Started Dec 27 12:37:15 PM PST 23
Finished Dec 27 12:39:23 PM PST 23
Peak memory 200752 kb
Host smart-a130c3e4-9b2c-4d2c-acab-d37aa7d302bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588584700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3588584700
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2693285491
Short name T839
Test name
Test status
Simulation time 325084261651 ps
CPU time 160.01 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:40:22 PM PST 23
Peak memory 200748 kb
Host smart-6e74ef9d-8476-4100-adaf-bb32eff5ee81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693285491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2693285491
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1306977266
Short name T97
Test name
Test status
Simulation time 91718133275 ps
CPU time 368.08 seconds
Started Dec 27 12:37:31 PM PST 23
Finished Dec 27 12:43:54 PM PST 23
Peak memory 201248 kb
Host smart-21eed4e9-19c4-4854-84c1-2463202b1a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306977266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1306977266
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.285528660
Short name T531
Test name
Test status
Simulation time 38815253680 ps
CPU time 90.09 seconds
Started Dec 27 12:37:57 PM PST 23
Finished Dec 27 12:39:37 PM PST 23
Peak memory 200676 kb
Host smart-9f205324-4c2d-492f-8859-ef9781fe5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285528660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.285528660
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1655895119
Short name T593
Test name
Test status
Simulation time 3353847138 ps
CPU time 7.31 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 200636 kb
Host smart-2f72fbcf-51d3-4ffa-95ca-fc1b59c23c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655895119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1655895119
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1448992260
Short name T40
Test name
Test status
Simulation time 3809692604 ps
CPU time 9.6 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:38:26 PM PST 23
Peak memory 216004 kb
Host smart-ad593f1d-0096-46f4-a8e0-24caf934d690
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448992260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1448992260
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1284177508
Short name T753
Test name
Test status
Simulation time 5761952594 ps
CPU time 14.69 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:37:53 PM PST 23
Peak memory 200528 kb
Host smart-12d49524-0630-4a32-8413-dff473d24c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284177508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1284177508
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1631580535
Short name T744
Test name
Test status
Simulation time 366284179385 ps
CPU time 77.85 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:38:57 PM PST 23
Peak memory 200804 kb
Host smart-5199246c-9675-4a08-99de-4d82f09aa8d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631580535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1631580535
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.790924295
Short name T781
Test name
Test status
Simulation time 186937184110 ps
CPU time 45.8 seconds
Started Dec 27 12:37:34 PM PST 23
Finished Dec 27 12:38:33 PM PST 23
Peak memory 208976 kb
Host smart-ef174929-f18e-4736-a526-c853905ab6fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790924295 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.790924295
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3440919676
Short name T703
Test name
Test status
Simulation time 418753414 ps
CPU time 1.23 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:39:15 PM PST 23
Peak memory 200556 kb
Host smart-a1eb9177-b60d-411e-a603-316917a8a7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440919676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3440919676
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3999570353
Short name T214
Test name
Test status
Simulation time 158559947457 ps
CPU time 94.02 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:40:07 PM PST 23
Peak memory 200740 kb
Host smart-b8156dfc-78d5-43a3-a948-0f7f1081d328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999570353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3999570353
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3066243407
Short name T739
Test name
Test status
Simulation time 328040577520 ps
CPU time 709.03 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:50:35 PM PST 23
Peak memory 200720 kb
Host smart-e02a2137-815c-41ff-9fe0-834d5470da26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066243407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3066243407
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2385779398
Short name T104
Test name
Test status
Simulation time 323708607741 ps
CPU time 399.95 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:45:17 PM PST 23
Peak memory 200772 kb
Host smart-809b7757-1f62-42e0-a619-38c3a186371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385779398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2385779398
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1886341190
Short name T461
Test name
Test status
Simulation time 159889342139 ps
CPU time 32.42 seconds
Started Dec 27 12:38:26 PM PST 23
Finished Dec 27 12:39:05 PM PST 23
Peak memory 200816 kb
Host smart-5d1c09a8-8530-492d-9cc7-6426131e9abe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886341190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1886341190
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3313683637
Short name T644
Test name
Test status
Simulation time 329270370961 ps
CPU time 704.05 seconds
Started Dec 27 12:38:31 PM PST 23
Finished Dec 27 12:50:23 PM PST 23
Peak memory 200784 kb
Host smart-ef8d4543-6a6b-4cbe-a962-f5c88fc72c0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313683637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3313683637
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.492260599
Short name T484
Test name
Test status
Simulation time 491802382409 ps
CPU time 1134.59 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:57:40 PM PST 23
Peak memory 200748 kb
Host smart-be8b4f3d-82ea-4d95-a187-e0ea1eee6469
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492260599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.492260599
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.691399588
Short name T177
Test name
Test status
Simulation time 67832968268 ps
CPU time 274.32 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:43:31 PM PST 23
Peak memory 201148 kb
Host smart-5de8695c-c2ee-4499-ad8e-70711e058661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691399588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.691399588
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2639896676
Short name T562
Test name
Test status
Simulation time 38886111953 ps
CPU time 23.98 seconds
Started Dec 27 12:38:56 PM PST 23
Finished Dec 27 12:39:35 PM PST 23
Peak memory 200688 kb
Host smart-7c1fba58-0943-41d6-9e23-f2f662d79d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639896676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2639896676
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1724011585
Short name T549
Test name
Test status
Simulation time 5244510804 ps
CPU time 12.97 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:39:00 PM PST 23
Peak memory 200636 kb
Host smart-3d3454e9-8053-4387-af33-d3e3b7e72bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724011585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1724011585
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1808631604
Short name T759
Test name
Test status
Simulation time 5747177957 ps
CPU time 14.11 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:39:10 PM PST 23
Peak memory 200656 kb
Host smart-433e071a-05f7-46a1-b63c-32e460d474c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808631604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1808631604
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3782753928
Short name T351
Test name
Test status
Simulation time 164777048584 ps
CPU time 447.21 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:46:07 PM PST 23
Peak memory 201192 kb
Host smart-3981fddc-02c3-4450-bba3-49507ac43ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782753928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3782753928
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3439128563
Short name T34
Test name
Test status
Simulation time 36588597739 ps
CPU time 88.59 seconds
Started Dec 27 12:38:43 PM PST 23
Finished Dec 27 12:40:22 PM PST 23
Peak memory 209320 kb
Host smart-4b38914e-15b6-431b-a517-4b4d69f54db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439128563 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3439128563
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2174244355
Short name T755
Test name
Test status
Simulation time 473331144 ps
CPU time 0.89 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:39:13 PM PST 23
Peak memory 200508 kb
Host smart-f9f1bb5d-b7ba-48a1-b1b3-35a686494b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174244355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2174244355
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1355707956
Short name T280
Test name
Test status
Simulation time 166473778407 ps
CPU time 81.45 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:39:46 PM PST 23
Peak memory 200784 kb
Host smart-2572cdae-7427-449b-af1d-7e222f3493a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355707956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1355707956
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2254344731
Short name T50
Test name
Test status
Simulation time 323192270027 ps
CPU time 389.75 seconds
Started Dec 27 12:38:28 PM PST 23
Finished Dec 27 12:45:05 PM PST 23
Peak memory 200828 kb
Host smart-b393e178-32ec-4f3d-bc19-127ecfc6eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254344731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2254344731
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.175446744
Short name T713
Test name
Test status
Simulation time 322273593989 ps
CPU time 176.28 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:41:38 PM PST 23
Peak memory 200648 kb
Host smart-6c4caf28-7f84-4967-83e2-455368d82103
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=175446744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.175446744
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1937991431
Short name T599
Test name
Test status
Simulation time 318216703058 ps
CPU time 792.38 seconds
Started Dec 27 12:39:11 PM PST 23
Finished Dec 27 12:52:48 PM PST 23
Peak memory 200780 kb
Host smart-890ed98c-247d-4dce-aa80-4119c75dc316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937991431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1937991431
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1787946154
Short name T653
Test name
Test status
Simulation time 165592940722 ps
CPU time 91.3 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:40:20 PM PST 23
Peak memory 200712 kb
Host smart-1bfb6756-ddc3-441f-970d-9e6ebfc81b5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787946154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1787946154
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2521133844
Short name T132
Test name
Test status
Simulation time 409216212618 ps
CPU time 207.54 seconds
Started Dec 27 12:38:55 PM PST 23
Finished Dec 27 12:42:38 PM PST 23
Peak memory 200824 kb
Host smart-8c5fe21a-1dca-4fea-b75b-12f22b69a9b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521133844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2521133844
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2423463441
Short name T707
Test name
Test status
Simulation time 164944093412 ps
CPU time 382.77 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:45:20 PM PST 23
Peak memory 200612 kb
Host smart-2a3c5032-65a6-4806-8e9f-82e7d59031dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423463441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2423463441
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2747778141
Short name T349
Test name
Test status
Simulation time 99233919680 ps
CPU time 326.69 seconds
Started Dec 27 12:39:14 PM PST 23
Finished Dec 27 12:45:06 PM PST 23
Peak memory 201260 kb
Host smart-e298ad9f-fe7b-486c-a390-c8e86ed84bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747778141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2747778141
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2770717271
Short name T539
Test name
Test status
Simulation time 38536372588 ps
CPU time 13.75 seconds
Started Dec 27 12:38:55 PM PST 23
Finished Dec 27 12:39:24 PM PST 23
Peak memory 200600 kb
Host smart-9ec317ac-8c52-4cb8-a860-cf6435114695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770717271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2770717271
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.890967279
Short name T415
Test name
Test status
Simulation time 5580478714 ps
CPU time 1.42 seconds
Started Dec 27 12:38:53 PM PST 23
Finished Dec 27 12:39:09 PM PST 23
Peak memory 200672 kb
Host smart-cb006f30-757e-4c27-b6a8-6c5b00969b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890967279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.890967279
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4285396588
Short name T645
Test name
Test status
Simulation time 5867798850 ps
CPU time 7.46 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:38:54 PM PST 23
Peak memory 200604 kb
Host smart-bdb98fcc-038e-4c23-a275-66fbb7ef60bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285396588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4285396588
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2757167301
Short name T236
Test name
Test status
Simulation time 164833685795 ps
CPU time 379.49 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:44:50 PM PST 23
Peak memory 200796 kb
Host smart-99572b62-45f6-4aa8-8ec4-9f00e5ac9942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757167301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2757167301
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1084880557
Short name T160
Test name
Test status
Simulation time 53255559540 ps
CPU time 55.61 seconds
Started Dec 27 12:38:36 PM PST 23
Finished Dec 27 12:39:41 PM PST 23
Peak memory 211088 kb
Host smart-160d944a-fb79-4725-a7cd-0e7d89ca525f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084880557 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1084880557
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2832137609
Short name T584
Test name
Test status
Simulation time 487640601 ps
CPU time 0.77 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:39:02 PM PST 23
Peak memory 200552 kb
Host smart-3140e73f-4c12-4666-ae4e-bb9f2836f8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832137609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2832137609
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.564784225
Short name T503
Test name
Test status
Simulation time 164720032466 ps
CPU time 241.84 seconds
Started Dec 27 12:40:47 PM PST 23
Finished Dec 27 12:45:51 PM PST 23
Peak memory 200536 kb
Host smart-c5b70261-6126-4040-9664-d4ea4ee2e15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564784225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.564784225
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3576071028
Short name T809
Test name
Test status
Simulation time 483602926896 ps
CPU time 313.84 seconds
Started Dec 27 12:38:44 PM PST 23
Finished Dec 27 12:44:07 PM PST 23
Peak memory 200788 kb
Host smart-7238ff6c-6455-4e79-8b84-3e791f967764
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576071028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3576071028
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.179034562
Short name T224
Test name
Test status
Simulation time 493857016124 ps
CPU time 298.79 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:44:02 PM PST 23
Peak memory 200868 kb
Host smart-7465012a-dfa1-48ef-8c00-9dcf28021dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179034562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.179034562
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1938920866
Short name T848
Test name
Test status
Simulation time 320609283086 ps
CPU time 165.3 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:41:51 PM PST 23
Peak memory 200728 kb
Host smart-b47a10bf-8489-48be-bb11-38a06512880b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938920866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1938920866
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3579810412
Short name T144
Test name
Test status
Simulation time 500126055596 ps
CPU time 165.26 seconds
Started Dec 27 12:39:41 PM PST 23
Finished Dec 27 12:43:04 PM PST 23
Peak memory 200868 kb
Host smart-e76eedc3-4710-4f92-a2d5-0f216a80344a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579810412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3579810412
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3698586154
Short name T520
Test name
Test status
Simulation time 315578513187 ps
CPU time 710.19 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:51:00 PM PST 23
Peak memory 200724 kb
Host smart-2e78b5a5-7c4f-4de4-8770-900bfd95445a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698586154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3698586154
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1036626347
Short name T543
Test name
Test status
Simulation time 111725872928 ps
CPU time 574.16 seconds
Started Dec 27 12:39:39 PM PST 23
Finished Dec 27 12:49:52 PM PST 23
Peak memory 199780 kb
Host smart-955cf93c-5634-4f82-a443-8b181f58b0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036626347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1036626347
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2156641212
Short name T534
Test name
Test status
Simulation time 24565970958 ps
CPU time 13.32 seconds
Started Dec 27 12:40:30 PM PST 23
Finished Dec 27 12:41:40 PM PST 23
Peak memory 200320 kb
Host smart-6ff90555-038c-4728-bbef-daec79f05eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156641212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2156641212
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3571444712
Short name T607
Test name
Test status
Simulation time 5476065704 ps
CPU time 14.1 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:39:11 PM PST 23
Peak memory 200584 kb
Host smart-942e382b-2bea-4bb9-ba0e-ab958ca58662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571444712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3571444712
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3710840903
Short name T533
Test name
Test status
Simulation time 5741680848 ps
CPU time 3.98 seconds
Started Dec 27 12:39:13 PM PST 23
Finished Dec 27 12:39:42 PM PST 23
Peak memory 200668 kb
Host smart-5a04b71e-d355-4e7a-9ff4-abf091de6567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710840903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3710840903
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1113107067
Short name T225
Test name
Test status
Simulation time 829001821156 ps
CPU time 1029.69 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:56:18 PM PST 23
Peak memory 200636 kb
Host smart-c5b69b8e-5183-463b-8e53-f93957d052ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113107067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1113107067
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4030520498
Short name T671
Test name
Test status
Simulation time 434681310 ps
CPU time 0.82 seconds
Started Dec 27 12:39:29 PM PST 23
Finished Dec 27 12:40:01 PM PST 23
Peak memory 200560 kb
Host smart-a82e144f-497e-464a-8fe0-633a8da0ec91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030520498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4030520498
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.128543123
Short name T130
Test name
Test status
Simulation time 319253931025 ps
CPU time 772.25 seconds
Started Dec 27 12:40:35 PM PST 23
Finished Dec 27 12:54:26 PM PST 23
Peak memory 200564 kb
Host smart-14db2ebb-e178-44d1-8ed7-9586b39211cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128543123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.128543123
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2634613107
Short name T751
Test name
Test status
Simulation time 330650345240 ps
CPU time 775.11 seconds
Started Dec 27 12:39:03 PM PST 23
Finished Dec 27 12:52:14 PM PST 23
Peak memory 200940 kb
Host smart-1728e623-9287-403a-b2b8-81e47a2066c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634613107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2634613107
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1977000726
Short name T790
Test name
Test status
Simulation time 334442401132 ps
CPU time 823.83 seconds
Started Dec 27 12:38:37 PM PST 23
Finished Dec 27 12:52:30 PM PST 23
Peak memory 200736 kb
Host smart-1e597c31-c2c8-4497-b568-4e4862dfb943
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977000726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1977000726
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2105972407
Short name T594
Test name
Test status
Simulation time 161126325165 ps
CPU time 174.36 seconds
Started Dec 27 12:40:10 PM PST 23
Finished Dec 27 12:43:54 PM PST 23
Peak memory 200484 kb
Host smart-61e6b50d-d9a3-4190-a806-361140fcb971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105972407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2105972407
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3222711624
Short name T668
Test name
Test status
Simulation time 328758936960 ps
CPU time 48.42 seconds
Started Dec 27 12:39:10 PM PST 23
Finished Dec 27 12:40:21 PM PST 23
Peak memory 200936 kb
Host smart-8153155e-ca20-4340-9b5e-86844eefeca1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222711624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3222711624
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1395215860
Short name T779
Test name
Test status
Simulation time 162804336462 ps
CPU time 92.31 seconds
Started Dec 27 12:38:46 PM PST 23
Finished Dec 27 12:40:28 PM PST 23
Peak memory 200744 kb
Host smart-c304fd3d-61c3-43f4-b745-9bf538294821
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395215860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1395215860
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.243718335
Short name T640
Test name
Test status
Simulation time 109538674170 ps
CPU time 428.43 seconds
Started Dec 27 12:38:59 PM PST 23
Finished Dec 27 12:46:23 PM PST 23
Peak memory 201332 kb
Host smart-a2b432d9-a1d6-41b1-8753-927e4f9c423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243718335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.243718335
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1370909471
Short name T649
Test name
Test status
Simulation time 36245298349 ps
CPU time 41.1 seconds
Started Dec 27 12:40:39 PM PST 23
Finished Dec 27 12:42:21 PM PST 23
Peak memory 200264 kb
Host smart-33f08147-30c4-4328-8e48-ae02ab83a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370909471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1370909471
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4149289903
Short name T422
Test name
Test status
Simulation time 4206892648 ps
CPU time 11.26 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:39:12 PM PST 23
Peak memory 200632 kb
Host smart-0023fa37-1d25-48f2-9868-888911a0ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149289903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4149289903
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.983844467
Short name T486
Test name
Test status
Simulation time 5809905647 ps
CPU time 11.09 seconds
Started Dec 27 12:38:42 PM PST 23
Finished Dec 27 12:39:03 PM PST 23
Peak memory 200556 kb
Host smart-7c5be615-7fe4-4bed-8da4-19974234e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983844467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.983844467
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.633797162
Short name T239
Test name
Test status
Simulation time 161277085206 ps
CPU time 92.3 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:40:35 PM PST 23
Peak memory 200816 kb
Host smart-1d239fd9-b1ea-43ae-90b4-94fc7f607fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633797162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
633797162
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2679512953
Short name T443
Test name
Test status
Simulation time 289500089 ps
CPU time 1.28 seconds
Started Dec 27 12:39:03 PM PST 23
Finished Dec 27 12:39:27 PM PST 23
Peak memory 200616 kb
Host smart-f503af87-fe49-41ad-a063-aad554163491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679512953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2679512953
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.363457371
Short name T301
Test name
Test status
Simulation time 498296025019 ps
CPU time 575.53 seconds
Started Dec 27 12:39:18 PM PST 23
Finished Dec 27 12:49:19 PM PST 23
Peak memory 200836 kb
Host smart-f9ee3104-ca40-4424-975f-ecfe629e8a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363457371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.363457371
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3270557904
Short name T571
Test name
Test status
Simulation time 486978778851 ps
CPU time 297.76 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:44:03 PM PST 23
Peak memory 200780 kb
Host smart-89bc5814-66e1-4d81-8d4c-f250f496324f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270557904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3270557904
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1726033267
Short name T155
Test name
Test status
Simulation time 335736536811 ps
CPU time 148.34 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:41:16 PM PST 23
Peak memory 200828 kb
Host smart-1a006485-2447-4080-9907-6b19e8a43d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726033267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1726033267
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3973175746
Short name T500
Test name
Test status
Simulation time 327459001612 ps
CPU time 193.58 seconds
Started Dec 27 12:40:43 PM PST 23
Finished Dec 27 12:44:57 PM PST 23
Peak memory 200472 kb
Host smart-48eebc67-6ddd-4e09-8447-5fa085d82f2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973175746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3973175746
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1415923175
Short name T638
Test name
Test status
Simulation time 162937323329 ps
CPU time 89.08 seconds
Started Dec 27 12:40:30 PM PST 23
Finished Dec 27 12:42:56 PM PST 23
Peak memory 200508 kb
Host smart-06de3bdd-aa0d-4926-a775-cb8df8aaa4e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415923175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1415923175
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1106406825
Short name T796
Test name
Test status
Simulation time 167029260812 ps
CPU time 67.41 seconds
Started Dec 27 12:40:56 PM PST 23
Finished Dec 27 12:43:08 PM PST 23
Peak memory 200484 kb
Host smart-f8237bb7-144d-4b56-a1b8-006328f37a8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106406825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1106406825
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1326129715
Short name T99
Test name
Test status
Simulation time 96237357110 ps
CPU time 327.21 seconds
Started Dec 27 12:39:39 PM PST 23
Finished Dec 27 12:45:45 PM PST 23
Peak memory 199756 kb
Host smart-cbd51f4d-df4c-4893-8a54-5f32bf8d6315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326129715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1326129715
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3147592437
Short name T726
Test name
Test status
Simulation time 23337902092 ps
CPU time 54.31 seconds
Started Dec 27 12:39:17 PM PST 23
Finished Dec 27 12:40:36 PM PST 23
Peak memory 200580 kb
Host smart-71f0291f-118a-4368-8297-6b7198806b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147592437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3147592437
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1959631517
Short name T828
Test name
Test status
Simulation time 5479393070 ps
CPU time 1.37 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:38:43 PM PST 23
Peak memory 200576 kb
Host smart-b54fe73c-cc41-4374-8df9-5b4962f44386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959631517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1959631517
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.102078882
Short name T834
Test name
Test status
Simulation time 5856227126 ps
CPU time 4.01 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:39:05 PM PST 23
Peak memory 200536 kb
Host smart-c0af803e-0f14-4ed7-9336-064ed7056772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102078882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.102078882
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1518417202
Short name T215
Test name
Test status
Simulation time 55486453435 ps
CPU time 211.08 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:42:18 PM PST 23
Peak memory 201184 kb
Host smart-df85c1f6-5c23-4492-a7e4-848304a02e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518417202 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1518417202
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.743108655
Short name T632
Test name
Test status
Simulation time 383038136 ps
CPU time 1.43 seconds
Started Dec 27 12:39:06 PM PST 23
Finished Dec 27 12:39:25 PM PST 23
Peak memory 200608 kb
Host smart-4b898bff-53ce-489c-b44d-29f92780e087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743108655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.743108655
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3561920877
Short name T277
Test name
Test status
Simulation time 166835102184 ps
CPU time 66.06 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:40:18 PM PST 23
Peak memory 200824 kb
Host smart-41a30647-a30d-4ed8-be3d-44c6de7950ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561920877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3561920877
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3828532078
Short name T826
Test name
Test status
Simulation time 332439908404 ps
CPU time 376.8 seconds
Started Dec 27 12:38:45 PM PST 23
Finished Dec 27 12:45:11 PM PST 23
Peak memory 200828 kb
Host smart-4cc6a463-ebdd-491d-b0c3-0302142ae87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828532078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3828532078
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.38965248
Short name T106
Test name
Test status
Simulation time 496975439119 ps
CPU time 122.7 seconds
Started Dec 27 12:38:44 PM PST 23
Finished Dec 27 12:40:56 PM PST 23
Peak memory 200748 kb
Host smart-05e558f6-ae9e-4aea-a875-7f7f985caa20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=38965248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt
_fixed.38965248
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2896959628
Short name T673
Test name
Test status
Simulation time 330300239972 ps
CPU time 43.18 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:39:40 PM PST 23
Peak memory 200756 kb
Host smart-9bfff4cc-37cb-4b58-9766-70a79abe19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896959628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2896959628
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3909167365
Short name T672
Test name
Test status
Simulation time 164496592567 ps
CPU time 377.73 seconds
Started Dec 27 12:38:42 PM PST 23
Finished Dec 27 12:45:09 PM PST 23
Peak memory 200728 kb
Host smart-71c465de-ad6c-42fe-8b58-e92c10cc25cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909167365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3909167365
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2475295560
Short name T321
Test name
Test status
Simulation time 162249523543 ps
CPU time 99.78 seconds
Started Dec 27 12:38:53 PM PST 23
Finished Dec 27 12:40:48 PM PST 23
Peak memory 200820 kb
Host smart-492853cd-3e74-4948-89c7-8d78aae890aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475295560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2475295560
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2592376858
Short name T600
Test name
Test status
Simulation time 491344277331 ps
CPU time 1067.53 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:56:19 PM PST 23
Peak memory 200740 kb
Host smart-ca28e198-198e-4e42-a055-462b73222f3c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592376858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2592376858
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2171920751
Short name T866
Test name
Test status
Simulation time 107566223990 ps
CPU time 360.23 seconds
Started Dec 27 12:38:30 PM PST 23
Finished Dec 27 12:44:38 PM PST 23
Peak memory 201112 kb
Host smart-b76ea585-a750-4f0f-8ad7-3224ee8ebc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171920751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2171920751
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1200676413
Short name T452
Test name
Test status
Simulation time 39668469075 ps
CPU time 26.35 seconds
Started Dec 27 12:38:23 PM PST 23
Finished Dec 27 12:38:57 PM PST 23
Peak memory 200608 kb
Host smart-fd1d7335-4242-4870-a15c-2d5678f26485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200676413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1200676413
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3729844996
Short name T535
Test name
Test status
Simulation time 2729728953 ps
CPU time 4.13 seconds
Started Dec 27 12:38:31 PM PST 23
Finished Dec 27 12:38:44 PM PST 23
Peak memory 200696 kb
Host smart-88b947cf-5c43-4b21-9c93-f4d1710f2b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729844996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3729844996
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1500767694
Short name T481
Test name
Test status
Simulation time 5697908505 ps
CPU time 3.93 seconds
Started Dec 27 12:38:44 PM PST 23
Finished Dec 27 12:38:58 PM PST 23
Peak memory 200540 kb
Host smart-1d5df71c-2f28-4615-9f79-b75a93822c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500767694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1500767694
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.297933192
Short name T204
Test name
Test status
Simulation time 332091809632 ps
CPU time 719 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:51:00 PM PST 23
Peak memory 200804 kb
Host smart-9df03df4-5308-4ead-a41a-ad44c0f6aa8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297933192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
297933192
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.982332106
Short name T592
Test name
Test status
Simulation time 345894140 ps
CPU time 0.8 seconds
Started Dec 27 12:38:40 PM PST 23
Finished Dec 27 12:38:51 PM PST 23
Peak memory 200568 kb
Host smart-41f76ae7-1f52-442b-9504-ee554e96dace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982332106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.982332106
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2984819886
Short name T262
Test name
Test status
Simulation time 162731587493 ps
CPU time 396.79 seconds
Started Dec 27 12:38:27 PM PST 23
Finished Dec 27 12:45:10 PM PST 23
Peak memory 200716 kb
Host smart-5abe76e4-cbf6-4aac-b286-26098e122a74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984819886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2984819886
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4192875201
Short name T525
Test name
Test status
Simulation time 163483609176 ps
CPU time 227.95 seconds
Started Dec 27 12:38:56 PM PST 23
Finished Dec 27 12:43:00 PM PST 23
Peak memory 200864 kb
Host smart-329791a4-568f-4826-ae27-96a098cbe598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192875201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4192875201
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.180933919
Short name T263
Test name
Test status
Simulation time 160546097901 ps
CPU time 182.69 seconds
Started Dec 27 12:39:05 PM PST 23
Finished Dec 27 12:42:25 PM PST 23
Peak memory 200920 kb
Host smart-2c9759e7-a7f7-435f-8997-acb23cf569a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180933919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.180933919
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2397627045
Short name T634
Test name
Test status
Simulation time 160727087792 ps
CPU time 365.51 seconds
Started Dec 27 12:38:53 PM PST 23
Finished Dec 27 12:45:14 PM PST 23
Peak memory 200776 kb
Host smart-a01f117a-8ac2-4655-9f73-ca5c82fc4107
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397627045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2397627045
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3118525473
Short name T115
Test name
Test status
Simulation time 491382149602 ps
CPU time 636.65 seconds
Started Dec 27 12:38:16 PM PST 23
Finished Dec 27 12:49:00 PM PST 23
Peak memory 200760 kb
Host smart-85f4ea36-5459-4299-8252-d69146e41269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118525473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3118525473
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2687309384
Short name T414
Test name
Test status
Simulation time 492725515949 ps
CPU time 1059.36 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:56:49 PM PST 23
Peak memory 200792 kb
Host smart-da88c742-bf37-4a62-9f4b-cd35bb950d27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687309384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2687309384
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1131250822
Short name T217
Test name
Test status
Simulation time 489027497189 ps
CPU time 1143.7 seconds
Started Dec 27 12:38:45 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 200768 kb
Host smart-8f52e856-a33b-4538-800f-293177d4f2eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131250822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1131250822
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1970315670
Short name T682
Test name
Test status
Simulation time 329362153441 ps
CPU time 194.42 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:42:28 PM PST 23
Peak memory 200796 kb
Host smart-8d9d1faa-6d80-408f-bd70-e73263151059
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970315670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1970315670
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.684842596
Short name T176
Test name
Test status
Simulation time 103543530000 ps
CPU time 320.37 seconds
Started Dec 27 12:38:40 PM PST 23
Finished Dec 27 12:44:10 PM PST 23
Peak memory 201052 kb
Host smart-af30b014-a9ad-43ce-b794-6f8079d549f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684842596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.684842596
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3314236206
Short name T727
Test name
Test status
Simulation time 41688144390 ps
CPU time 24.18 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:39:13 PM PST 23
Peak memory 200584 kb
Host smart-2293d156-d374-42f7-aba8-910b4beada43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314236206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3314236206
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2734256153
Short name T468
Test name
Test status
Simulation time 3956439728 ps
CPU time 1.72 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 200640 kb
Host smart-6d1dfadf-c88e-4fcf-a89e-2f7ef176b8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734256153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2734256153
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.4030012418
Short name T852
Test name
Test status
Simulation time 5849855727 ps
CPU time 1.86 seconds
Started Dec 27 12:38:45 PM PST 23
Finished Dec 27 12:38:57 PM PST 23
Peak memory 200684 kb
Host smart-ad00de80-c5bb-4d88-94e3-7b501621f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030012418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.4030012418
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3657578452
Short name T636
Test name
Test status
Simulation time 47378954190 ps
CPU time 26.27 seconds
Started Dec 27 12:38:49 PM PST 23
Finished Dec 27 12:39:26 PM PST 23
Peak memory 200824 kb
Host smart-1d5ab3f7-6abf-4d18-9ba0-c34ecafa0877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657578452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3657578452
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.331514822
Short name T567
Test name
Test status
Simulation time 204330162687 ps
CPU time 77.14 seconds
Started Dec 27 12:38:55 PM PST 23
Finished Dec 27 12:40:28 PM PST 23
Peak memory 200820 kb
Host smart-8fcceadc-ab8b-4fda-a9fb-1c695cd9dfec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331514822 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.331514822
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.819796659
Short name T807
Test name
Test status
Simulation time 492425892 ps
CPU time 0.79 seconds
Started Dec 27 12:38:54 PM PST 23
Finished Dec 27 12:39:10 PM PST 23
Peak memory 200548 kb
Host smart-d6f2a311-0a12-4ff4-853b-bf4862f7637f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819796659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.819796659
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1434174886
Short name T292
Test name
Test status
Simulation time 497464534173 ps
CPU time 312.54 seconds
Started Dec 27 12:38:39 PM PST 23
Finished Dec 27 12:44:06 PM PST 23
Peak memory 200772 kb
Host smart-2d0a3f69-8db2-4e03-abfa-0eb5d842cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434174886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1434174886
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1909222000
Short name T278
Test name
Test status
Simulation time 160651953465 ps
CPU time 207.98 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:42:41 PM PST 23
Peak memory 200736 kb
Host smart-36c9dce4-e52a-450f-9f25-d853d201bffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909222000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1909222000
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2290191669
Short name T660
Test name
Test status
Simulation time 327231199434 ps
CPU time 59.95 seconds
Started Dec 27 12:38:46 PM PST 23
Finished Dec 27 12:39:55 PM PST 23
Peak memory 200716 kb
Host smart-3de23110-18be-4c8e-97f2-acec870d7753
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290191669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2290191669
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1077310563
Short name T187
Test name
Test status
Simulation time 498200946213 ps
CPU time 1134.82 seconds
Started Dec 27 12:38:42 PM PST 23
Finished Dec 27 12:57:47 PM PST 23
Peak memory 200892 kb
Host smart-1e83b650-6bbb-42e7-9f26-c9999eea953e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077310563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1077310563
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2937221799
Short name T466
Test name
Test status
Simulation time 163015092620 ps
CPU time 375.72 seconds
Started Dec 27 12:38:21 PM PST 23
Finished Dec 27 12:44:45 PM PST 23
Peak memory 200756 kb
Host smart-045bbf83-1450-4b3f-807c-3f290af2fc70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937221799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2937221799
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2321436879
Short name T279
Test name
Test status
Simulation time 333158333965 ps
CPU time 184.66 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:41:45 PM PST 23
Peak memory 200672 kb
Host smart-001ff64c-4df8-4b69-9fbf-957fa02340cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321436879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2321436879
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1672147090
Short name T410
Test name
Test status
Simulation time 164206808327 ps
CPU time 93.99 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:40:39 PM PST 23
Peak memory 200808 kb
Host smart-8a5ab752-710d-4b50-8e88-728a130408e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672147090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1672147090
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3124131900
Short name T168
Test name
Test status
Simulation time 122460071438 ps
CPU time 643.46 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:49:40 PM PST 23
Peak memory 201296 kb
Host smart-8cf01cb8-c301-49f1-9045-635f75ba81ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124131900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3124131900
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.338631246
Short name T457
Test name
Test status
Simulation time 35670087785 ps
CPU time 22.13 seconds
Started Dec 27 12:38:59 PM PST 23
Finished Dec 27 12:39:37 PM PST 23
Peak memory 200148 kb
Host smart-ad890861-82ab-458d-a296-6971c54a5d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338631246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.338631246
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.638003284
Short name T780
Test name
Test status
Simulation time 4548374212 ps
CPU time 3.7 seconds
Started Dec 27 12:38:55 PM PST 23
Finished Dec 27 12:39:14 PM PST 23
Peak memory 200680 kb
Host smart-b0f5e078-5e54-403d-9500-092997c020af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638003284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.638003284
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.740092324
Short name T463
Test name
Test status
Simulation time 5722319491 ps
CPU time 4.07 seconds
Started Dec 27 12:38:34 PM PST 23
Finished Dec 27 12:38:46 PM PST 23
Peak memory 200524 kb
Host smart-550b9a72-bdac-4988-bf0f-72f501d3a3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740092324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.740092324
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1308776100
Short name T621
Test name
Test status
Simulation time 320403184912 ps
CPU time 1120.77 seconds
Started Dec 27 12:39:06 PM PST 23
Finished Dec 27 12:58:05 PM PST 23
Peak memory 201088 kb
Host smart-feb490ef-af96-4e99-8c06-87c2c480c8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308776100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1308776100
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1274373880
Short name T210
Test name
Test status
Simulation time 208900784980 ps
CPU time 195.73 seconds
Started Dec 27 12:38:59 PM PST 23
Finished Dec 27 12:42:30 PM PST 23
Peak memory 209268 kb
Host smart-8df4cf16-fc00-4ec9-a9cc-573a9ec10afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274373880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1274373880
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1118028277
Short name T662
Test name
Test status
Simulation time 342412121 ps
CPU time 1.35 seconds
Started Dec 27 12:38:52 PM PST 23
Finished Dec 27 12:39:14 PM PST 23
Peak memory 200456 kb
Host smart-fd5a4c4f-e051-4787-b529-28a86980067d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118028277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1118028277
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2495162130
Short name T655
Test name
Test status
Simulation time 166480243762 ps
CPU time 399.74 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:45:37 PM PST 23
Peak memory 200712 kb
Host smart-c6e617c3-07b9-4e4f-933a-33182c02f1f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495162130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2495162130
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3061186073
Short name T135
Test name
Test status
Simulation time 327864761387 ps
CPU time 210.28 seconds
Started Dec 27 12:38:57 PM PST 23
Finished Dec 27 12:42:43 PM PST 23
Peak memory 200856 kb
Host smart-e259d6f9-a8c5-43b6-a13d-7d2ecca566fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061186073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3061186073
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4045729912
Short name T523
Test name
Test status
Simulation time 162518751223 ps
CPU time 154.35 seconds
Started Dec 27 12:39:26 PM PST 23
Finished Dec 27 12:42:30 PM PST 23
Peak memory 200864 kb
Host smart-7a3f02a0-9857-4f1e-aa04-7e014930cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045729912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4045729912
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2745701762
Short name T821
Test name
Test status
Simulation time 330964696917 ps
CPU time 735.03 seconds
Started Dec 27 12:39:19 PM PST 23
Finished Dec 27 12:52:01 PM PST 23
Peak memory 200696 kb
Host smart-1f7d5b55-c887-415d-9a02-840eb2659e8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745701762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2745701762
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1807837412
Short name T326
Test name
Test status
Simulation time 493006252656 ps
CPU time 270.11 seconds
Started Dec 27 12:38:56 PM PST 23
Finished Dec 27 12:43:42 PM PST 23
Peak memory 200776 kb
Host smart-e73d0ef3-f876-4079-9adb-c4dc685e9dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807837412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1807837412
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3959591387
Short name T459
Test name
Test status
Simulation time 161663853441 ps
CPU time 401.83 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:45:40 PM PST 23
Peak memory 200740 kb
Host smart-c04ac512-bc4b-4af5-a94a-d23ee1c8e989
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959591387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3959591387
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2630391649
Short name T540
Test name
Test status
Simulation time 159741584573 ps
CPU time 70.02 seconds
Started Dec 27 12:39:15 PM PST 23
Finished Dec 27 12:40:51 PM PST 23
Peak memory 200728 kb
Host smart-12439f45-d073-4497-910d-7bb7a7fcdf8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630391649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2630391649
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.329920188
Short name T22
Test name
Test status
Simulation time 322687941602 ps
CPU time 173.71 seconds
Started Dec 27 12:38:52 PM PST 23
Finished Dec 27 12:42:00 PM PST 23
Peak memory 200812 kb
Host smart-041fa1fe-a745-4445-82b1-872ccbd3eb03
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329920188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.329920188
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1776933499
Short name T804
Test name
Test status
Simulation time 111551153651 ps
CPU time 465.24 seconds
Started Dec 27 12:38:59 PM PST 23
Finished Dec 27 12:47:00 PM PST 23
Peak memory 201116 kb
Host smart-817f0537-5e7f-49b3-bc03-57ce2f0ef3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776933499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1776933499
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1115196720
Short name T471
Test name
Test status
Simulation time 31700527290 ps
CPU time 70.37 seconds
Started Dec 27 12:39:15 PM PST 23
Finished Dec 27 12:40:51 PM PST 23
Peak memory 200656 kb
Host smart-6cba2946-6c67-4fa3-9e48-d5d4c8f7659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115196720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1115196720
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.4160080054
Short name T527
Test name
Test status
Simulation time 4947087249 ps
CPU time 6.41 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:38:47 PM PST 23
Peak memory 200608 kb
Host smart-8d3557a3-fb48-400c-b620-c0a4e1e12f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160080054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.4160080054
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3405507671
Short name T564
Test name
Test status
Simulation time 5834252085 ps
CPU time 13.77 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:39:17 PM PST 23
Peak memory 200596 kb
Host smart-438105a5-5df1-4d2a-a3ce-94e86cfb68b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405507671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3405507671
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1078598439
Short name T212
Test name
Test status
Simulation time 53466266195 ps
CPU time 63.89 seconds
Started Dec 27 12:39:14 PM PST 23
Finished Dec 27 12:40:43 PM PST 23
Peak memory 200824 kb
Host smart-25ee852d-8d02-4dd3-9c79-52da427c16bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078598439 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1078598439
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1373990534
Short name T717
Test name
Test status
Simulation time 571279732 ps
CPU time 0.71 seconds
Started Dec 27 12:39:04 PM PST 23
Finished Dec 27 12:39:21 PM PST 23
Peak memory 200556 kb
Host smart-b5497df7-b184-42ea-99d5-020ced3198df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373990534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1373990534
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3005665317
Short name T146
Test name
Test status
Simulation time 491262142300 ps
CPU time 248.83 seconds
Started Dec 27 12:38:47 PM PST 23
Finished Dec 27 12:43:05 PM PST 23
Peak memory 200828 kb
Host smart-ec08dfd3-25dc-480b-bafd-cfe93db1afe1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005665317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3005665317
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.149972348
Short name T158
Test name
Test status
Simulation time 323695835406 ps
CPU time 74.37 seconds
Started Dec 27 12:38:12 PM PST 23
Finished Dec 27 12:39:33 PM PST 23
Peak memory 200828 kb
Host smart-9f51fc03-4757-4583-b8f7-19a61f02e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149972348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.149972348
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.186500842
Short name T341
Test name
Test status
Simulation time 168514987413 ps
CPU time 100.32 seconds
Started Dec 27 12:39:07 PM PST 23
Finished Dec 27 12:41:06 PM PST 23
Peak memory 200760 kb
Host smart-da08bf59-00de-4798-8408-f92319ef5574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186500842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.186500842
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.850786749
Short name T156
Test name
Test status
Simulation time 162738607234 ps
CPU time 102.49 seconds
Started Dec 27 12:38:51 PM PST 23
Finished Dec 27 12:40:47 PM PST 23
Peak memory 200644 kb
Host smart-0c530452-fc5f-4947-b94e-0d12265a0970
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=850786749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.850786749
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.493451621
Short name T119
Test name
Test status
Simulation time 321108842247 ps
CPU time 643.33 seconds
Started Dec 27 12:38:48 PM PST 23
Finished Dec 27 12:49:51 PM PST 23
Peak memory 200688 kb
Host smart-fd05d949-b5b7-4531-b271-83b048fdc240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493451621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.493451621
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3666820291
Short name T656
Test name
Test status
Simulation time 501381745561 ps
CPU time 611.7 seconds
Started Dec 27 12:39:21 PM PST 23
Finished Dec 27 12:50:00 PM PST 23
Peak memory 200704 kb
Host smart-7da6ff84-c0d9-494b-9895-0600503619f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666820291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3666820291
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3856039867
Short name T792
Test name
Test status
Simulation time 239795861925 ps
CPU time 284.21 seconds
Started Dec 27 12:39:04 PM PST 23
Finished Dec 27 12:44:05 PM PST 23
Peak memory 200824 kb
Host smart-081ddc3f-7a71-4df0-8a47-322e220444c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856039867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3856039867
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3060041032
Short name T603
Test name
Test status
Simulation time 489603592981 ps
CPU time 1152.21 seconds
Started Dec 27 12:39:08 PM PST 23
Finished Dec 27 12:58:45 PM PST 23
Peak memory 200768 kb
Host smart-52c5ad38-1029-4071-9a41-773a397c543e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060041032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3060041032
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3703048146
Short name T348
Test name
Test status
Simulation time 103479985622 ps
CPU time 586.54 seconds
Started Dec 27 12:39:09 PM PST 23
Finished Dec 27 12:49:18 PM PST 23
Peak memory 201284 kb
Host smart-fa38d156-e41c-457f-b62b-7ff73d1d836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703048146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3703048146
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3689939008
Short name T451
Test name
Test status
Simulation time 33957113851 ps
CPU time 19.94 seconds
Started Dec 27 12:38:55 PM PST 23
Finished Dec 27 12:39:30 PM PST 23
Peak memory 200652 kb
Host smart-58eb3e45-7c44-44fe-9199-a40ba64d5e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689939008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3689939008
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2865844319
Short name T446
Test name
Test status
Simulation time 3984110372 ps
CPU time 5.62 seconds
Started Dec 27 12:38:38 PM PST 23
Finished Dec 27 12:38:52 PM PST 23
Peak memory 200604 kb
Host smart-4409f3e8-104b-4e7c-91f5-e3e03e4b770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865844319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2865844319
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2151749099
Short name T765
Test name
Test status
Simulation time 5827424000 ps
CPU time 7.34 seconds
Started Dec 27 12:39:01 PM PST 23
Finished Dec 27 12:39:25 PM PST 23
Peak memory 200544 kb
Host smart-65243e70-f320-4491-a744-e43593eeaf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151749099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2151749099
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1097142292
Short name T633
Test name
Test status
Simulation time 96338557135 ps
CPU time 452.3 seconds
Started Dec 27 12:38:50 PM PST 23
Finished Dec 27 12:46:37 PM PST 23
Peak memory 210508 kb
Host smart-dc5f28e6-241a-467f-afa8-9344919b1ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097142292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1097142292
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2511428089
Short name T586
Test name
Test status
Simulation time 41933512415 ps
CPU time 31.76 seconds
Started Dec 27 12:38:32 PM PST 23
Finished Dec 27 12:39:12 PM PST 23
Peak memory 200812 kb
Host smart-5f857dec-9e48-4b8d-a63d-cc96cf512de2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511428089 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2511428089
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1574151348
Short name T448
Test name
Test status
Simulation time 511307286 ps
CPU time 1.68 seconds
Started Dec 27 12:37:29 PM PST 23
Finished Dec 27 12:37:46 PM PST 23
Peak memory 200616 kb
Host smart-acec24be-ad5a-4ed3-8af3-c5874bb4be1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574151348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1574151348
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.202038274
Short name T133
Test name
Test status
Simulation time 494846017607 ps
CPU time 231.13 seconds
Started Dec 27 12:37:01 PM PST 23
Finished Dec 27 12:41:17 PM PST 23
Peak memory 200828 kb
Host smart-bd963124-fada-475c-b8b3-7a017d2382b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202038274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.202038274
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2545740521
Short name T244
Test name
Test status
Simulation time 172807281563 ps
CPU time 27.8 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:38:44 PM PST 23
Peak memory 200812 kb
Host smart-8f420c12-7526-4ee1-82a6-5b37065c50ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545740521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2545740521
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2285147862
Short name T802
Test name
Test status
Simulation time 160375770958 ps
CPU time 364.16 seconds
Started Dec 27 12:37:25 PM PST 23
Finished Dec 27 12:43:46 PM PST 23
Peak memory 200800 kb
Host smart-60d94b1c-f96d-42a4-8c69-44549c5da9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285147862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2285147862
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2641340814
Short name T420
Test name
Test status
Simulation time 504003163921 ps
CPU time 1154.14 seconds
Started Dec 27 12:37:26 PM PST 23
Finished Dec 27 12:56:57 PM PST 23
Peak memory 200764 kb
Host smart-25e9127d-1fd7-4a9d-87bb-8072cb940cef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641340814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2641340814
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.4240985601
Short name T823
Test name
Test status
Simulation time 167455652556 ps
CPU time 175.5 seconds
Started Dec 27 12:37:06 PM PST 23
Finished Dec 27 12:40:25 PM PST 23
Peak memory 200664 kb
Host smart-e69f9889-377a-4cf0-86a4-655d8d7d9ba1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240985601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.4240985601
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3026251719
Short name T152
Test name
Test status
Simulation time 162254616230 ps
CPU time 91.24 seconds
Started Dec 27 12:37:43 PM PST 23
Finished Dec 27 12:39:22 PM PST 23
Peak memory 200852 kb
Host smart-deb8d85e-bac2-43ae-92fb-620a014828f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026251719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3026251719
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1986778265
Short name T572
Test name
Test status
Simulation time 487384804311 ps
CPU time 305.17 seconds
Started Dec 27 12:37:50 PM PST 23
Finished Dec 27 12:42:59 PM PST 23
Peak memory 200828 kb
Host smart-f4834587-4c88-43bf-95ae-d2e36167dcba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986778265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1986778265
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2971372787
Short name T643
Test name
Test status
Simulation time 117411536397 ps
CPU time 393.52 seconds
Started Dec 27 12:37:15 PM PST 23
Finished Dec 27 12:44:10 PM PST 23
Peak memory 201368 kb
Host smart-3d600d51-b046-49d7-8629-1fc625cc63c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971372787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2971372787
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3117919388
Short name T747
Test name
Test status
Simulation time 36986535034 ps
CPU time 79.23 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:39:35 PM PST 23
Peak memory 200648 kb
Host smart-90b919d2-2014-44e4-864b-439be64ccd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117919388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3117919388
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.644521544
Short name T684
Test name
Test status
Simulation time 3996103143 ps
CPU time 9.11 seconds
Started Dec 27 12:37:58 PM PST 23
Finished Dec 27 12:38:17 PM PST 23
Peak memory 200680 kb
Host smart-3a7f275f-35fa-4b4b-9e51-b6a9cc7cd465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644521544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.644521544
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3395773721
Short name T456
Test name
Test status
Simulation time 5831529495 ps
CPU time 7.38 seconds
Started Dec 27 12:37:51 PM PST 23
Finished Dec 27 12:38:02 PM PST 23
Peak memory 200688 kb
Host smart-f46f42ce-e207-46a3-aa3f-9ee8b8db937d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395773721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3395773721
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1536884713
Short name T284
Test name
Test status
Simulation time 202370513778 ps
CPU time 450.37 seconds
Started Dec 27 12:38:18 PM PST 23
Finished Dec 27 12:45:57 PM PST 23
Peak memory 200728 kb
Host smart-591e0a26-6a4f-4329-91de-c13654770686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536884713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1536884713
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2892481200
Short name T318
Test name
Test status
Simulation time 149503195976 ps
CPU time 171.74 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:40:30 PM PST 23
Peak memory 209400 kb
Host smart-1b0b696f-aca9-4e12-9818-1a876f09691c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892481200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2892481200
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3463322230
Short name T659
Test name
Test status
Simulation time 302429650 ps
CPU time 0.96 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:37:51 PM PST 23
Peak memory 200532 kb
Host smart-9fd30039-75f9-46fb-9b67-5cb11dcb0ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463322230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3463322230
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3386380658
Short name T254
Test name
Test status
Simulation time 330329948358 ps
CPU time 763.78 seconds
Started Dec 27 12:39:07 PM PST 23
Finished Dec 27 12:52:10 PM PST 23
Peak memory 200792 kb
Host smart-74e1acb3-30f5-4ee9-9cfa-8a0c3e81e511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386380658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3386380658
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2417745561
Short name T273
Test name
Test status
Simulation time 165507987579 ps
CPU time 103.37 seconds
Started Dec 27 12:38:09 PM PST 23
Finished Dec 27 12:39:59 PM PST 23
Peak memory 200700 kb
Host smart-de1c5d17-c907-440a-8286-d1f3591f584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417745561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2417745561
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4194725423
Short name T532
Test name
Test status
Simulation time 161525734206 ps
CPU time 87.19 seconds
Started Dec 27 12:37:27 PM PST 23
Finished Dec 27 12:39:10 PM PST 23
Peak memory 200732 kb
Host smart-ade1e27e-0930-42a1-9790-0f5fc9d9529c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194725423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4194725423
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1378924730
Short name T706
Test name
Test status
Simulation time 495974648091 ps
CPU time 129.09 seconds
Started Dec 27 12:37:22 PM PST 23
Finished Dec 27 12:39:50 PM PST 23
Peak memory 200708 kb
Host smart-36153413-1aa1-47d4-aaf5-8a00d0e90a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378924730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1378924730
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3084016383
Short name T482
Test name
Test status
Simulation time 485115928062 ps
CPU time 286.79 seconds
Started Dec 27 12:38:04 PM PST 23
Finished Dec 27 12:42:58 PM PST 23
Peak memory 200812 kb
Host smart-c61585ca-d4a7-4a77-9c74-ffbc5c1de07c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084016383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3084016383
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2978424139
Short name T628
Test name
Test status
Simulation time 165410908406 ps
CPU time 227.79 seconds
Started Dec 27 12:37:14 PM PST 23
Finished Dec 27 12:41:23 PM PST 23
Peak memory 200788 kb
Host smart-084fdd69-9543-448b-b53f-b424c038717b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978424139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2978424139
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1569685833
Short name T449
Test name
Test status
Simulation time 492025447320 ps
CPU time 1219.73 seconds
Started Dec 27 12:37:19 PM PST 23
Finished Dec 27 12:57:58 PM PST 23
Peak memory 200752 kb
Host smart-c32257f7-20c6-4fc1-8fc3-1d04abcaecb9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569685833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1569685833
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3531576634
Short name T128
Test name
Test status
Simulation time 97625537557 ps
CPU time 389.77 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:44:07 PM PST 23
Peak memory 201220 kb
Host smart-681f4cd2-7abf-405d-aabb-91276c011d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531576634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3531576634
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1729273071
Short name T513
Test name
Test status
Simulation time 25757389471 ps
CPU time 62.88 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:38:40 PM PST 23
Peak memory 200568 kb
Host smart-7163943c-d849-4840-becf-f3833f2fea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729273071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1729273071
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.333647655
Short name T769
Test name
Test status
Simulation time 3078081717 ps
CPU time 2.19 seconds
Started Dec 27 12:39:04 PM PST 23
Finished Dec 27 12:39:22 PM PST 23
Peak memory 200576 kb
Host smart-042d9ae3-f40c-4c81-9397-2f652a474ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333647655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.333647655
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3014317283
Short name T817
Test name
Test status
Simulation time 5540545576 ps
CPU time 4.23 seconds
Started Dec 27 12:38:07 PM PST 23
Finished Dec 27 12:38:17 PM PST 23
Peak memory 200620 kb
Host smart-3692bdd8-80b6-4afb-a4ca-953875289c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014317283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3014317283
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.795085740
Short name T312
Test name
Test status
Simulation time 205496252446 ps
CPU time 485.39 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:45:44 PM PST 23
Peak memory 200760 kb
Host smart-b4c6030a-6f26-4b57-89f8-f0fa2e9396d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795085740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.795085740
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3849128754
Short name T552
Test name
Test status
Simulation time 375092336 ps
CPU time 1.46 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:37:50 PM PST 23
Peak memory 200460 kb
Host smart-59fae8b5-625b-4e9d-a181-c56e89056e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849128754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3849128754
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2520259095
Short name T291
Test name
Test status
Simulation time 165162158269 ps
CPU time 23.42 seconds
Started Dec 27 12:38:17 PM PST 23
Finished Dec 27 12:38:49 PM PST 23
Peak memory 200788 kb
Host smart-192c3895-cb22-485f-b8ff-33a08319b8c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520259095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2520259095
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2782136717
Short name T555
Test name
Test status
Simulation time 493938177974 ps
CPU time 90.26 seconds
Started Dec 27 12:38:11 PM PST 23
Finished Dec 27 12:39:47 PM PST 23
Peak memory 200784 kb
Host smart-9b7565bb-bd94-4ead-9153-97f9ed28ed33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782136717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2782136717
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3138412905
Short name T676
Test name
Test status
Simulation time 161791951240 ps
CPU time 176.65 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:41:09 PM PST 23
Peak memory 200852 kb
Host smart-8acd158e-98ba-471d-99c6-358da35d19c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138412905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3138412905
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1885209037
Short name T537
Test name
Test status
Simulation time 160738755091 ps
CPU time 24.42 seconds
Started Dec 27 12:38:25 PM PST 23
Finished Dec 27 12:38:56 PM PST 23
Peak memory 200748 kb
Host smart-7a6f04dd-675d-4d3d-8a25-0c558bec7bcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885209037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1885209037
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1283269921
Short name T234
Test name
Test status
Simulation time 162248620985 ps
CPU time 102.12 seconds
Started Dec 27 12:37:50 PM PST 23
Finished Dec 27 12:39:36 PM PST 23
Peak memory 200760 kb
Host smart-75bbad46-075a-4902-b4aa-e76af4eb4f81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283269921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1283269921
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2908546098
Short name T485
Test name
Test status
Simulation time 163630280551 ps
CPU time 67.08 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:38:46 PM PST 23
Peak memory 200788 kb
Host smart-07e597cf-d28c-447a-8cdc-80307fa3e2b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908546098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2908546098
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2445714354
Short name T529
Test name
Test status
Simulation time 120371815118 ps
CPU time 515.38 seconds
Started Dec 27 12:37:10 PM PST 23
Finished Dec 27 12:46:08 PM PST 23
Peak memory 201160 kb
Host smart-2e167c4f-6882-4723-aec2-bdeae20a78c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445714354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2445714354
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2200465111
Short name T688
Test name
Test status
Simulation time 23716150529 ps
CPU time 58.03 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:38:36 PM PST 23
Peak memory 200664 kb
Host smart-576e3c82-4931-475b-b046-a6c798602a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200465111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2200465111
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.974139962
Short name T714
Test name
Test status
Simulation time 2901256209 ps
CPU time 8.27 seconds
Started Dec 27 12:37:13 PM PST 23
Finished Dec 27 12:37:42 PM PST 23
Peak memory 200608 kb
Host smart-f4ab58d1-c6a0-4d6f-9e8b-0360702bd6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974139962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.974139962
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1769327080
Short name T612
Test name
Test status
Simulation time 5925986755 ps
CPU time 15.55 seconds
Started Dec 27 12:38:05 PM PST 23
Finished Dec 27 12:38:28 PM PST 23
Peak memory 200392 kb
Host smart-0f71b8e4-f0af-4f7d-a9b3-e3f3b434dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769327080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1769327080
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1148004719
Short name T98
Test name
Test status
Simulation time 61388847288 ps
CPU time 35.79 seconds
Started Dec 27 12:37:09 PM PST 23
Finished Dec 27 12:38:07 PM PST 23
Peak memory 209536 kb
Host smart-c5bcbd3e-e279-40da-ad71-790655e5d950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148004719 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1148004719
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.596119015
Short name T37
Test name
Test status
Simulation time 512032530 ps
CPU time 0.97 seconds
Started Dec 27 12:37:34 PM PST 23
Finished Dec 27 12:37:48 PM PST 23
Peak memory 200520 kb
Host smart-ab767068-35ee-4eff-b270-051231ce1954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596119015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.596119015
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2625179516
Short name T639
Test name
Test status
Simulation time 329370796688 ps
CPU time 391.91 seconds
Started Dec 27 12:37:37 PM PST 23
Finished Dec 27 12:44:21 PM PST 23
Peak memory 200740 kb
Host smart-b45ebb95-3055-4d91-b464-b02f0a854486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625179516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2625179516
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2735800794
Short name T686
Test name
Test status
Simulation time 494481849275 ps
CPU time 1133.21 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:56:43 PM PST 23
Peak memory 200684 kb
Host smart-ba1ec82a-4127-4f37-9a4d-ce5738ead701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735800794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2735800794
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3438178784
Short name T429
Test name
Test status
Simulation time 495163936105 ps
CPU time 612.9 seconds
Started Dec 27 12:38:02 PM PST 23
Finished Dec 27 12:48:23 PM PST 23
Peak memory 200708 kb
Host smart-97acbb71-b951-4436-9287-e52f87859e15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438178784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3438178784
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.9399735
Short name T126
Test name
Test status
Simulation time 495154190494 ps
CPU time 1056.93 seconds
Started Dec 27 12:39:00 PM PST 23
Finished Dec 27 12:56:52 PM PST 23
Peak memory 200792 kb
Host smart-8504f6e7-cd94-4d37-bdd6-54a97f08900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9399735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.9399735
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3815644019
Short name T822
Test name
Test status
Simulation time 320481359195 ps
CPU time 734.52 seconds
Started Dec 27 12:37:37 PM PST 23
Finished Dec 27 12:50:04 PM PST 23
Peak memory 200720 kb
Host smart-8ebc9f4e-2f47-48f2-98f7-e25ef4227ccb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815644019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3815644019
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3694264952
Short name T223
Test name
Test status
Simulation time 328830385482 ps
CPU time 825.34 seconds
Started Dec 27 12:39:02 PM PST 23
Finished Dec 27 12:53:04 PM PST 23
Peak memory 200796 kb
Host smart-8cba8879-f9a9-4dbc-8f48-d6a5dfb98ee7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694264952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3694264952
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.368535730
Short name T498
Test name
Test status
Simulation time 492063238811 ps
CPU time 1225.51 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:58:19 PM PST 23
Peak memory 200748 kb
Host smart-d5a663f7-a1b9-4965-a82e-3d87281e42f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368535730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.368535730
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.940407571
Short name T735
Test name
Test status
Simulation time 95756737574 ps
CPU time 282.64 seconds
Started Dec 27 12:37:10 PM PST 23
Finished Dec 27 12:42:15 PM PST 23
Peak memory 201268 kb
Host smart-71387fd2-aff7-4772-88f9-29c57ec1ecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940407571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.940407571
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1213751476
Short name T665
Test name
Test status
Simulation time 35997997183 ps
CPU time 75.06 seconds
Started Dec 27 12:37:17 PM PST 23
Finished Dec 27 12:38:52 PM PST 23
Peak memory 200624 kb
Host smart-b98d34e1-4b42-4e04-b68b-06f947c1eaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213751476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1213751476
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2771562067
Short name T544
Test name
Test status
Simulation time 3194080213 ps
CPU time 7.42 seconds
Started Dec 27 12:37:38 PM PST 23
Finished Dec 27 12:37:57 PM PST 23
Peak memory 200572 kb
Host smart-60e906b1-e3fb-445a-bc86-c21971506edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771562067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2771562067
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3853456373
Short name T472
Test name
Test status
Simulation time 5797631433 ps
CPU time 11.83 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:37:51 PM PST 23
Peak memory 200540 kb
Host smart-0faba39e-5488-4701-b47d-c51c46dddb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853456373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3853456373
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2397492502
Short name T18
Test name
Test status
Simulation time 216348251887 ps
CPU time 504.84 seconds
Started Dec 27 12:37:15 PM PST 23
Finished Dec 27 12:46:00 PM PST 23
Peak memory 200868 kb
Host smart-a8381f52-8019-42eb-920a-84d257ac57d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397492502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2397492502
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2426022622
Short name T689
Test name
Test status
Simulation time 305826715 ps
CPU time 1.25 seconds
Started Dec 27 12:37:40 PM PST 23
Finished Dec 27 12:37:51 PM PST 23
Peak memory 200536 kb
Host smart-15faf119-53c5-42c6-8650-ad90d4fc500e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426022622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2426022622
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1727549838
Short name T811
Test name
Test status
Simulation time 490136474010 ps
CPU time 249.59 seconds
Started Dec 27 12:37:20 PM PST 23
Finished Dec 27 12:41:49 PM PST 23
Peak memory 200788 kb
Host smart-44e1bc34-2c60-4d4a-bc31-f5f49eb9b842
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727549838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1727549838
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3362544844
Short name T193
Test name
Test status
Simulation time 490149813193 ps
CPU time 328.24 seconds
Started Dec 27 12:37:42 PM PST 23
Finished Dec 27 12:43:19 PM PST 23
Peak memory 200924 kb
Host smart-16dc40d4-9d24-4788-b8e3-ed3a9c4a33b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362544844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3362544844
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2780713407
Short name T339
Test name
Test status
Simulation time 163368225817 ps
CPU time 93.17 seconds
Started Dec 27 12:37:29 PM PST 23
Finished Dec 27 12:39:17 PM PST 23
Peak memory 200872 kb
Host smart-26f34991-ec2a-43d3-affe-41868e008f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780713407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2780713407
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2546126945
Short name T489
Test name
Test status
Simulation time 162479121007 ps
CPU time 42.5 seconds
Started Dec 27 12:37:36 PM PST 23
Finished Dec 27 12:38:31 PM PST 23
Peak memory 200688 kb
Host smart-658e3265-5f32-42e1-a6ae-2702c92a3c49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546126945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2546126945
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1799049997
Short name T116
Test name
Test status
Simulation time 329837799488 ps
CPU time 49.13 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:38:37 PM PST 23
Peak memory 200736 kb
Host smart-bc84be5e-963b-491b-bebf-196cc7a76b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799049997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1799049997
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2749283716
Short name T495
Test name
Test status
Simulation time 160692491325 ps
CPU time 373.6 seconds
Started Dec 27 12:37:18 PM PST 23
Finished Dec 27 12:43:51 PM PST 23
Peak memory 200800 kb
Host smart-2616c34d-c7c9-435d-b3d1-d9346d9b07a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749283716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2749283716
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3086562687
Short name T270
Test name
Test status
Simulation time 503686562848 ps
CPU time 1043.8 seconds
Started Dec 27 12:37:26 PM PST 23
Finished Dec 27 12:55:06 PM PST 23
Peak memory 200764 kb
Host smart-2915c34b-6dac-456f-8581-cd56543d36c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086562687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3086562687
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2474490172
Short name T433
Test name
Test status
Simulation time 166144972155 ps
CPU time 197.92 seconds
Started Dec 27 12:37:44 PM PST 23
Finished Dec 27 12:41:09 PM PST 23
Peak memory 200808 kb
Host smart-a783928d-70a5-4780-a4d8-07de88312689
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474490172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2474490172
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3231754948
Short name T702
Test name
Test status
Simulation time 43746713983 ps
CPU time 15.63 seconds
Started Dec 27 12:37:49 PM PST 23
Finished Dec 27 12:38:09 PM PST 23
Peak memory 200576 kb
Host smart-006d766d-eaee-4a82-bc91-04f81ad7bfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231754948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3231754948
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3224169280
Short name T730
Test name
Test status
Simulation time 4870159593 ps
CPU time 4.52 seconds
Started Dec 27 12:37:54 PM PST 23
Finished Dec 27 12:38:02 PM PST 23
Peak memory 200588 kb
Host smart-2b1559af-ebb9-49bb-9804-a8d7a5972d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224169280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3224169280
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1745716359
Short name T661
Test name
Test status
Simulation time 5889148918 ps
CPU time 7.02 seconds
Started Dec 27 12:37:35 PM PST 23
Finished Dec 27 12:37:55 PM PST 23
Peak memory 200588 kb
Host smart-b8bc45f0-234f-41b2-a1ea-e7ac617c941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745716359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1745716359
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1662276851
Short name T181
Test name
Test status
Simulation time 265681811442 ps
CPU time 925.46 seconds
Started Dec 27 12:39:09 PM PST 23
Finished Dec 27 12:54:57 PM PST 23
Peak memory 201184 kb
Host smart-63c8cc87-374f-4105-9390-9d91c55319c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662276851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1662276851
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3632509805
Short name T307
Test name
Test status
Simulation time 116316219789 ps
CPU time 234.19 seconds
Started Dec 27 12:37:38 PM PST 23
Finished Dec 27 12:41:44 PM PST 23
Peak memory 209424 kb
Host smart-eb86237d-d07c-4fa3-9d95-38ec1973b4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632509805 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3632509805
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%