Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6432	1			T13	61		T14	5		T16	42
testmodes[AdcCtrlTestmodeNormal]	5200	1			T12	3		T13	35		T14	7
testmodes[AdcCtrlTestmodeLowpower]	5561	1			T13	57		T14	2		T15	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3377	1			T13	25		T14	2		T16	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1623	1			T13	11		T14	3		T16	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1310	1			T13	25		T16	12		T17	21
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1629	1			T13	12		T14	2		T16	14
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1902	1			T12	2		T13	6		T14	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1329	1			T13	16		T16	11		T17	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1319	1			T13	23		T14	1		T16	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1338	1			T13	18		T16	12		T17	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2673	1			T13	16		T14	1		T15	1