Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21254

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3415

1

T12

3

T24

11

T57

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18646

1

T5

2

T28

1

T32

3

auto[1]

6023

1

T12

2

T13

5

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	412	1			T13	5		T16	13		T17	1
values[0]	45	1			T116	22		T98	1		T191	8
values[1]	588	1			T86	1		T95	13		T192	1
values[2]	2665	1			T12	1		T15	17		T18	2
values[3]	706	1			T14	9		T93	15		T94	26
values[4]	774	1			T39	10		T87	16		T82	27
values[5]	632	1			T22	1		T88	1		T83	5
values[6]	570	1			T12	1		T57	1		T82	21
values[7]	693	1			T39	5		T81	45		T87	10
values[8]	879	1			T12	1		T57	1		T81	15
values[9]	830	1			T14	2		T21	5		T22	20
minimum	15875	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	780	1			T12	1		T24	11		T87	15
values[1]	2653	1			T14	9		T15	17		T18	2
values[2]	774	1			T39	3		T93	15		T82	27
values[3]	719	1			T39	7		T87	16		T88	1
values[4]	632	1			T82	21		T85	2		T90	11
values[5]	555	1			T12	1		T22	1		T87	10
values[6]	670	1			T39	5		T57	1		T81	45
values[7]	856	1			T12	1		T57	1		T81	15
values[8]	612	1			T14	2		T21	5		T22	20
values[9]	121	1			T101	8		T193	12		T194	1
minimum	16297	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T87	8		T82	5		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	1		T24	9		T95	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T14	5		T15	17		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T88	2		T195	1		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T39	2		T82	13		T94	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T93	1		T94	1		T41	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T39	6		T88	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T87	8		T83	5		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T90	11		T102	14		T105	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T82	10		T85	1		T91	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	1		T91	13		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T87	8		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	3		T79	7		T150	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	1		T81	25		T83	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T103	4		T96	6		T105	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T57	1		T81	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	2		T21	1		T22	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T93	1		T104	7		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T198	1		T199	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T101	5		T193	12		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16141	1			T13	153		T14	10		T16	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T87	7		T82	12		T115	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T24	2		T201	1		T202	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T14	4		T20	24		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T195	1		T101	7		T203	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	1		T82	14		T94	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T93	14		T94	2		T41	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	1		T105	5		T204	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T87	8		T90	13		T205	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T102	12		T105	14		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T82	11		T85	1		T202	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T117	13		T207	2		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T87	2		T86	9		T173	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T39	2		T79	1		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T81	20		T89	2		T195	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T103	3		T105	9		T209	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T81	6		T94	2		T90	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T21	4		T22	10		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T93	8		T173	6		T141	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T198	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T101	3		T100	7		T123	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	2		T28	1		T32	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T13	5		T16	13		T17	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T116	12		T98	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T191	8		T210	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T86	1		T96	12		T211	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T95	13		T192	1		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T15	17		T18	2		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T24	9		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	5		T94	12		T213	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T93	1		T94	1		T41	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	8		T82	13		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T87	8		T84	14		T103	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	1		T88	1		T90	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T83	5		T85	1		T90	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T91	13		T139	1		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T12	1		T57	1		T82	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T39	3		T79	7		T150	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T81	25		T87	8		T83	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T102	5		T96	6		T105	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T57	1		T81	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	2		T21	1		T22	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T93	1		T101	5		T104	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15729	1			T13	148		T14	10		T16	107
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T214	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T116	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T210	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T215	12		T161	12		T118	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T202	13		T163	1		T99	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T20	24		T87	7		T82	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T24	2		T195	1		T201	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	4		T94	11		T213	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T93	14		T94	2		T41	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	2		T82	14		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T87	8		T84	15		T103	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T102	12		T105	14		T216	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T85	1		T90	13		T86	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T206	2		T207	2		T217	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T82	11		T173	3		T102	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	2		T79	1		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T81	20		T87	2		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T102	5		T105	9		T209	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T81	6		T94	2		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T21	4		T22	10		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T93	8		T101	3		T173	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T87	8		T82	13		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	1		T24	8		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T14	6		T15	2		T18	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T88	2		T195	2		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T39	3		T82	15		T94	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T93	15		T94	3		T41	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	3		T88	1		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T87	9		T83	1		T90	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T90	1		T102	13		T105	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T82	12		T85	2		T91	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T22	1		T91	1		T196	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	1		T87	3		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	4		T79	7		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T57	1		T81	22		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T103	4		T96	1		T105	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T12	1		T57	1		T81	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	2		T21	5		T22	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T93	9		T104	1		T173	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T198	5		T199	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T101	4		T193	1		T194	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16286	1			T5	2		T28	1		T32	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T87	7		T82	4		T96	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	3		T95	12		T140	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T14	3		T15	15		T23	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T101	9		T177	12		T203	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T82	12		T94	11		T213	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T41	9		T84	13		T218	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T39	4		T204	3		T219	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T87	7		T83	4		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T90	10		T102	13		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T82	9		T91	2		T104	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T91	12		T207	7		T217	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T87	7		T86	4		T102	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T39	1		T79	1		T150	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T81	23		T83	7		T89	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T103	3		T96	5		T105	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T81	8		T94	3		T90	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T22	9		T40	1		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T104	6		T141	12		T128	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T101	4		T193	11		T100	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T116	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	412	1			T13	5		T16	13		T17	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T116	11		T98	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T191	1		T210	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T86	1		T96	1		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T95	1		T192	1		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T15	2		T18	2		T20	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T24	8		T88	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	6		T94	12		T213	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T93	15		T94	3		T41	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	6		T82	15		T105	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T87	9		T84	16		T103	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T22	1		T88	1		T90	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T83	1		T85	2		T90	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T91	1		T139	1		T206	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T57	1		T82	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T39	4		T79	7		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T81	22		T87	3		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T102	6		T96	1		T105	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T12	1		T57	1		T81	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	2		T21	5		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T93	9		T101	4		T104	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15875	1			T5	2		T28	1		T32	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T116	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T191	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T96	11		T211	2		T215	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T95	12		T99	11		T220	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T15	15		T23	17		T46	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T24	3		T140	6		T203	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T14	3		T94	11		T213	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	9		T218	3		T101	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T39	4		T82	12		T204	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T87	7		T84	13		T103	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T90	10		T102	13		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T83	4		T90	10		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T91	12		T207	7		T217	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T82	9		T102	14		T96	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T39	1		T79	1		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T81	23		T87	7		T83	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T102	4		T96	5		T105	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T81	8		T94	3		T89	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T22	9		T40	1		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T101	4		T104	6		T141	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21438

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3231

1

T12

2

T21

5

T39

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18966

1

T5

2

T28

1

T32

3

auto[1]

5703

1

T12

3

T14

2

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T177	13		-	-		-	-
values[0]	30	1			T115	2		T125	16		T221	1
values[1]	775	1			T22	20		T56	1		T39	7
values[2]	331	1			T39	5		T81	15		T40	3
values[3]	942	1			T93	15		T87	15		T82	17
values[4]	524	1			T39	3		T87	10		T79	8
values[5]	627	1			T24	11		T57	1		T150	24
values[6]	605	1			T81	37		T82	27		T88	1
values[7]	619	1			T81	8		T93	9		T83	5
values[8]	2616	1			T12	2		T14	2		T15	17
values[9]	1312	1			T12	1		T14	9		T21	5
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	774	1			T22	20		T56	1		T39	7
values[1]	637	1			T39	5		T81	15		T87	15
values[2]	851	1			T82	17		T41	19		T83	8
values[3]	459	1			T39	3		T93	15		T87	10
values[4]	620	1			T24	11		T57	1		T150	24
values[5]	549	1			T93	9		T82	27		T88	1
values[6]	2743	1			T12	1		T15	17		T18	2
values[7]	558	1			T12	1		T14	11		T87	16
values[8]	1053	1			T12	1		T21	5		T22	1
values[9]	125	1			T222	1		T208	2		T145	1
minimum	16300	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	10		T56	1		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T39	6		T57	1		T94	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T81	9		T163	1		T223	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	3		T87	8		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T177	8		T224	1		T115	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T82	5		T41	10		T83	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T93	1		T79	7		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	2		T87	8		T121	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	9		T57	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	14		T88	1		T84	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T88	1		T90	11		T195	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T93	1		T82	13		T83	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T12	1		T15	17		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T218	4		T95	13		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	7		T104	6		T102	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T87	8		T140	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T22	1		T94	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	1		T21	1		T82	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T222	1		T208	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T145	1		T226	4		T227	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16140	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T228	1		T200	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	10		T115	1		T118	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	1		T94	2		T106	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T81	6		T163	1		T198	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	2		T87	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T115	21		T105	5		T116	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T82	12		T41	9		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T93	14		T79	1		T215	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T39	1		T87	2		T107	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T24	2		T85	1		T195	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	10		T84	15		T101	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T195	9		T173	9		T209	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T93	8		T82	14		T101	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1104	1			T20	24		T81	20		T94	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T166	14		T163	10		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T14	4		T102	12		T105	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T87	8		T140	10		T143	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T94	2		T84	3		T101	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T21	4		T82	11		T90	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T208	1		T229	4		T230	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T226	5		T227	29		T231	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	2		T28	1		T32	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T177	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T115	1		T125	16		T232	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	1		T233	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T22	10		T56	1		T86	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T39	6		T57	1		T104	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T81	9		T120	1		T130	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T39	3		T40	2		T94	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T93	1		T177	8		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T87	8		T82	5		T83	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T79	7		T115	14		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	2		T87	8		T41	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	9		T57	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T150	14		T88	1		T84	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T81	17		T88	1		T90	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T82	13		T101	5		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T81	8		T173	1		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T93	1		T83	5		T218	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T12	1		T14	2		T15	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T140	10		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T14	5		T22	1		T94	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T12	1		T21	1		T87	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T115	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T233	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	10		T163	1		T118	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	1		T236	15		T106	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T81	6		T198	9		T237	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T39	2		T40	1		T94	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T93	14		T105	5		T116	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T87	7		T82	12		T89	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T79	1		T115	21		T238	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T39	1		T87	2		T41	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T24	2		T85	1		T103	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T150	10		T84	15		T101	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T81	20		T195	10		T173	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T82	14		T101	3		T198	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T173	6		T202	12		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T93	8		T161	12		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T20	24		T94	11		T86	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	10		T166	14		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	4		T94	2		T84	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T21	4		T87	8		T82	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3