Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21395

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3274

1

T14

9

T22

20

T24

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18981

1

T5

2

T28

1

T32

3

auto[1]

5688

1

T12

1

T14

11

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T39	3		T201	2		T121	7
values[0]	16	1			T166	15		T221	1		-	-
values[1]	634	1			T12	1		T56	1		T57	1
values[2]	581	1			T39	7		T57	1		T40	3
values[3]	629	1			T12	1		T14	9		T150	24
values[4]	2707	1			T15	17		T18	2		T20	26
values[5]	509	1			T21	5		T88	1		T91	13
values[6]	575	1			T82	44		T84	4		T90	20
values[7]	730	1			T22	1		T39	5		T84	29
values[8]	756	1			T22	20		T24	11		T81	8
values[9]	1030	1			T12	1		T14	2		T81	37
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	607	1			T12	1		T56	1		T57	1
values[1]	679	1			T12	1		T39	7		T40	3
values[2]	537	1			T14	9		T93	15		T150	24
values[3]	2688	1			T15	17		T18	2		T20	26
values[4]	539	1			T21	5		T88	1		T91	13
values[5]	670	1			T82	44		T84	4		T85	15
values[6]	736	1			T22	1		T24	11		T39	5
values[7]	710	1			T22	20		T93	9		T87	10
values[8]	948	1			T12	1		T14	2		T39	3
values[9]	101	1			T116	7		T264	14		T156	38
minimum	16454	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	1		T94	1		T104	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T56	1		T57	1		T83	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T104	7		T102	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	6		T40	2		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T93	1		T197	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	5		T150	14		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T15	17		T18	2		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T81	9		T88	1		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T21	1		T91	13		T103	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T88	1		T173	1		T102	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T82	5		T96	12		T115	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T82	13		T84	1		T85	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T22	1		T86	1		T102	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	9		T39	3		T81	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T93	1		T79	7		T94	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	10		T87	8		T94	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	1		T14	2		T81	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T39	2		T87	8		T89	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T116	5		T307	1		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T264	14		T156	19		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T57	1		T103	4		T166	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T94	2		T141	7		T239	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T101	7		T115	20		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T102	5		T106	7		T99	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T39	1		T40	1		T41	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T93	14		T115	1		T215	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	4		T150	10		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T20	24		T87	7		T101	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T81	6		T173	6		T205	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T21	4		T103	3		T238	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T173	3		T102	12		T238	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T82	12		T115	21		T204	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T82	14		T84	3		T90	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T102	11		T105	14		T120	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	2		T39	2		T84	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T93	8		T79	1		T94	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	10		T87	2		T94	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T81	20		T82	11		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	1		T87	8		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T116	2		T230	15		T267	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T156	19		T266	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T103	3		T166	14		T296	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T201	1		T309	16		T310	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T39	2		T121	7		T156	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T221	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T166	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	1		T94	1		T141	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T56	1		T57	1		T83	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T104	13		T235	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	6		T57	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T197	1		T102	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	5		T150	14		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T15	17		T18	2		T20	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T81	9		T88	1		T83	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T21	1		T91	13		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T88	1		T173	1		T102	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T82	5		T140	1		T204	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T82	13		T84	1		T90	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T22	1		T86	1		T102	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	3		T84	14		T85	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T93	1		T79	7		T94	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T22	10		T24	9		T81	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T14	2		T81	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T87	16		T89	5		T195	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T201	1		T311	9		T312	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	1		T156	19		T231	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T166	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T94	2		T141	7		T239	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T101	7		T103	3		T115	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T99	8		T269	15		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T39	1		T40	1		T41	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T102	5		T106	7		T130	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	4		T150	10		T103	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T20	24		T93	14		T87	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T81	6		T173	6		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T21	4		T101	1		T103	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T173	3		T102	12		T265	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T82	12		T204	7		T106	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T82	14		T84	3		T90	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T102	11		T115	21		T120	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	2		T84	15		T85	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T93	8		T79	1		T94	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T22	10		T24	2		T94	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T81	20		T82	11		T41	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T87	10		T89	2		T195	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T94	3		T104	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T56	1		T57	1		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T104	1		T102	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	3		T40	2		T41	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T93	15		T197	1		T115	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	6		T150	11		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T15	2		T18	2		T20	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T81	7		T88	1		T173	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T21	5		T91	1		T103	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T88	1		T173	4		T102	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T82	13		T96	1		T115	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T82	15		T84	4		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T22	1		T86	1		T102	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T24	8		T39	4		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T93	9		T79	7		T94	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T22	11		T87	3		T94	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T14	2		T81	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T39	3		T87	9		T89	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T116	3		T307	1		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T264	1		T156	20		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16320	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T57	1		T103	4		T166	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T104	5		T141	12		T211	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T83	7		T101	9		T96	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T104	6		T102	4		T96	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	4		T40	1		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T215	10		T130	21		T306	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T14	3		T150	13		T83	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T15	15		T23	17		T46	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T81	8		T270	6		T100	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T91	12		T103	11		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T102	13		T128	9		T238	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T82	4		T96	11		T115	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T82	12		T85	14		T90	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T102	14		T177	7		T105	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	3		T39	1		T81	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T79	1		T94	3		T91	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	9		T87	7		T94	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T81	16		T82	9		T41	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T87	7		T89	3		T218	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T116	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T264	13		T156	18		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T313	16		T266	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T103	3		T296	11		T220	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T201	2		T309	1		T310	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T39	3		T121	1		T156	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T221	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T166	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T94	3		T141	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T56	1		T57	1		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T104	2		T235	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T39	3		T57	1		T40	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T197	1		T102	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	6		T150	11		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T15	2		T18	2		T20	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T81	7		T88	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T21	5		T91	1		T101	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T88	1		T173	4		T102	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T82	13		T140	1		T204	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T82	15		T84	4		T90	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T22	1		T86	1		T102	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	4		T84	16		T85	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T93	9		T79	7		T94	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T22	11		T24	8		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T14	2		T81	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T87	12		T89	4		T195	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T309	15		T310	13		T263	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T121	6		T156	18		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T141	12		T211	2		T239	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T83	7		T101	9		T103	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T104	11		T260	2		T123	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	4		T40	1		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T102	4		T96	5		T130	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	3		T150	13		T95	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T15	15		T23	17		T46	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T81	8		T83	4		T215	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T91	12		T103	11		T270	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T102	13		T273	11		T271	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T82	4		T204	3		T241	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T82	12		T90	2		T128	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T102	14		T177	7		T96	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	1		T84	13		T85	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T79	1		T94	3		T91	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	9		T24	3		T81	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T81	16		T82	9		T41	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T87	14		T89	3		T218	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9