Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21290

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3379

1

T12

1

T21

5

T22

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19037

1

T5

2

T28

1

T32

3

auto[1]

5632

1

T12

2

T14

9

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	235	1			T86	14		T129	1		T241	11
values[0]	9	1			T307	1		T314	1		T315	5
values[1]	787	1			T12	1		T87	15		T82	27
values[2]	2777	1			T15	17		T18	2		T20	26
values[3]	563	1			T94	23		T150	24		T197	1
values[4]	642	1			T87	16		T89	7		T90	24
values[5]	539	1			T14	9		T39	7		T81	15
values[6]	768	1			T81	37		T93	24		T82	21
values[7]	790	1			T14	2		T22	20		T56	1
values[8]	471	1			T21	5		T39	8		T57	2
values[9]	813	1			T12	2		T24	11		T81	8
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	849	1			T12	1		T94	6		T84	29
values[1]	2666	1			T15	17		T18	2		T20	26
values[2]	505	1			T94	23		T89	7		T90	11
values[3]	731	1			T39	7		T81	15		T87	16
values[4]	554	1			T14	9		T93	9		T82	17
values[5]	786	1			T22	20		T56	1		T81	37
values[6]	677	1			T14	2		T21	5		T39	3
values[7]	518	1			T12	1		T39	5		T57	1
values[8]	818	1			T12	1		T24	11		T81	8
values[9]	83	1			T238	2		T109	12		T316	1
minimum	16482	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T94	4		T84	14		T101	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T234	1		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T15	17		T18	2		T20	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T22	1		T88	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T194	1		T220	18		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T94	12		T89	5		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T87	8		T101	1		T177	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	6		T81	9		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	5		T82	5		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T93	1		T91	3		T160	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T93	1		T82	10		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T22	10		T56	1		T81	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	2		T39	2		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T21	1		T195	7		T103	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	1		T85	15		T213	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	3		T57	1		T79	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T24	9		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T81	8		T41	10		T86	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T109	12		T313	17		T135	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T238	1		T316	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16178	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T82	13		T121	1		T203	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T94	2		T84	15		T101	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T202	12		T166	14		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T20	24		T150	10		T173	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T163	10		T118	13		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T123	4		T318	2		T294	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T94	11		T89	2		T99	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T87	8		T101	1		T115	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	1		T81	6		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	4		T82	12		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T93	8		T160	10		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T93	14		T82	11		T90	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	10		T81	20		T41	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	1		T296	12		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T21	4		T195	9		T103	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T213	9		T202	13		T215	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T39	2		T79	1		T195	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T24	2		T87	2		T85	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	9		T86	9		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T135	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T238	1		T319	7		T320	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T82	14		T203	13		T214	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T109	12		T309	7		T221	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T86	5		T129	1		T241	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T307	1		T315	4		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T87	8		T94	4		T101	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T82	13		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T15	17		T18	2		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T22	1		T88	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T150	14		T197	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T94	12		T90	11		T91	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T87	8		T177	13		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T89	5		T90	11		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	5		T82	5		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T39	6		T81	9		T91	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T93	1		T82	10		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T81	17		T93	1		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	2		T96	18		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T22	10		T56	1		T195	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	2		T57	1		T213	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T21	1		T39	3		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	2		T24	9		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T81	8		T41	10		T104	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T321	3		T135	9		T322	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T86	9		T238	1		T323	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T315	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T87	7		T94	2		T101	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T82	14		T202	12		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T20	24		T84	15		T103	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T166	14		T163	10		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T150	10		T173	6		T102	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T94	11		T99	8		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T87	8		T115	1		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T89	2		T90	13		T201	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	4		T82	12		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T39	1		T81	6		T204	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T93	14		T82	11		T90	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T81	20		T93	8		T41	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T296	12		T122	1		T186	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T22	10		T195	9		T103	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	1		T213	9		T215	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T21	4		T39	2		T79	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T24	2		T87	2		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T41	9		T140	10		T239	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T94	3		T84	16		T101	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T234	1		T235	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T15	2		T18	2		T20	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T22	1		T88	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T194	1		T220	2		T123	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T94	12		T89	4		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T87	9		T101	2		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T39	3		T81	7		T90	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	6		T82	13		T40	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T93	9		T91	1		T160	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T93	15		T82	12		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T22	11		T56	1		T81	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	2		T39	3		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T21	5		T195	15		T103	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T85	1		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	4		T57	1		T79	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T24	8		T87	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T81	1		T41	10		T86	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T109	1		T313	1		T135	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T238	2		T316	1		T317	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16320	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T82	15		T121	1		T203	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T94	3		T84	13		T101	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T277	1		T260	2		T223	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T15	15		T23	17		T46	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T96	5		T140	6		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T220	16		T123	13		T324	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T94	11		T89	3		T90	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T87	7		T177	12		T128	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	4		T81	8		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	3		T82	4		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T91	2		T160	9		T116	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T82	9		T90	2		T101	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T22	9		T81	16		T41	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T96	17		T296	11		T248	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T195	1		T103	11		T161	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T85	14		T213	17		T215	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T39	1		T79	1		T83	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T24	3		T87	7		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T81	7		T41	9		T86	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T109	11		T313	16		T135	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T325	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T87	7		T121	6		T326	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T82	12		T203	11		T327	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T109	1		T309	1		T221	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T86	10		T129	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T307	1		T315	2		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T87	8		T94	3		T101	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T82	15		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T15	2		T18	2		T20	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T22	1		T88	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T150	11		T197	1		T173	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T94	12		T90	1		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T87	9		T177	1		T115	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T89	4		T90	14		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	6		T82	13		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T39	3		T81	7		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T93	15		T82	12		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T81	21		T93	9		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	2		T96	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T22	11		T56	1		T195	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T39	3		T57	1		T213	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T21	5		T39	4		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	2		T24	8		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T81	1		T41	10		T104	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T109	11		T309	6		T263	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T86	4		T241	10		T270	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T315	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T87	7		T94	3		T101	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T82	12		T277	1		T203	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T15	15		T23	17		T46	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T140	6		T163	10		T130	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T150	13		T102	4		T220	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T94	11		T90	10		T91	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T87	7		T177	12		T128	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T89	3		T90	10		T95	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	3		T82	4		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T39	4		T81	8		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T82	9		T90	2		T101	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T81	16		T41	2		T102	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T96	17		T296	11		T100	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T22	9		T195	1		T103	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T213	17		T215	10		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T39	1		T79	1		T83	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	3		T87	7		T85	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T81	7		T41	9		T104	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9