Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21292

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3377

1

T12

1

T21

5

T22

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19032

1

T5

2

T28

1

T32

3

auto[1]

5637

1

T12

2

T14

9

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T270	10		T321	8		T279	1
values[0]	33	1			T258	6		T327	12		T244	7
values[1]	740	1			T12	1		T87	15		T82	27
values[2]	2802	1			T15	17		T18	2		T20	26
values[3]	516	1			T94	23		T150	24		T197	1
values[4]	701	1			T87	16		T94	3		T89	7
values[5]	571	1			T14	9		T39	7		T81	52
values[6]	715	1			T56	1		T93	24		T82	21
values[7]	761	1			T14	2		T21	5		T22	20
values[8]	452	1			T12	1		T39	8		T57	2
values[9]	1084	1			T12	1		T24	11		T81	8
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1002	1			T12	1		T87	15		T82	27
values[1]	2693	1			T15	17		T18	2		T20	26
values[2]	522	1			T94	23		T197	1		T89	7
values[3]	733	1			T39	7		T81	15		T87	16
values[4]	568	1			T14	9		T81	37		T93	9
values[5]	742	1			T56	1		T93	15		T82	21
values[6]	677	1			T14	2		T21	5		T22	20
values[7]	511	1			T12	1		T39	5		T57	1
values[8]	778	1			T12	1		T24	11		T81	8
values[9]	140	1			T85	2		T239	8		T238	2
minimum	16303	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T87	8		T84	14		T101	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T82	13		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T15	17		T18	2		T20	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T22	1		T88	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T197	1		T194	1		T220	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T94	12		T89	5		T90	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T87	8		T101	1		T177	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	6		T81	9		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	5		T82	5		T94	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T81	17		T93	1		T91	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T93	1		T82	10		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T56	1		T41	3		T102	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	2		T39	2		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T21	1		T22	10		T195	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	1		T85	15		T177	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	3		T57	1		T79	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T24	9		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T81	8		T41	10		T86	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T85	1		T109	12		T313	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T239	4		T238	1		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16130	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T203	12		T328	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T87	7		T84	15		T101	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T82	14		T202	12		T166	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T20	24		T94	2		T150	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T163	10		T118	13		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T123	4		T318	2		T294	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T94	11		T89	2		T99	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T87	8		T101	1		T115	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	1		T81	6		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	4		T82	12		T94	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T81	20		T93	8		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T93	14		T82	11		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	4		T102	11		T103	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T39	1		T296	12		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T21	4		T22	10		T195	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T213	9		T202	13		T236	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T39	2		T79	1		T195	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	2		T87	2		T102	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T41	9		T86	9		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T85	1		T329	11		T330	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T239	4		T238	1		T331	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T203	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T321	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T270	10		T279	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T258	4		T307	1		T315	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T327	5		T244	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T87	8		T94	4		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T82	13		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T15	17		T18	2		T20	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T22	1		T88	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T150	14		T197	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T94	12		T90	11		T91	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T87	8		T94	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T89	5		T90	11		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	5		T82	5		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	6		T81	26		T91	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T93	1		T82	10		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	1		T93	1		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	2		T96	18		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T21	1		T22	10		T195	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T39	2		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T39	3		T57	1		T83	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T12	1		T24	9		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T81	8		T79	7		T41	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T321	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T258	2		T315	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T327	7		T244	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T87	7		T94	2		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T82	14		T202	12		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T20	24		T84	15		T101	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T166	14		T163	10		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T150	10		T173	6		T102	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T94	11		T99	8		T216	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T87	8		T94	2		T101	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T89	2		T90	13		T201	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	4		T82	12		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T39	1		T81	26		T204	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T93	14		T82	11		T84	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T93	8		T41	4		T102	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T296	12		T122	1		T100	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T21	4		T22	10		T195	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	1		T213	9		T215	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T39	2		T106	7		T107	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T24	2		T87	2		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T79	1		T41	9		T86	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T87	8		T84	16		T101	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T12	1		T82	15		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T15	2		T18	2		T20	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	1		T88	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T197	1		T194	1		T220	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T94	12		T89	4		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T87	9		T101	2		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	3		T81	7		T90	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	6		T82	13		T94	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T81	21		T93	9		T91	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T93	15		T82	12		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T56	1		T41	5		T102	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	2		T39	3		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T21	5		T22	11		T195	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T85	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	4		T57	1		T79	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T24	8		T87	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T81	1		T41	10		T86	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T85	2		T109	1		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T239	5		T238	2		T316	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16277	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T203	14		T328	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T87	7		T84	13		T101	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T82	12		T121	6		T277	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T15	15		T23	17		T46	30
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T96	5		T140	6		T163	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T220	16		T123	13		T324	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T94	11		T89	3		T90	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T87	7		T177	12		T141	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	4		T81	8		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T14	3		T82	4		T83	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T81	16		T91	2		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T82	9		T40	1		T90	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T41	2		T102	14		T103	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T96	17		T296	11		T248	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T22	9		T195	1		T103	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T85	14		T177	7		T213	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T39	1		T79	1		T83	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T24	3		T87	7		T102	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T81	7		T41	9		T86	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T109	11		T313	16		T325	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T239	3		T325	13		T233	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T203	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T321	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T270	1		T279	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T258	3		T307	1		T315	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T327	8		T244	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T87	8		T94	3		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T82	15		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T15	2		T18	2		T20	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	1		T88	1		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T150	11		T197	1		T173	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T94	12		T90	1		T91	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T87	9		T94	3		T101	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T89	4		T90	14		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	6		T82	13		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T39	3		T81	28		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T93	15		T82	12		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T56	1		T93	9		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	2		T96	1		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T21	5		T22	11		T195	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T39	3		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	4		T57	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T12	1		T24	8		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T81	1		T79	7		T41	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T321	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T270	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T258	3		T315	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T327	4		T244	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T87	7		T94	3		T215	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T82	12		T121	6		T277	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T15	15		T23	17		T46	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T140	6		T163	10		T130	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T150	13		T102	4		T220	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T94	11		T90	10		T91	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T87	7		T177	12		T128	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T89	3		T90	10		T95	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	3		T82	4		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T39	4		T81	24		T91	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T82	9		T90	2		T105	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	2		T102	14		T103	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T96	17		T296	11		T100	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	9		T195	1		T103	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T213	17		T215	10		T236	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T39	1		T83	4		T218	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T24	3		T87	7		T85	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T81	7		T79	1		T41	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9