Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19243

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

5426

1

T12

1

T14

2

T15

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19027

1

T5

2

T28

1

T32

3

auto[1]

5642

1

T12

2

T15

17

T18

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T246	24		T242	7		T325	3
values[0]	155	1			T39	5		T173	4		T215	23
values[1]	663	1			T39	10		T57	1		T93	15
values[2]	649	1			T12	1		T40	3		T88	1
values[3]	672	1			T12	1		T82	21		T84	4
values[4]	689	1			T81	37		T94	29		T90	24
values[5]	469	1			T14	2		T85	2		T104	6
values[6]	678	1			T12	1		T14	9		T22	20
values[7]	559	1			T22	1		T93	9		T41	7
values[8]	573	1			T57	1		T81	15		T87	25
values[9]	3253	1			T15	17		T18	2		T20	26
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	873	1			T39	8		T57	1		T93	15
values[1]	2764	1			T12	1		T15	17		T18	2
values[2]	789	1			T12	1		T81	37		T82	21
values[3]	648	1			T94	23		T90	24		T115	38
values[4]	495	1			T14	2		T85	2		T104	6
values[5]	680	1			T12	1		T14	9		T22	21
values[6]	502	1			T93	9		T41	7		T83	8
values[7]	649	1			T56	1		T57	1		T81	15
values[8]	741	1			T21	5		T24	11		T81	8
values[9]	236	1			T41	19		T103	7		T139	1
minimum	16292	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T39	2		T79	7		T101	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	3		T57	1		T93	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T40	2		T197	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1375	1			T12	1		T15	17		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T81	17		T82	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T94	4		T102	14		T120	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T94	12		T115	1		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T90	11		T115	16		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T102	5		T213	18		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	2		T85	1		T104	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T14	5		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T22	11		T90	3		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T127	1		T106	1		T164	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T93	1		T41	3		T83	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T57	1		T81	9		T87	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T56	1		T87	8		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	1		T24	9		T82	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T81	8		T87	8		T83	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T41	10		T103	4		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T234	1		T211	3		T166	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16135	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T270	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T39	1		T79	1		T101	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T39	2		T93	14		T82	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	1		T236	11		T209	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1076	1			T20	24		T115	21		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T81	20		T82	11		T84	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T94	2		T102	12		T120	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T94	11		T115	1		T105	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T90	13		T115	20		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T102	5		T213	9		T116	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T85	1		T332	18		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	4		T102	11		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T22	10		T90	17		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T106	4		T164	13		T214	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T93	8		T41	4		T118	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T81	6		T87	2		T94	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T87	7		T150	10		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T21	4		T24	2		T82	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T87	8		T195	1		T173	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T41	9		T103	3		T333	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T166	14		T246	11		T311	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	2		T28	1		T32	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T242	7		T325	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T246	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T193	12		T323	1		T295	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T39	3		T173	1		T215	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	8		T79	7		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T57	1		T93	1		T82	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	2		T88	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T96	6		T115	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	1		T82	10		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T104	7		T102	14		T120	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T81	17		T94	12		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T94	4		T90	11		T115	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T129	1		T116	5		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	2		T85	1		T104	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T14	5		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	10		T141	13		T97	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T127	1		T129	1		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T22	1		T93	1		T41	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T57	1		T81	9		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T87	8		T150	14		T195	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T21	1		T24	9		T82	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1561	1			T15	17		T18	2		T20	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T246	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T323	4		T295	4		T334	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T39	2		T173	3		T215	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	2		T79	1		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T93	14		T82	14		T89	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	1		T101	7		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T115	21		T163	10		T269	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T82	11		T84	3		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T102	12		T120	17		T236	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T81	20		T94	11		T115	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T94	2		T90	13		T115	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T116	2		T144	8		T107	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T85	1		T323	7		T332	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	4		T102	16		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T22	10		T141	7		T203	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T106	4		T164	13		T214	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T93	8		T41	4		T90	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T81	6		T87	2		T94	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T87	7		T150	10		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T21	4		T24	2		T82	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1162	1			T20	24		T87	8		T195	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T39	3		T79	7		T101	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T39	4		T57	1		T93	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	2		T197	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1412	1			T12	1		T15	2		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T81	21		T82	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T94	3		T102	13		T120	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T94	12		T115	2		T105	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T90	14		T115	21		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T102	6		T213	10		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	2		T85	2		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T14	6		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	12		T90	18		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T127	1		T106	5		T164	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T93	9		T41	5		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	1		T81	7		T87	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T56	1		T87	8		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T21	5		T24	8		T82	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T81	1		T87	9		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T41	10		T103	4		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T234	1		T211	1		T166	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16278	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T79	1		T101	9		T128	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T39	1		T82	12		T89	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T40	1		T188	5		T277	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T15	15		T23	17		T46	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T81	16		T82	9		T103	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T94	3		T102	13		T120	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T94	11		T105	5		T107	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T90	10		T115	15		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T102	4		T213	17		T116	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T104	5		T109	15		T219	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	3		T102	14		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T22	9		T90	2		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T164	3		T123	13		T226	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T41	2		T83	7		T85	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T81	8		T87	7		T95	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T87	7		T150	13		T91	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	3		T82	4		T177	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T81	7		T87	7		T83	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T41	9		T103	3		T333	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T211	2		T246	12		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T39	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T270	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T242	1		T325	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T193	1		T323	5		T295	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T39	4		T173	4		T215	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	6		T79	7		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T57	1		T93	15		T82	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T40	2		T88	1		T197	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T96	1		T115	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T82	12		T84	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T104	1		T102	13		T120	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T81	21		T94	12		T115	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T94	3		T90	14		T115	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T129	1		T116	3		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	2		T85	2		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T14	6		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T22	11		T141	8		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T127	1		T129	1		T106	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T22	1		T93	9		T41	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T57	1		T81	7		T87	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T87	8		T150	11		T195	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T21	5		T24	8		T82	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1547	1			T15	2		T18	2		T20	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T242	6		T325	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T193	11		T295	10		T325	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T39	1		T215	10		T273	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T39	4		T79	1		T128	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T82	12		T89	3		T84	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T40	1		T101	9		T270	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T96	5		T115	13		T128	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T82	9		T103	2		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T104	6		T102	13		T120	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T81	16		T94	11		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T94	3		T90	10		T115	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T116	4		T107	11		T109	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T104	5		T140	6		T109	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	3		T102	18		T213	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T22	9		T141	12		T97	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T164	3		T335	2		T158	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T41	2		T83	7		T85	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T81	8		T87	7		T95	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T87	7		T150	13		T177	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T24	3		T82	4		T41	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1176	1			T15	15		T23	17		T46	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9