Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21398

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3271

1

T12

2

T14

9

T21

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19111

1

T5

2

T28

1

T32

3

auto[1]

5558

1

T12

2

T14

9

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	239	1			T12	1		T21	5		T235	1
values[0]	31	1			T236	1		T304	24		T275	6
values[1]	722	1			T24	11		T39	7		T87	16
values[2]	837	1			T93	9		T82	27		T94	23
values[3]	366	1			T56	1		T81	8		T94	9
values[4]	751	1			T12	1		T87	15		T79	8
values[5]	2534	1			T15	17		T18	2		T20	26
values[6]	721	1			T81	37		T93	15		T88	1
values[7]	577	1			T12	1		T22	21		T150	24
values[8]	608	1			T39	5		T81	15		T197	1
values[9]	1008	1			T14	11		T57	1		T87	10
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	818	1			T24	11		T39	7		T82	48
values[1]	682	1			T93	9		T94	23		T218	4
values[2]	402	1			T56	1		T81	8		T94	9
values[3]	2870	1			T12	1		T15	17		T18	2
values[4]	496	1			T39	3		T57	1		T93	15
values[5]	597	1			T81	37		T85	2		T91	13
values[6]	636	1			T12	1		T22	21		T150	24
values[7]	748	1			T39	5		T81	15		T40	3
values[8]	838	1			T14	11		T21	5		T57	1
values[9]	118	1			T12	1		T211	3		T202	13
minimum	16464	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T24	9		T82	13		T91	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T39	6		T82	10		T83	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T93	1		T218	4		T95	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T94	12		T102	14		T96	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T81	8		T94	5		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T56	1		T105	11		T161	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T12	1		T15	17		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T79	7		T84	1		T90	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T57	1		T127	1		T209	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	2		T93	1		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T204	8		T128	9		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T81	17		T85	1		T91	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T22	1		T150	14		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T22	10		T84	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	2		T85	15		T90	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	3		T81	9		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	2		T57	1		T87	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	5		T21	1		T41	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T99	1		T328	1		T284	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T12	1		T211	3		T202	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16199	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T41	3		T141	13		T317	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	2		T82	14		T336	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	1		T82	11		T101	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T93	8		T103	3		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T94	11		T102	12		T120	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T94	4		T195	9		T143	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T105	9		T161	8		T238	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T20	24		T87	7		T173	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T79	1		T84	3		T166	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T209	8		T116	3		T100	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	1		T93	14		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T204	7		T337	4		T198	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T81	20		T85	1		T195	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T150	10		T106	11		T269	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	10		T84	15		T115	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T40	1		T90	17		T86	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	2		T81	6		T115	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T87	2		T82	12		T89	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	4		T21	4		T41	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T99	8		T284	19		T303	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T202	12		T208	2		T273	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T41	4		T141	7		T299	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T107	5		T99	1		T100	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T12	1		T21	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T236	1		T304	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T24	9		T87	8		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T39	6		T82	10		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T93	1		T82	13		T91	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T94	12		T102	14		T96	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T81	8		T94	5		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T56	1		T105	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T87	8		T173	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T79	7		T84	1		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T15	17		T18	2		T20	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	2		T90	11		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T128	9		T129	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T81	17		T93	1		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T22	1		T150	14		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T22	10		T84	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T90	3		T86	1		T103	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T39	3		T81	9		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T14	2		T57	1		T87	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T14	5		T41	10		T90	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T107	3		T99	8		T100	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T21	4		T202	12		T164	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T275	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T24	2		T87	8		T116	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	1		T82	11		T41	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T93	8		T82	14		T103	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T94	11		T102	12		T120	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T94	4		T195	9		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T105	9		T238	3		T99	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T87	7		T173	6		T115	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T79	1		T84	3		T166	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T20	24		T136	10		T137	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T39	1		T205	8		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T116	3		T337	4		T198	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T81	20		T93	14		T85	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T150	10		T204	7		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T22	10		T84	15		T209	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T90	17		T103	11		T215	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T39	2		T81	6		T115	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T87	2		T82	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	4		T41	9		T90	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T24	8		T82	15		T91	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T39	3		T82	12		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T93	9		T218	1		T95	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T94	12		T102	13		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T81	1		T94	6		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T56	1		T105	10		T161	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T12	1		T15	2		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T79	7		T84	4		T90	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T57	1		T127	1		T209	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	3		T93	15		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T204	12		T128	1		T129	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T81	21		T85	2		T91	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T22	1		T150	11		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T22	11		T84	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T40	2		T85	1		T90	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	4		T81	7		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	2		T57	1		T87	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	6		T21	5		T41	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T99	9		T328	1		T284	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T12	1		T211	1		T202	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16372	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T41	5		T141	8		T317	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T24	3		T82	12		T91	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T39	4		T82	9		T83	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T218	3		T95	7		T103	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T94	11		T102	13		T96	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T81	7		T94	3		T83	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T105	10		T161	2		T238	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1074	1			T15	15		T23	17		T46	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T79	1		T90	10		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T209	1		T116	2		T100	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T160	9		T236	14		T277	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T204	3		T128	8		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T81	16		T91	12		T95	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T150	13		T128	9		T130	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	9		T84	13		T104	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	1		T85	14		T90	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	1		T81	8		T96	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T87	7		T82	4		T89	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	3		T41	9		T90	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T284	15		T303	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T211	2		T125	2		T306	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T87	7		T116	4		T203	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T41	2		T141	12		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T107	4		T99	9		T100	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T12	1		T21	5		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T236	1		T304	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T275	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	8		T87	9		T224	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	3		T82	12		T41	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T93	9		T82	15		T91	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T94	12		T102	13		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T81	1		T94	6		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T56	1		T105	10		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T87	8		T173	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T79	7		T84	4		T166	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T15	2		T18	2		T20	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	3		T90	1		T205	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T128	1		T129	1		T97	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T81	21		T93	15		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	1		T150	11		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T22	11		T84	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T90	18		T86	1		T103	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	4		T81	7		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T14	2		T57	1		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T14	6		T41	10		T90	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T107	4		T100	5		T293	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T164	3		T125	2		T255	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T304	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T24	3		T87	7		T140	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	4		T82	9		T41	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T82	12		T91	2		T218	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T94	11		T102	13		T96	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T81	7		T94	3		T83	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T105	10		T241	5		T238	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T87	7		T115	15		T97	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T79	1		T161	12		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T15	15		T23	17		T46	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T90	10		T160	9		T121	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T128	8		T241	10		T116	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T81	16		T91	12		T177	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T150	13		T204	3		T130	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	9		T84	13		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T90	2		T103	2		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T39	1		T81	8		T96	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T87	7		T82	4		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T14	3		T41	9		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9