Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21483

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3186

1

T12

2

T14

9

T21

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19003

1

T5

2

T28

1

T32

3

auto[1]

5666

1

T12

1

T14

11

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	256	1			T21	5		T22	20		T82	17
values[0]	53	1			T103	14		T238	2		T237	33
values[1]	526	1			T88	1		T195	2		T201	2
values[2]	823	1			T81	37		T87	16		T88	1
values[3]	531	1			T12	1		T39	5		T81	8
values[4]	565	1			T12	1		T24	11		T79	8
values[5]	567	1			T39	3		T57	1		T82	27
values[6]	773	1			T41	19		T84	4		T90	24
values[7]	590	1			T22	1		T87	10		T83	8
values[8]	623	1			T12	1		T14	9		T56	1
values[9]	3087	1			T14	2		T15	17		T18	2
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	519	1			T81	37		T88	2		T89	7
values[1]	710	1			T81	8		T87	16		T88	1
values[2]	671	1			T12	2		T39	5		T150	24
values[3]	528	1			T24	11		T39	3		T79	8
values[4]	530	1			T57	1		T82	27		T40	3
values[5]	682	1			T41	19		T84	4		T90	24
values[6]	2732	1			T15	17		T18	2		T20	26
values[7]	725	1			T12	1		T14	9		T39	7
values[8]	868	1			T14	2		T21	5		T93	15
values[9]	174	1			T22	20		T93	9		T115	36
minimum	16530	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T195	1		T201	1		T96	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T81	17		T88	2		T89	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T81	8		T87	8		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T88	1		T85	15		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T39	3		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T150	14		T95	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T39	2		T79	7		T102	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	9		T218	4		T105	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T94	12		T102	14		T96	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T57	1		T82	13		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T84	1		T90	11		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T41	10		T103	12		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T15	17		T18	2		T20	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T22	1		T56	1		T87	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T81	9		T87	8		T82	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T14	5		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	2		T82	5		T94	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T21	1		T93	1		T94	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T246	13		T223	14		T258	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T22	10		T93	1		T115	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16221	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T120	1		T280	9		T265	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T195	1		T201	1		T140	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T81	20		T89	2		T214	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T87	8		T206	2		T166	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T102	5		T103	3		T161	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T39	2		T41	4		T173	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T150	10		T238	3		T123	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	1		T79	1		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T24	2		T105	19		T277	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T94	11		T102	12		T202	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T82	14		T40	1		T101	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T84	3		T90	13		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	9		T103	3		T204	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T20	24		T136	10		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T87	2		T161	8		T236	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T81	6		T87	7		T82	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	4		T39	1		T173	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T82	12		T94	2		T101	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T21	4		T93	14		T94	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T246	11		T258	4		T278	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T22	10		T93	8		T115	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T280	8		T265	16		T338	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T82	5		T94	4		T83	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T21	1		T22	10		T177	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T103	3		T238	1		T237	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T195	1		T201	1		T96	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T88	1		T120	1		T97	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T87	8		T192	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T81	17		T88	1		T89	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	3		T81	8		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T88	1		T95	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	1		T79	7		T41	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	9		T150	14		T218	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	2		T94	12		T102	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T57	1		T82	13		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T84	1		T90	11		T96	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T41	10		T103	12		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T105	11		T141	13		T128	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	1		T87	8		T83	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T81	9		T87	8		T82	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T14	5		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T14	2		T15	17		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T93	2		T94	1		T84	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T82	12		T94	2		T246	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T21	4		T22	10		T118	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T103	11		T238	1		T237	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T338	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T195	1		T201	1		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T208	1		T283	2		T280	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T87	8		T166	14		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T81	20		T89	2		T102	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	2		T173	3		T206	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T143	2		T238	3		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T79	1		T41	4		T215	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	2		T150	10		T105	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	1		T94	11		T102	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T82	14		T40	1		T101	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T84	3		T90	13		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T41	9		T103	3		T204	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T105	9		T141	7		T116	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T87	2		T161	8		T236	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T81	6		T87	7		T82	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	4		T39	1		T173	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T20	24		T101	7		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T93	22		T94	2		T84	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T195	2		T201	2		T96	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T81	21		T88	2		T89	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T81	1		T87	9		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T88	1		T85	1		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T39	4		T41	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T150	11		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T39	3		T79	7		T102	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	8		T218	1		T105	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T94	12		T102	13		T96	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T57	1		T82	15		T40	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T84	4		T90	14		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T41	10		T103	4		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T15	2		T18	2		T20	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T22	1		T56	1		T87	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T81	7		T87	8		T82	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T14	6		T39	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	2		T82	13		T94	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T21	5		T93	15		T94	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T246	12		T223	1		T258	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T22	11		T93	9		T115	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16372	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T120	1		T280	9		T265	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T96	5		T140	9		T239	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T81	16		T89	3		T97	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T81	7		T87	7		T209	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T85	14		T102	4		T103	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	1		T41	2		T104	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	13		T95	7		T104	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T79	1		T102	14		T215	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T24	3		T218	3		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T94	11		T102	13		T96	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T82	12		T40	1		T241	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T90	10		T160	9		T339	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T41	9		T103	11		T204	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T15	15		T23	17		T46	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T87	7		T83	7		T95	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T81	8		T87	7		T82	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	3		T39	4		T115	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T82	4		T94	3		T83	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T84	13		T90	2		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T246	12		T223	13		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T22	9		T115	15		T284	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T103	2		T188	5		T130	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T280	8		T340	17		T341	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T82	13		T94	3		T83	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T21	5		T22	11		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T103	12		T238	2		T237	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T338	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T195	2		T201	2		T96	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T88	1		T120	1		T97	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T87	9		T192	1		T166	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T81	21		T88	1		T89	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	4		T81	1		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T88	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T79	7		T41	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T24	8		T150	11		T218	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	3		T94	12		T102	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T57	1		T82	15		T40	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T84	4		T90	14		T96	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T41	10		T103	4		T224	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T105	10		T141	8		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T22	1		T87	3		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T81	7		T87	8		T82	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T14	6		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T14	2		T15	2		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	414	1			T93	24		T94	3		T84	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T82	4		T94	3		T83	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T22	9		T177	7		T271	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T103	2		T237	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T96	5		T140	9		T239	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T97	1		T280	8		T281	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T87	7		T209	1		T116	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T81	16		T89	3		T85	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	1		T81	7		T277	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T95	7		T104	6		T177	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T79	1		T41	2		T104	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T24	3		T150	13		T218	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T94	11		T102	27		T220	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T82	12		T40	1		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T90	10		T96	17		T160	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T41	9		T103	11		T204	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T105	10		T141	12		T128	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T87	7		T83	7		T161	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T81	8		T87	7		T82	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T14	3		T39	4		T95	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T15	15		T23	17		T46	30
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T84	13		T90	2		T91	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9