Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19264

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

5405

1

T12

1

T14

2

T15

17

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19003

1

T5

2

T28

1

T32

3

auto[1]

5666

1

T12

2

T15

17

T18

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	213	1			T86	1		T95	13		T173	7
values[0]	135	1			T39	7		T173	4		T215	23
values[1]	613	1			T39	8		T57	1		T93	15
values[2]	676	1			T12	1		T40	3		T197	1
values[3]	728	1			T12	1		T82	21		T88	1
values[4]	675	1			T81	37		T94	29		T90	24
values[5]	480	1			T14	2		T85	2		T104	6
values[6]	683	1			T12	1		T14	9		T22	20
values[7]	566	1			T22	1		T93	9		T41	7
values[8]	543	1			T56	1		T57	1		T87	25
values[9]	3082	1			T15	17		T18	2		T20	26
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	522	1			T39	8		T93	15		T82	27
values[1]	2867	1			T12	1		T15	17		T18	2
values[2]	747	1			T12	1		T81	37		T82	21
values[3]	592	1			T94	23		T90	24		T115	38
values[4]	532	1			T14	2		T85	2		T104	6
values[5]	712	1			T12	1		T14	9		T22	21
values[6]	444	1			T93	9		T41	7		T83	8
values[7]	634	1			T56	1		T57	1		T81	15
values[8]	826	1			T21	5		T24	11		T81	8
values[9]	192	1			T41	19		T95	13		T139	1
minimum	16601	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	2		T101	10		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	3		T93	1		T82	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	2		T197	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1432	1			T12	1		T15	17		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T81	17		T82	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T94	4		T102	14		T120	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T94	12		T115	1		T105	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T90	11		T115	16		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T102	5		T213	18		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	2		T85	1		T104	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	1		T14	5		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T22	11		T85	15		T90	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T127	1		T241	11		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T93	1		T41	3		T83	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T57	1		T81	9		T87	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T56	1		T87	8		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T21	1		T24	9		T82	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T81	8		T87	8		T83	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T41	10		T139	1		T333	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T95	13		T234	1		T211	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16214	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T57	1		T84	14		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	1		T101	7		T143	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T39	2		T93	14		T82	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	1		T236	11		T209	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1105	1			T20	24		T115	21		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T81	20		T82	11		T84	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T94	2		T102	12		T120	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T94	11		T115	1		T105	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T90	13		T115	20		T214	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T102	5		T213	9		T116	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T85	1		T332	18		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	4		T102	11		T105	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T22	10		T90	17		T204	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T106	4		T164	13		T214	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T93	8		T41	4		T116	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T81	6		T87	2		T94	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T87	7		T150	10		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	4		T24	2		T82	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T87	8		T195	1		T173	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T41	9		T333	12		T283	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T246	11		T311	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T84	15		T209	15		T238	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T177	13		T96	12		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T86	1		T95	13		T173	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T39	6		T334	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T173	1		T215	11		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T39	2		T79	7		T128	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	3		T57	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	2		T197	1		T101	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	1		T86	5		T104	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T82	10		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T102	14		T120	19		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T81	17		T94	12		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T94	4		T90	11		T115	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T129	1		T116	5		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	2		T85	1		T104	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	1		T14	5		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T22	10		T85	15		T97	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T127	1		T241	11		T164	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	1		T93	1		T41	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	1		T87	8		T94	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	1		T87	8		T150	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T21	1		T24	9		T81	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1527	1			T15	17		T18	2		T20	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T277	3		T333	12		T208	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T173	6		T161	8		T107	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T39	1		T334	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T173	3		T215	12		T209	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T39	1		T79	1		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	2		T93	14		T82	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	1		T101	7		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T86	9		T115	21		T163	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T82	11		T84	3		T103	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T102	12		T120	17		T236	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T81	20		T94	11		T115	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T94	2		T90	13		T115	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T116	2		T144	8		T107	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T85	1		T323	7		T332	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	4		T102	16		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T22	10		T203	13		T208	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T164	13		T214	8		T335	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T93	8		T41	4		T90	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T87	2		T94	2		T101	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T87	7		T150	10		T195	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T21	4		T24	2		T81	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1106	1			T20	24		T87	8		T195	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T39	3		T101	8		T143	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	4		T93	15		T82	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T40	2		T197	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1445	1			T12	1		T15	2		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	1		T81	21		T82	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T94	3		T102	13		T120	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T94	12		T115	2		T105	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T90	14		T115	21		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T102	6		T213	10		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	2		T85	2		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	1		T14	6		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T22	12		T85	1		T90	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T127	1		T241	1		T106	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T93	9		T41	5		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T57	1		T81	7		T87	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	1		T87	8		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T21	5		T24	8		T82	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T81	1		T87	9		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T41	10		T139	1		T333	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T95	1		T234	1		T211	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16375	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T57	1		T84	16		T127	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T101	9		T121	6		T270	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T39	1		T82	12		T89	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T40	1		T188	5		T220	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1092	1			T15	15		T23	17		T46	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T81	16		T82	9		T103	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T94	3		T102	13		T120	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T94	11		T105	5		T107	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T90	10		T115	15		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T102	4		T213	17		T116	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T104	5		T109	15		T219	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	3		T102	14		T141	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T22	9		T85	14		T90	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T241	10		T164	3		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T41	2		T83	7		T218	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T81	8		T87	7		T101	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T87	7		T150	13		T91	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	3		T82	4		T95	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T81	7		T87	7		T83	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T41	9		T333	9		T244	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T95	12		T211	2		T246	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T39	4		T79	1		T128	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T84	13		T238	1		T342	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T177	1		T96	1		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T86	1		T95	1		T173	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T39	3		T334	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T173	4		T215	13		T209	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T39	3		T79	7		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	4		T57	1		T93	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T40	2		T197	1		T101	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T86	10		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T82	12		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T102	13		T120	18		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T81	21		T94	12		T115	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T94	3		T90	14		T115	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	1		T116	3		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	2		T85	2		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T14	6		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T22	11		T85	1		T97	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T127	1		T241	1		T164	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T22	1		T93	9		T41	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T57	1		T87	3		T94	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T56	1		T87	8		T150	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T21	5		T24	8		T81	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1472	1			T15	2		T18	2		T20	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T177	12		T96	11		T277	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T95	12		T161	2		T107	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T39	4		T334	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T215	10		T273	14		T322	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T79	1		T128	9		T121	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T39	1		T82	12		T89	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T40	1		T101	9		T188	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T86	4		T104	6		T96	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T82	9		T103	2		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T102	13		T120	18		T236	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T81	16		T94	11		T105	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T94	3		T90	10		T115	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T116	4		T107	11		T109	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T104	5		T109	15		T219	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	3		T102	18		T213	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T22	9		T85	14		T97	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T241	10		T164	3		T335	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	2		T83	7		T90	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T87	7		T95	7		T101	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T87	7		T150	13		T195	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	3		T81	8		T82	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1161	1			T15	15		T23	17		T46	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9