Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T22	11		T56	1		T86	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T39	3		T57	1		T94	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T81	7		T163	2		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	4		T87	8		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T177	1		T224	1		T115	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T82	13		T41	10		T83	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T93	15		T79	7		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T39	3		T87	3		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	8		T57	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T150	11		T88	1		T84	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T88	1		T90	1		T195	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T93	9		T82	15		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T12	1		T15	2		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T218	1		T95	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	8		T104	1		T102	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T87	9		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T22	1		T94	3		T84	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	1		T21	5		T82	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T222	1		T208	2		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T145	1		T226	6		T227	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16288	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T228	1		T200	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T22	9		T128	8		T107	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T39	4		T94	3		T104	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T81	8		T223	13		T130	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	1		T87	7		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T177	7		T115	13		T140	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T82	4		T41	9		T83	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T79	1		T215	2		T238	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T87	7		T121	6		T107	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T24	3		T102	4		T213	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	13		T84	13		T91	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T90	10		T195	1		T209	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T82	12		T83	4		T101	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T15	15		T23	17		T46	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T218	3		T95	12		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	3		T104	5		T102	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T87	7		T140	9		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T85	14		T161	10		T241	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T82	9		T90	10		T91	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T242	6		T232	11		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T226	3		T244	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T245	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T177	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T115	2		T125	1		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T221	1		T233	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T22	11		T56	1		T86	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T39	3		T57	1		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T81	7		T120	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T39	4		T40	2		T94	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T93	15		T177	1		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T87	8		T82	13		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T79	7		T115	22		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T39	3		T87	3		T41	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T24	8		T57	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	11		T88	1		T84	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T81	21		T88	1		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T82	15		T101	4		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T81	1		T173	7		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T93	9		T83	1		T218	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T12	1		T14	2		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T140	11		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T14	6		T22	1		T94	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T12	1		T21	5		T87	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T177	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T125	15		T232	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T233	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T22	9		T128	8		T107	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	4		T104	6		T236	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T81	8		T130	9		T237	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T39	1		T40	1		T94	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T177	7		T116	2		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T87	7		T82	4		T83	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T79	1		T115	13		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T87	7		T41	9		T96	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T24	3		T103	3		T204	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T150	13		T84	13		T91	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T81	16		T90	10		T195	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T82	12		T101	4		T100	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T81	7		T239	3		T120	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T83	4		T218	3		T95	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T15	15		T23	17		T46	30
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T140	9		T163	10		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T14	3		T85	14		T104	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T87	7		T82	9		T90	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9