Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24669

1

T5

2

T28

1

T32

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21341

1

T5

2

T28

1

T32

3

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T12

2

T21

5

T22

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19111

1

T5

2

T28

1

T32

3

auto[1]

5558

1

T12

1

T14

9

T15

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20678

1

T12

3

T13

153

T14

17

auto[1]

3991

1

T5

2

T28

1

T32

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T247	10		-	-		-	-
values[0]	54	1			T118	14		T109	16		T248	9
values[1]	491	1			T39	5		T87	16		T94	3
values[2]	604	1			T12	1		T81	8		T82	27
values[3]	609	1			T22	1		T56	1		T39	3
values[4]	657	1			T57	1		T81	37		T87	15
values[5]	2792	1			T15	17		T18	2		T20	26
values[6]	788	1			T14	2		T24	11		T39	7
values[7]	441	1			T57	1		T93	15		T40	3
values[8]	679	1			T12	1		T14	9		T22	20
values[9]	1269	1			T12	1		T21	5		T93	9
minimum	16275	1			T5	2		T28	1		T32	3

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	680	1			T39	5		T87	16		T82	27
values[1]	608	1			T39	3		T81	8		T102	26
values[2]	650	1			T12	1		T22	1		T56	1
values[3]	2729	1			T15	17		T18	2		T20	26
values[4]	643	1			T83	5		T101	17		T102	26
values[5]	799	1			T14	2		T24	11		T39	7
values[6]	473	1			T82	21		T40	3		T94	23
values[7]	822	1			T14	9		T22	20		T82	17
values[8]	816	1			T12	2		T21	5		T93	9
values[9]	172	1			T91	3		T103	7		T193	12
minimum	16277	1			T5	2		T28	1		T32	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

3485

1

T14

3

T15

15

T22

9

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T87	8		T94	1		T88	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	3		T82	13		T89	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T206	1		T127	1		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T39	2		T81	8		T102	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T22	1		T79	7		T90	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T56	1		T84	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T15	17		T18	2		T20	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T81	26		T197	1		T84	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T83	5		T102	14		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T101	10		T141	13		T163	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	2		T24	9		T41	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T39	6		T57	1		T93	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T85	15		T90	11		T115	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T82	10		T40	2		T94	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	5		T91	13		T195	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	10		T82	5		T105	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T150	14		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	1		T21	1		T93	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T91	3		T125	3		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T103	4		T193	12		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T231	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T87	8		T94	2		T115	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	2		T82	14		T89	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T206	2		T208	2		T123	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	1		T102	11		T115	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T79	1		T90	17		T209	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T84	3		T195	1		T105	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T20	24		T87	7		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T81	26		T84	15		T90	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T102	12		T161	12		T236	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T101	7		T141	7		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	2		T41	4		T213	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	1		T93	14		T94	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T115	20		T116	10		T123	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T82	11		T40	1		T94	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	4		T195	9		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T22	10		T82	12		T105	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T150	10		T239	4		T215	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T21	4		T93	8		T87	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T251	6		T252	1		T253	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T103	3		T214	12		T207	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T231	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T247	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T118	1		T248	9		T254	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T109	16		T255	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T87	8		T94	1		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T39	3		T89	5		T256	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T206	1		T129	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	1		T81	8		T82	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T22	1		T79	7		T104	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T56	1		T39	2		T195	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T57	1		T87	8		T90	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T81	17		T197	1		T84	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T15	17		T18	2		T20	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T81	9		T94	4		T90	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	2		T24	9		T83	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T39	6		T82	10		T41	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T41	3		T85	15		T90	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T57	1		T93	1		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T14	5		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T22	10		T94	12		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T91	3		T86	1		T95	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T12	1		T21	1		T93	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16129	1			T13	153		T14	10		T16	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T247	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T118	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T87	8		T94	2		T115	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	2		T89	2		T100	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T206	2		T257	15		T123	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T82	14		T84	3		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T79	1		T209	12		T130	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	1		T195	1		T105	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T87	7		T90	17		T215	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T81	20		T84	15		T173	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T20	24		T102	12		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T81	6		T94	2		T90	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T24	2		T213	9		T103	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T39	1		T82	11		T41	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T41	4		T115	20		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T93	14		T40	1		T101	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	4		T150	10		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	10		T94	11		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T102	5		T239	4		T215	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T21	4		T93	8		T87	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T32	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T87	9		T94	3		T88	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	4		T82	15		T89	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T206	3		T127	1		T249	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	3		T81	1		T102	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T22	1		T79	7		T90	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T56	1		T84	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T15	2		T18	2		T20	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T81	28		T197	1		T84	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T83	1		T102	13		T161	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T101	8		T141	8		T163	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	2		T24	8		T41	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T39	3		T57	1		T93	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T85	1		T90	1		T115	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T82	12		T40	2		T94	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T14	6		T91	1		T195	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T22	11		T82	13		T105	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T12	1		T150	11		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T21	5		T93	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T91	1		T125	1		T250	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T103	4		T193	1		T214	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T231	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T87	7		T115	13		T120	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T39	1		T82	12		T89	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T123	11		T258	3		T259	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T81	7		T102	14		T177	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T79	1		T90	2		T104	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T105	5		T140	6		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T15	15		T23	17		T46	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T81	24		T84	13		T90	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T83	4		T102	13		T236	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T101	9		T141	12		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T24	3		T41	2		T213	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T39	4		T94	3		T41	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T85	14		T90	10		T115	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T82	9		T40	1		T94	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	3		T91	12		T195	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T22	9		T82	4		T128	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T150	13		T95	7		T239	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T87	7		T83	7		T218	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T91	2		T125	2		T251	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T103	3		T193	11		T207	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T247	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T118	14		T248	1		T254	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T109	1		T255	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T87	9		T94	3		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T39	4		T89	4		T256	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T206	3		T129	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T81	1		T82	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T22	1		T79	7		T104	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T56	1		T39	3		T195	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T57	1		T87	8		T90	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T81	21		T197	1		T84	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T15	2		T18	2		T20	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T81	7		T94	3		T90	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	2		T24	8		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T39	3		T82	12		T41	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T41	5		T85	1		T90	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T57	1		T93	15		T40	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T14	6		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T22	11		T94	12		T105	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T91	1		T86	1		T95	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T12	1		T21	5		T93	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16275	1			T5	2		T28	1		T32	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T247	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T248	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T109	15		T255	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T87	7		T115	13		T120	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T39	1		T89	3		T260	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T123	11		T261	12		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T81	7		T82	12		T104	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T79	1		T104	6		T130	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T96	22		T105	5		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T87	7		T90	2		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T81	16		T84	13		T241	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T15	15		T23	17		T46	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T81	8		T94	3		T90	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T24	3		T83	4		T213	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	4		T82	9		T41	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T41	2		T85	14		T90	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T40	1		T101	4		T105	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	3		T150	13		T91	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T22	9		T94	11		T128	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T91	2		T95	19		T102	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T87	7		T82	4		T83	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21184

1

T5

2

T28

1

T32

3

auto[1]

auto[0]

3485

1

T14

3

T15

15

T22

9